sun4i_a10_ccu.c revision 1.13
1 /* $NetBSD: sun4i_a10_ccu.c,v 1.13 2021/01/18 02:35:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.13 2021/01/18 02:35:49 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun4i_a10_ccu.h> 42 #include <arm/sunxi/sun7i_a20_ccu.h> 43 44 #define PLL1_CFG_REG 0x000 45 #define PLL2_CFG_REG 0x008 46 #define PLL3_CFG_REG 0x010 47 #define PLL5_CFG_REG 0x020 48 #define PLL6_CFG_REG 0x028 49 #define PLL7_CFG_REG 0x030 50 #define OSC24M_CFG_REG 0x050 51 #define CPU_AHB_APB0_CFG_REG 0x054 52 #define APB1_CLK_DIV_REG 0x058 53 #define AHB_GATING_REG0 0x060 54 #define AHB_GATING_REG1 0x064 55 #define APB0_GATING_REG 0x068 56 #define APB1_GATING_REG 0x06c 57 #define NAND_SCLK_CFG_REG 0x080 58 #define SD0_SCLK_CFG_REG 0x088 59 #define SD1_SCLK_CFG_REG 0x08c 60 #define SD2_SCLK_CFG_REG 0x090 61 #define SD3_SCLK_CFG_REG 0x094 62 #define SPI0_CLK_CFG_REG 0x0a0 63 #define SPI1_CLK_CFG_REG 0x0a4 64 #define SPI2_CLK_CFG_REG 0x0a8 65 #define SATA_CFG_REG 0x0c8 66 #define USBPHY_CFG_REG 0x0cc 67 #define SPI3_CLK_CFG_REG 0x0d4 68 #define DRAM_GATING_REG 0x100 69 #define BE0_CFG_REG 0x104 70 #define BE1_CFG_REG 0x108 71 #define FE0_CFG_REG 0x10c 72 #define FE1_CFG_REG 0x110 73 #define MP_CFG_REG 0x114 74 #define LCD0CH0_CFG_REG 0x118 75 #define LCD1CH0_CFG_REG 0x11c 76 #define LCD0CH1_CFG_REG 0x12c 77 #define LCD1CH1_CFG_REG 0x130 78 #define CSI_CFG_REG 0x134 79 #define VE_CFG_REG 0x13c 80 #define AUDIO_CODEC_SCLK_CFG_REG 0x140 81 #define LVDS_CFG_REG 0x14c 82 #define HDMI_CLOCK_CFG_REG 0x150 83 #define MALI_CLOCK_CFG_REG 0x154 84 #define IEP_SCLK_CFG_REG 0x160 85 #define CLK_OUTA_REG 0x1f0 86 #define CLK_OUTB_REG 0x1f4 87 88 static int sun4i_a10_ccu_match(device_t, cfdata_t, void *); 89 static void sun4i_a10_ccu_attach(device_t, device_t, void *); 90 91 enum sun4i_a10_ccu_type { 92 CCU_A10 = 1, 93 CCU_A20, 94 }; 95 96 static const struct device_compatible_entry compat_data[] = { 97 { .compat = "allwinner,sun4i-a10-ccu", .value = CCU_A10 }, 98 { .compat = "allwinner,sun7i-a20-ccu", .value = CCU_A20 }, 99 100 { 0 } 101 }; 102 103 CFATTACH_DECL_NEW(sunxi_a10_ccu, sizeof(struct sunxi_ccu_softc), 104 sun4i_a10_ccu_match, sun4i_a10_ccu_attach, NULL, NULL); 105 106 static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = { 107 SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0), 108 SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1), 109 SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2), 110 SUNXI_CCU_RESET(A10_RST_DE_BE0, BE0_CFG_REG, 30), 111 SUNXI_CCU_RESET(A10_RST_DE_BE1, BE1_CFG_REG, 30), 112 SUNXI_CCU_RESET(A10_RST_DE_FE0, FE0_CFG_REG, 30), 113 SUNXI_CCU_RESET(A10_RST_DE_FE1, FE1_CFG_REG, 30), 114 SUNXI_CCU_RESET(A10_RST_DE_MP, MP_CFG_REG, 30), 115 SUNXI_CCU_RESET(A10_RST_TCON0, LCD0CH0_CFG_REG, 30), 116 SUNXI_CCU_RESET(A10_RST_TCON1, LCD1CH0_CFG_REG, 30), 117 SUNXI_CCU_RESET(A10_RST_LVDS, LVDS_CFG_REG, 0), 118 }; 119 120 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 121 static const char *axi_parents[] = { "cpu" }; 122 static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" }; 123 static const char *apb0_parents[] = { "ahb" }; 124 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; 125 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr_other" }; 126 static const char *sata_parents[] = { "pll6_periph_sata", "external" }; 127 static const char *de_parents[] = { "pll_video0", "pll_video1", "pll_ddr_other" }; 128 static const char *lcd_parents[] = { "pll_video0", "pll_video1", "pll_video0x2", "pll_video1x2" }; 129 static const char *out_parents[] = { "losc" /* really OSC24MHz/750 */, "losc", "osc24m" }; 130 131 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = { 132 { 1008000000, 21, 1, 0, 0 }, 133 { 960000000, 20, 1, 0, 0 }, 134 { 912000000, 19, 1, 0, 0 }, 135 { 864000000, 18, 1, 0, 0 }, 136 { 720000000, 30, 0, 0, 0 }, 137 { 624000000, 26, 0, 0, 0 }, 138 { 528000000, 22, 0, 0, 0 }, 139 { 312000000, 13, 0, 0, 0 }, 140 { 144000000, 12, 0, 0, 1 }, 141 { 0 } 142 }; 143 144 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = { 145 { 24576000, 86, 0, 21, 4 }, 146 { 0 } 147 }; 148 149 /* 150 * some special cases 151 * hardcode lcd0 (tcon0) to pll3 and lcd1 (tcon1) to pll7. 152 * compute pll rate based on desired pixel clock 153 */ 154 155 static int sun4i_a10_ccu_lcd0ch0_set_rate(struct sunxi_ccu_softc *, 156 struct sunxi_ccu_clk *, u_int); 157 static int sun4i_a10_ccu_lcd1ch0_set_rate(struct sunxi_ccu_softc *, 158 struct sunxi_ccu_clk *, u_int); 159 static u_int sun4i_a10_ccu_lcd0ch0_round_rate(struct sunxi_ccu_softc *, 160 struct sunxi_ccu_clk *, u_int); 161 static u_int sun4i_a10_ccu_lcd1ch0_round_rate(struct sunxi_ccu_softc *, 162 struct sunxi_ccu_clk *, u_int); 163 static int sun4i_a10_ccu_lcd0ch1_set_rate(struct sunxi_ccu_softc *, 164 struct sunxi_ccu_clk *, u_int); 165 static int sun4i_a10_ccu_lcd1ch1_set_rate(struct sunxi_ccu_softc *, 166 struct sunxi_ccu_clk *, u_int); 167 168 static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = { 169 SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc", 170 OSC24M_CFG_REG, 0), 171 172 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_CORE, "pll_core", "osc24m", 173 PLL1_CFG_REG, /* reg */ 174 __BITS(12,8), /* n */ 175 __BITS(5,4), /* k */ 176 __BITS(1,0), /* m */ 177 __BITS(17,16), /* p */ 178 __BIT(31), /* enable */ 179 0, /* lock */ 180 sun4i_a10_pll1_table, /* table */ 181 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT | 182 SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE | SUNXI_CCU_NKMP_SCALE_CLOCK), 183 184 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 185 PLL2_CFG_REG, /* reg */ 186 __BITS(14,8), /* n */ 187 0, /* k */ 188 __BITS(4,0), /* m */ 189 __BITS(29,26), /* p */ 190 __BIT(31), /* enable */ 191 0, /* lock */ 192 sun4i_a10_ac_dig_table, /* table */ 193 0), 194 195 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_BASE, "pll_periph_base", "osc24m", 196 PLL6_CFG_REG, /* reg */ 197 __BITS(12,8), /* n */ 198 __BITS(5,4), /* k */ 199 0, /* m */ 200 0, /* p */ 201 __BIT(31), /* enable */ 202 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 203 204 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_PERIPH, "pll_periph", "pll_periph_base", 205 2, 1), 206 207 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_SATA, "pll_periph_sata", "pll_periph_base", 208 PLL6_CFG_REG, /* reg */ 209 0, /* n */ 210 0, /* k */ 211 __BITS(1,0), /* m */ 212 0, /* p */ 213 __BIT(14), /* enable */ 214 0), 215 216 SUNXI_CCU_DIV_GATE(A10_CLK_SATA, "sata", sata_parents, 217 SATA_CFG_REG, /* reg */ 218 0, /* div */ 219 __BIT(24), /* sel */ 220 __BIT(31), /* enable */ 221 0), 222 223 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR_BASE, "pll_ddr_other", "osc24m", 224 PLL5_CFG_REG, /* reg */ 225 __BITS(12, 8), /* n */ 226 __BITS(5,4), /* k */ 227 0, /* m */ 228 __BITS(17,16), /* p */ 229 __BIT(31), /* enable */ 230 SUNXI_CCU_NKMP_FACTOR_N_EXACT | SUNXI_CCU_NKMP_FACTOR_P_POW2), 231 232 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR, "pll_ddr", "osc24m", 233 PLL5_CFG_REG, /* reg */ 234 __BITS(12, 8), /* n */ 235 __BITS(5,4), /* k */ 236 __BITS(1,0), /* m */ 237 0, /* p */ 238 __BIT(31), /* enable */ 239 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 240 241 SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents, 242 CPU_AHB_APB0_CFG_REG, /* reg */ 243 0, /* div */ 244 __BITS(17,16), /* sel */ 245 SUNXI_CCU_DIV_SET_RATE_PARENT), 246 247 SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents, 248 CPU_AHB_APB0_CFG_REG, /* reg */ 249 __BITS(1,0), /* div */ 250 0, /* sel */ 251 0), 252 253 SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents, 254 CPU_AHB_APB0_CFG_REG, /* reg */ 255 __BITS(5,4), /* div */ 256 __BITS(7,6), /* sel */ 257 SUNXI_CCU_DIV_POWER_OF_TWO), 258 259 SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents, 260 CPU_AHB_APB0_CFG_REG, /* reg */ 261 __BITS(9,8), /* div */ 262 0, /* sel */ 263 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 264 265 SUNXI_CCU_NM(A10_CLK_APB1, "apb1", apb1_parents, 266 APB1_CLK_DIV_REG, /* reg */ 267 __BITS(17,16), /* n */ 268 __BITS(4,0), /* m */ 269 __BITS(25,24), /* sel */ 270 0, /* enable */ 271 SUNXI_CCU_NM_POWER_OF_TWO), 272 273 SUNXI_CCU_NM(A10_CLK_NAND, "nand", mod_parents, 274 NAND_SCLK_CFG_REG, /* reg */ 275 __BITS(17,16), /* n */ 276 __BITS(3,0), /* m */ 277 __BITS(25,24), /* sel */ 278 __BIT(31), /* enable */ 279 SUNXI_CCU_NM_POWER_OF_TWO), 280 281 SUNXI_CCU_NM(A10_CLK_SPI0, "spi0", mod_parents, 282 SPI0_CLK_CFG_REG, /* reg */ 283 __BITS(17,16), /* n */ 284 __BITS(3,0), /* m */ 285 __BITS(25,24), /* sel */ 286 __BIT(31), /* enable */ 287 SUNXI_CCU_NM_POWER_OF_TWO), 288 289 SUNXI_CCU_NM(A10_CLK_SPI1, "spi1", mod_parents, 290 SPI1_CLK_CFG_REG, /* reg */ 291 __BITS(17,16), /* n */ 292 __BITS(3,0), /* m */ 293 __BITS(25,24), /* sel */ 294 __BIT(31), /* enable */ 295 SUNXI_CCU_NM_POWER_OF_TWO), 296 297 SUNXI_CCU_NM(A10_CLK_SPI2, "spi2", mod_parents, 298 SPI2_CLK_CFG_REG, /* reg */ 299 __BITS(17,16), /* n */ 300 __BITS(3,0), /* m */ 301 __BITS(25,24), /* sel */ 302 __BIT(31), /* enable */ 303 SUNXI_CCU_NM_POWER_OF_TWO), 304 305 SUNXI_CCU_NM(A10_CLK_SPI3, "spi3", mod_parents, 306 SPI3_CLK_CFG_REG, /* reg */ 307 __BITS(17,16), /* n */ 308 __BITS(3,0), /* m */ 309 __BITS(25,24), /* sel */ 310 __BIT(31), /* enable */ 311 SUNXI_CCU_NM_POWER_OF_TWO), 312 313 SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents, 314 SD0_SCLK_CFG_REG, /* reg */ 315 __BITS(17,16), /* n */ 316 __BITS(3,0), /* m */ 317 __BITS(25,24), /* sel */ 318 __BIT(31), /* enable */ 319 SUNXI_CCU_NM_POWER_OF_TWO), 320 SUNXI_CCU_PHASE(A10_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 321 SD0_SCLK_CFG_REG, __BITS(22,20)), 322 SUNXI_CCU_PHASE(A10_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 323 SD0_SCLK_CFG_REG, __BITS(10,8)), 324 SUNXI_CCU_NM(A10_CLK_MMC1, "mmc1", mod_parents, 325 SD1_SCLK_CFG_REG, /* reg */ 326 __BITS(17,16), /* n */ 327 __BITS(3,0), /* m */ 328 __BITS(25,24), /* sel */ 329 __BIT(31), /* enable */ 330 SUNXI_CCU_NM_POWER_OF_TWO), 331 SUNXI_CCU_PHASE(A10_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 332 SD1_SCLK_CFG_REG, __BITS(22,20)), 333 SUNXI_CCU_PHASE(A10_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 334 SD1_SCLK_CFG_REG, __BITS(10,8)), 335 SUNXI_CCU_NM(A10_CLK_MMC2, "mmc2", mod_parents, 336 SD2_SCLK_CFG_REG, /* reg */ 337 __BITS(17,16), /* n */ 338 __BITS(3,0), /* m */ 339 __BITS(25,24), /* sel */ 340 __BIT(31), /* enable */ 341 SUNXI_CCU_NM_POWER_OF_TWO), 342 SUNXI_CCU_PHASE(A10_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 343 SD2_SCLK_CFG_REG, __BITS(22,20)), 344 SUNXI_CCU_PHASE(A10_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 345 SD2_SCLK_CFG_REG, __BITS(10,8)), 346 SUNXI_CCU_NM(A10_CLK_MMC3, "mmc3", mod_parents, 347 SD3_SCLK_CFG_REG, /* reg */ 348 __BITS(17,16), /* n */ 349 __BITS(3,0), /* m */ 350 __BITS(25,24), /* sel */ 351 __BIT(31), /* enable */ 352 SUNXI_CCU_NM_POWER_OF_TWO), 353 SUNXI_CCU_PHASE(A10_CLK_MMC3_SAMPLE, "mmc3_sample", "mmc3", 354 SD3_SCLK_CFG_REG, __BITS(22,20)), 355 SUNXI_CCU_PHASE(A10_CLK_MMC3_OUTPUT, "mmc3_output", "mmc3", 356 SD3_SCLK_CFG_REG, __BITS(10,8)), 357 358 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO0, "pll_video0", "osc24m", 359 PLL3_CFG_REG, /* reg */ 360 __BITS(7,0), /* m */ 361 9, /* m_min */ 362 127, /* m_max */ 363 __BIT(15), /* div_en */ 364 __BIT(14), /* frac_sel */ 365 270000000, 297000000, /* frac values */ 366 0, /* prediv */ 367 8, /* prediv_val */ 368 __BIT(31), /* enable */ 369 0), 370 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO1, "pll_video1", "osc24m", 371 PLL7_CFG_REG, /* reg */ 372 __BITS(7,0), /* m */ 373 9, /* m_min */ 374 127, /* m_max */ 375 __BIT(15), /* div_en */ 376 __BIT(14), /* frac_sel */ 377 270000000, 297000000, /* frac values */ 378 0, /* prediv */ 379 8, /* prediv_val */ 380 __BIT(31), /* enable */ 381 0), 382 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO0_2X, 383 "pll_video0x2", "pll_video0", 384 1, 2), 385 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO1_2X, 386 "pll_video1x2", "pll_video1", 387 1, 2), 388 389 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE0, "debe0-mod", de_parents, 390 BE0_CFG_REG, /* reg */ 391 __BITS(3,0), /* div */ 392 __BITS(25,24), /* sel */ 393 __BIT(31), /* enable */ 394 0 /* flags */ 395 ), 396 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE1, "debe1-mod", de_parents, 397 BE1_CFG_REG, /* reg */ 398 __BITS(3,0), /* div */ 399 __BITS(25,24), /* sel */ 400 __BIT(31), /* enable */ 401 0 /* flags */ 402 ), 403 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE0, "defe0-mod", de_parents, 404 FE0_CFG_REG, /* reg */ 405 __BITS(3,0), /* div */ 406 __BITS(25,24), /* sel */ 407 __BIT(31), /* enable */ 408 0 /* flags */ 409 ), 410 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE1, "defe1-mod", de_parents, 411 FE1_CFG_REG, /* reg */ 412 __BITS(3,0), /* div */ 413 __BITS(25,24), /* sel */ 414 __BIT(31), /* enable */ 415 0 /* flags */ 416 ), 417 [A10_CLK_TCON0_CH0] = { 418 .type = SUNXI_CCU_DIV, 419 .base.name = "tcon0-ch0", 420 .u.div.reg = LCD0CH0_CFG_REG, 421 .u.div.parents = lcd_parents, 422 .u.div.nparents = __arraycount(lcd_parents), 423 .u.div.div = 0, 424 .u.div.sel = __BITS(25,24), 425 .u.div.enable = __BIT(31), 426 .u.div.flags = 0, 427 .enable = sunxi_ccu_div_enable, 428 .get_rate = sunxi_ccu_div_get_rate, 429 .set_rate = sun4i_a10_ccu_lcd0ch0_set_rate, 430 .round_rate = sun4i_a10_ccu_lcd0ch0_round_rate, 431 .set_parent = sunxi_ccu_div_set_parent, 432 .get_parent = sunxi_ccu_div_get_parent, 433 }, 434 [A10_CLK_TCON1_CH0] = { 435 .type = SUNXI_CCU_DIV, 436 .base.name = "tcon1-ch0", 437 .u.div.reg = LCD1CH0_CFG_REG, 438 .u.div.parents = lcd_parents, 439 .u.div.nparents = __arraycount(lcd_parents), 440 .u.div.div = 0, 441 .u.div.sel = __BITS(25,24), 442 .u.div.enable = __BIT(31), 443 .u.div.flags = 0, 444 .enable = sunxi_ccu_div_enable, 445 .get_rate = sunxi_ccu_div_get_rate, 446 .set_rate = sun4i_a10_ccu_lcd1ch0_set_rate, 447 .round_rate = sun4i_a10_ccu_lcd1ch0_round_rate, 448 .set_parent = sunxi_ccu_div_set_parent, 449 .get_parent = sunxi_ccu_div_get_parent, 450 }, 451 [A10_CLK_TCON0_CH1] = { 452 .type = SUNXI_CCU_DIV, 453 .base.name = "tcon0-ch1", 454 .u.div.reg = LCD0CH1_CFG_REG, 455 .u.div.parents = lcd_parents, 456 .u.div.nparents = __arraycount(lcd_parents), 457 .u.div.div = __BITS(3,0), 458 .u.div.sel = __BITS(25,24), 459 .u.div.enable = __BIT(15) | __BIT(31), 460 .u.div.flags = 0, 461 .enable = sunxi_ccu_div_enable, 462 .get_rate = sunxi_ccu_div_get_rate, 463 .set_rate = sun4i_a10_ccu_lcd0ch1_set_rate, 464 .set_parent = sunxi_ccu_div_set_parent, 465 .get_parent = sunxi_ccu_div_get_parent, 466 }, 467 [A10_CLK_TCON1_CH1] = { 468 .type = SUNXI_CCU_DIV, 469 .base.name = "tcon1-ch1", 470 .u.div.reg = LCD1CH1_CFG_REG, 471 .u.div.parents = lcd_parents, 472 .u.div.nparents = __arraycount(lcd_parents), 473 .u.div.div = __BITS(3,0), 474 .u.div.sel = __BITS(25,24), 475 .u.div.enable = __BIT(15) | __BIT(31), 476 .u.div.flags = 0, 477 .enable = sunxi_ccu_div_enable, 478 .get_rate = sunxi_ccu_div_get_rate, 479 .set_rate = sun4i_a10_ccu_lcd1ch1_set_rate, 480 .set_parent = sunxi_ccu_div_set_parent, 481 .get_parent = sunxi_ccu_div_get_parent, 482 }, 483 SUNXI_CCU_DIV_GATE(A10_CLK_HDMI, "hdmi-mod", lcd_parents, 484 HDMI_CLOCK_CFG_REG, /* reg */ 485 __BITS(3,0), /* div */ 486 __BITS(25,24), /* sel */ 487 __BIT(31), /* enable */ 488 0 /* flags */ 489 ), 490 491 /* A20 specific */ 492 SUNXI_CCU_NM(A20_CLK_OUT_A, "outa", out_parents, 493 CLK_OUTA_REG, /* reg */ 494 __BITS(21,20), /* n */ 495 __BITS(12,8), /* m */ 496 __BITS(25,24), /* sel */ 497 __BIT(31), /* enable */ 498 SUNXI_CCU_NM_POWER_OF_TWO), 499 500 SUNXI_CCU_NM(A20_CLK_OUT_B, "outb", out_parents, 501 CLK_OUTB_REG, /* reg */ 502 __BITS(21,20), /* n */ 503 __BITS(12,8), /* m */ 504 __BITS(25,24), /* sel */ 505 __BIT(31), /* enable */ 506 SUNXI_CCU_NM_POWER_OF_TWO), 507 508 /* AHB_GATING_REG0 */ 509 SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb", 510 AHB_GATING_REG0, 0), 511 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 512 AHB_GATING_REG0, 1), 513 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 514 AHB_GATING_REG0, 2), 515 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 516 AHB_GATING_REG0, 3), 517 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 518 AHB_GATING_REG0, 4), 519 SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb", 520 AHB_GATING_REG0, 5), 521 SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb", 522 AHB_GATING_REG0, 6), 523 SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb", 524 AHB_GATING_REG0, 7), 525 SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 526 AHB_GATING_REG0, 8), 527 SUNXI_CCU_GATE(A10_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 528 AHB_GATING_REG0, 9), 529 SUNXI_CCU_GATE(A10_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 530 AHB_GATING_REG0, 10), 531 SUNXI_CCU_GATE(A10_CLK_AHB_MMC3, "ahb-mmc3", "ahb", 532 AHB_GATING_REG0, 11), 533 SUNXI_CCU_GATE(A10_CLK_AHB_MS, "ahb-ms", "ahb", 534 AHB_GATING_REG0, 12), 535 SUNXI_CCU_GATE(A10_CLK_AHB_NAND, "ahb-nand", "ahb", 536 AHB_GATING_REG0, 13), 537 SUNXI_CCU_GATE(A10_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 538 AHB_GATING_REG0, 14), 539 SUNXI_CCU_GATE(A10_CLK_AHB_ACE, "ahb-ace", "ahb", 540 AHB_GATING_REG0, 16), 541 SUNXI_CCU_GATE(A10_CLK_AHB_EMAC, "ahb-emac", "ahb", 542 AHB_GATING_REG0, 17), 543 SUNXI_CCU_GATE(A10_CLK_AHB_TS, "ahb-ts", "ahb", 544 AHB_GATING_REG0, 18), 545 SUNXI_CCU_GATE(A10_CLK_AHB_SPI0, "ahb-spi0", "ahb", 546 AHB_GATING_REG0, 20), 547 SUNXI_CCU_GATE(A10_CLK_AHB_SPI1, "ahb-spi1", "ahb", 548 AHB_GATING_REG0, 21), 549 SUNXI_CCU_GATE(A10_CLK_AHB_SPI2, "ahb-spi2", "ahb", 550 AHB_GATING_REG0, 22), 551 SUNXI_CCU_GATE(A10_CLK_AHB_SPI3, "ahb-spi3", "ahb", 552 AHB_GATING_REG0, 23), 553 SUNXI_CCU_GATE(A10_CLK_AHB_SATA, "ahb-sata", "ahb", 554 AHB_GATING_REG0, 25), 555 SUNXI_CCU_GATE(A10_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 556 AHB_GATING_REG0, 28), 557 558 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 559 SUNXI_CCU_GATE(A10_CLK_AHB_VE, "ahb-ve", "ahb", 560 AHB_GATING_REG1, 0), 561 SUNXI_CCU_GATE(A10_CLK_AHB_TVD, "ahb-tvd", "ahb", 562 AHB_GATING_REG1, 1), 563 SUNXI_CCU_GATE(A10_CLK_AHB_TVE0, "ahb-tve0", "ahb", 564 AHB_GATING_REG1, 2), 565 SUNXI_CCU_GATE(A10_CLK_AHB_TVE1, "ahb-tve1", "ahb", 566 AHB_GATING_REG1, 3), 567 SUNXI_CCU_GATE(A10_CLK_AHB_LCD0, "ahb-lcd0", "ahb", 568 AHB_GATING_REG1, 4), 569 SUNXI_CCU_GATE(A10_CLK_AHB_LCD1, "ahb-lcd1", "ahb", 570 AHB_GATING_REG1, 5), 571 SUNXI_CCU_GATE(A10_CLK_AHB_CSI0, "ahb-csi0", "ahb", 572 AHB_GATING_REG1, 8), 573 SUNXI_CCU_GATE(A10_CLK_AHB_CSI1, "ahb-csi1", "ahb", 574 AHB_GATING_REG1, 9), 575 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 576 AHB_GATING_REG1, 10), 577 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 578 AHB_GATING_REG1, 11), 579 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 580 AHB_GATING_REG1, 12), 581 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 582 AHB_GATING_REG1, 13), 583 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 584 AHB_GATING_REG1, 14), 585 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 586 AHB_GATING_REG1, 15), 587 SUNXI_CCU_GATE(A10_CLK_AHB_GMAC, "ahb-gmac", "ahb", 588 AHB_GATING_REG1, 17), 589 SUNXI_CCU_GATE(A10_CLK_AHB_MP, "ahb-mp", "ahb", 590 AHB_GATING_REG1, 18), 591 SUNXI_CCU_GATE(A10_CLK_AHB_GPU, "ahb-gpu", "ahb", 592 AHB_GATING_REG1, 20), 593 594 /* APB0_GATING_REG */ 595 SUNXI_CCU_GATE(A10_CLK_APB0_CODEC, "apb0-codec", "apb0", 596 APB0_GATING_REG, 0), 597 SUNXI_CCU_GATE(A10_CLK_APB0_SPDIF, "apb0-spdif", "apb0", 598 APB0_GATING_REG, 1), 599 SUNXI_CCU_GATE(A10_CLK_APB0_AC97, "apb0-ac97", "apb0", 600 APB0_GATING_REG, 2), 601 SUNXI_CCU_GATE(A10_CLK_APB0_I2S0, "apb0-i2s0", "apb0", 602 APB0_GATING_REG, 3), 603 SUNXI_CCU_GATE(A10_CLK_APB0_I2S1, "apb0-i2s1", "apb0", 604 APB0_GATING_REG, 4), 605 SUNXI_CCU_GATE(A10_CLK_APB0_PIO, "apb0-pio", "apb0", 606 APB0_GATING_REG, 5), 607 SUNXI_CCU_GATE(A10_CLK_APB0_IR0, "apb0-ir0", "apb0", 608 APB0_GATING_REG, 6), 609 SUNXI_CCU_GATE(A10_CLK_APB0_IR1, "apb0-ir1", "apb0", 610 APB0_GATING_REG, 7), 611 SUNXI_CCU_GATE(A10_CLK_APB0_I2S2, "apb0-i2s2", "apb0", 612 APB0_GATING_REG, 8), 613 SUNXI_CCU_GATE(A10_CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 614 APB0_GATING_REG, 10), 615 616 /* APB1_GATING_REG */ 617 SUNXI_CCU_GATE(A10_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 618 APB1_GATING_REG, 0), 619 SUNXI_CCU_GATE(A10_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 620 APB1_GATING_REG, 1), 621 SUNXI_CCU_GATE(A10_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 622 APB1_GATING_REG, 2), 623 SUNXI_CCU_GATE(A10_CLK_APB1_I2C3, "apb1-i2c3", "apb1", 624 APB1_GATING_REG, 3), 625 SUNXI_CCU_GATE(A10_CLK_APB1_CAN, "apb1-can", "apb1", 626 APB1_GATING_REG, 4), 627 SUNXI_CCU_GATE(A10_CLK_APB1_SCR, "apb1-scr", "apb1", 628 APB1_GATING_REG, 5), 629 SUNXI_CCU_GATE(A10_CLK_APB1_PS20, "apb1-ps20", "apb1", 630 APB1_GATING_REG, 6), 631 SUNXI_CCU_GATE(A10_CLK_APB1_PS21, "apb1-ps21", "apb1", 632 APB1_GATING_REG, 7), 633 SUNXI_CCU_GATE(A10_CLK_APB1_I2C4, "apb1-i2c4", "apb1", 634 APB1_GATING_REG, 15), 635 SUNXI_CCU_GATE(A10_CLK_APB1_UART0, "apb1-uart0", "apb1", 636 APB1_GATING_REG, 16), 637 SUNXI_CCU_GATE(A10_CLK_APB1_UART1, "apb1-uart1", "apb1", 638 APB1_GATING_REG, 17), 639 SUNXI_CCU_GATE(A10_CLK_APB1_UART2, "apb1-uart2", "apb1", 640 APB1_GATING_REG, 18), 641 SUNXI_CCU_GATE(A10_CLK_APB1_UART3, "apb1-uart3", "apb1", 642 APB1_GATING_REG, 19), 643 SUNXI_CCU_GATE(A10_CLK_APB1_UART4, "apb1-uart4", "apb1", 644 APB1_GATING_REG, 20), 645 SUNXI_CCU_GATE(A10_CLK_APB1_UART5, "apb1-uart5", "apb1", 646 APB1_GATING_REG, 21), 647 SUNXI_CCU_GATE(A10_CLK_APB1_UART6, "apb1-uart6", "apb1", 648 APB1_GATING_REG, 22), 649 SUNXI_CCU_GATE(A10_CLK_APB1_UART7, "apb1-uart7", "apb1", 650 APB1_GATING_REG, 23), 651 652 /* DRAM GATING */ 653 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE0, "dram-de-be0", "pll_ddr_other", 654 DRAM_GATING_REG, 26), 655 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE1, "dram-de-be1", "pll_ddr_other", 656 DRAM_GATING_REG, 27), 657 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE0, "dram-de-fe0", "pll_ddr_other", 658 DRAM_GATING_REG, 25), 659 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE1, "dram-de-fe1", "pll_ddr_other", 660 DRAM_GATING_REG, 24), 661 662 /* AUDIO_CODEC_SCLK_CFG_REG */ 663 SUNXI_CCU_GATE(A10_CLK_CODEC, "codec", "pll_audio", 664 AUDIO_CODEC_SCLK_CFG_REG, 31), 665 666 /* USBPHY_CFG_REG */ 667 SUNXI_CCU_GATE(A10_CLK_USB_OHCI0, "usb-ohci0", "osc24m", 668 USBPHY_CFG_REG, 6), 669 SUNXI_CCU_GATE(A10_CLK_USB_OHCI1, "usb-ohci1", "osc24m", 670 USBPHY_CFG_REG, 7), 671 SUNXI_CCU_GATE(A10_CLK_USB_PHY, "usb-phy", "osc24m", 672 USBPHY_CFG_REG, 8), 673 }; 674 675 /* 676 * some special cases 677 * hardcode lcd0 (tcon0) to pll3 and lcd1 (tcon1) to pll7. 678 * compute pll rate based on desired pixel clock 679 */ 680 681 static int 682 sun4i_a10_ccu_lcd0ch0_set_rate(struct sunxi_ccu_softc *sc, 683 struct sunxi_ccu_clk * clk, u_int rate) 684 { 685 int error; 686 error = sunxi_ccu_lcdxch0_set_rate(sc, clk, 687 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 688 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 689 rate); 690 return error; 691 } 692 693 static int 694 sun4i_a10_ccu_lcd1ch0_set_rate(struct sunxi_ccu_softc *sc, 695 struct sunxi_ccu_clk * clk, u_int rate) 696 { 697 return sunxi_ccu_lcdxch0_set_rate(sc, clk, 698 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 699 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 700 rate); 701 } 702 703 static u_int 704 sun4i_a10_ccu_lcd0ch0_round_rate(struct sunxi_ccu_softc *sc, 705 struct sunxi_ccu_clk * clk, u_int rate) 706 { 707 return sunxi_ccu_lcdxch0_round_rate(sc, clk, 708 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 709 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 710 rate); 711 } 712 713 static u_int 714 sun4i_a10_ccu_lcd1ch0_round_rate(struct sunxi_ccu_softc *sc, 715 struct sunxi_ccu_clk * clk, u_int rate) 716 { 717 return sunxi_ccu_lcdxch0_round_rate(sc, clk, 718 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 719 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 720 rate); 721 } 722 723 static int 724 sun4i_a10_ccu_lcd0ch1_set_rate(struct sunxi_ccu_softc *sc, 725 struct sunxi_ccu_clk * clk, u_int rate) 726 { 727 return sunxi_ccu_lcdxch1_set_rate(sc, clk, 728 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 729 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 730 rate); 731 } 732 733 static int 734 sun4i_a10_ccu_lcd1ch1_set_rate(struct sunxi_ccu_softc *sc, 735 struct sunxi_ccu_clk * clk, u_int rate) 736 { 737 return sunxi_ccu_lcdxch1_set_rate(sc, clk, 738 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 739 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 740 rate); 741 } 742 743 #if 0 744 static int 745 sun4i_a10_ccu_lcdxch0_set_rate(struct sunxi_ccu_softc *sc, 746 struct sunxi_ccu_clk * clk, u_int rate, int unit) 747 { 748 int parent_index; 749 struct clk *clkp; 750 int error; 751 752 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 753 clkp = &sun4i_a10_ccu_clks[parent_index].base; 754 error = clk_set_rate(clkp, rate); 755 if (error) { 756 error = clk_set_rate(clkp, rate / 2); 757 if (error != 0) 758 return error; 759 parent_index = 760 (unit == 0) ? A10_CLK_PLL_VIDEO0_2X : A10_CLK_PLL_VIDEO1_2X; 761 clkp = &sun4i_a10_ccu_clks[parent_index].base; 762 } 763 error = clk_set_parent(&clk->base, clkp); 764 KASSERT(error == 0); 765 return error; 766 } 767 768 static u_int 769 sun4i_a10_ccu_lcdxch0_round_rate(struct sunxi_ccu_softc *sc, 770 struct sunxi_ccu_clk * clk, u_int try_rate, int unit) 771 { 772 int parent_index; 773 struct clk *clkp; 774 int diff, diff_x2; 775 int rate, rate_x2; 776 777 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 778 clkp = &sun4i_a10_ccu_clks[parent_index].base; 779 rate = clk_round_rate(clkp, try_rate); 780 diff = abs(try_rate - rate); 781 782 rate_x2 = (clk_round_rate(clkp, try_rate / 2) * 2); 783 diff_x2 = abs(try_rate - rate_x2); 784 785 if (diff_x2 < diff) 786 return rate_x2; 787 return rate; 788 } 789 790 static void 791 sun4i_a10_tcon_calc_pll(int f_ref, int f_out, int *pm, int *pn, int *pd) 792 { 793 int best = INT_MAX; 794 for (int d = 1; d <= 2 && best != 0; d++) { 795 for (int m = 1; m <= 16 && best != 0; m++) { 796 for (int n = 9; n <= 127 && best != 0; n++) { 797 int f_cur = (n * f_ref * d) / m; 798 int diff = abs(f_out - f_cur); 799 if (diff < best) { 800 best = diff; 801 *pm = m; 802 *pn = n; 803 *pd = d; 804 if (diff == 0) 805 return; 806 } 807 } 808 } 809 } 810 } 811 812 static int 813 sun4i_a10_ccu_lcdxch1_set_rate(struct sunxi_ccu_softc *sc, 814 struct sunxi_ccu_clk *clk, u_int rate, int unit) 815 { 816 int parent_index; 817 struct clk *clkp, *pllclk; 818 int error; 819 int n = 0, m = 0, d = 0; 820 821 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 822 clkp = &sun4i_a10_ccu_clks[parent_index].base; 823 pllclk = clkp; 824 825 sun4i_a10_tcon_calc_pll(3000000, rate, &m, &n, &d); 826 827 if (n == 0 || m == 0 || d == 0) 828 return ERANGE; 829 830 if (d == 2) { 831 parent_index = 832 (unit == 0) ? A10_CLK_PLL_VIDEO0_2X : A10_CLK_PLL_VIDEO1_2X; 833 clkp = &sun4i_a10_ccu_clks[parent_index].base; 834 } 835 836 error = clk_set_rate(pllclk, 3000000 * n); 837 KASSERT(error == 0); 838 error = clk_set_parent(&clk->base, clkp); 839 KASSERT(error == 0); 840 error = sunxi_ccu_div_set_rate(sc, clk, rate); 841 KASSERT(error == 0); 842 return error; 843 } 844 #endif 845 846 static int 847 sun4i_a10_ccu_match(device_t parent, cfdata_t cf, void *aux) 848 { 849 struct fdt_attach_args * const faa = aux; 850 851 return of_match_compat_data(faa->faa_phandle, compat_data); 852 } 853 854 static struct sunxi_ccu_softc *sc0; 855 static void 856 sun4i_a10_ccu_attach(device_t parent, device_t self, void *aux) 857 { 858 struct sunxi_ccu_softc * const sc = device_private(self); 859 struct fdt_attach_args * const faa = aux; 860 enum sun4i_a10_ccu_type type; 861 struct clk *clk, *clkp; 862 int error; 863 864 sc->sc_dev = self; 865 sc->sc_phandle = faa->faa_phandle; 866 sc->sc_bst = faa->faa_bst; 867 868 sc->sc_resets = sun4i_a10_ccu_resets; 869 sc->sc_nresets = __arraycount(sun4i_a10_ccu_resets); 870 871 sc->sc_clks = sun4i_a10_ccu_clks; 872 sc->sc_nclks = __arraycount(sun4i_a10_ccu_clks); 873 874 if (sunxi_ccu_attach(sc) != 0) 875 return; 876 877 aprint_naive("\n"); 878 879 type = of_search_compatible(faa->faa_phandle, compat_data)->value; 880 881 switch (type) { 882 case CCU_A10: 883 aprint_normal(": A10 CCU\n"); 884 break; 885 case CCU_A20: 886 aprint_normal(": A20 CCU\n"); 887 break; 888 } 889 /* hardcode debe clocks parent to PLL5 */ 890 clkp = &sun4i_a10_ccu_clks[A10_CLK_PLL_DDR_BASE].base; 891 clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE0].base; 892 error = clk_set_parent(clk, clkp); 893 KASSERT(error == 0); 894 clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE1].base; 895 error = clk_set_parent(clk, clkp); 896 KASSERT(error == 0); 897 898 (void)error; 899 sunxi_ccu_print(sc); 900 sc0 = sc; 901 } 902 903 void sun4i_ccu_print(void); 904 void 905 sun4i_ccu_print(void) 906 { 907 sunxi_ccu_print(sc0); 908 } 909
Indexes created Thu Oct 02 01:09:59 GMT 2025