sun4i_a10_ccu.c revision 1.16.16.1
1 /* $NetBSD: sun4i_a10_ccu.c,v 1.16.16.1 2022/10/02 10:37:12 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.16.16.1 2022/10/02 10:37:12 bouyer Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun4i_a10_ccu.h> 42 #include <arm/sunxi/sun7i_a20_ccu.h> 43 44 #define PLL1_CFG_REG 0x000 45 #define PLL2_CFG_REG 0x008 46 #define PLL3_CFG_REG 0x010 47 #define PLL5_CFG_REG 0x020 48 #define PLL6_CFG_REG 0x028 49 #define PLL7_CFG_REG 0x030 50 #define PLL8_CFG_REG 0x040 51 #define OSC24M_CFG_REG 0x050 52 #define CPU_AHB_APB0_CFG_REG 0x054 53 #define APB1_CLK_DIV_REG 0x058 54 #define AHB_GATING_REG0 0x060 55 #define AHB_GATING_REG1 0x064 56 #define APB0_GATING_REG 0x068 57 #define APB1_GATING_REG 0x06c 58 #define NAND_SCLK_CFG_REG 0x080 59 #define SD0_SCLK_CFG_REG 0x088 60 #define SD1_SCLK_CFG_REG 0x08c 61 #define SD2_SCLK_CFG_REG 0x090 62 #define SD3_SCLK_CFG_REG 0x094 63 #define SPI0_CLK_CFG_REG 0x0a0 64 #define SPI1_CLK_CFG_REG 0x0a4 65 #define SPI2_CLK_CFG_REG 0x0a8 66 #define SATA_CFG_REG 0x0c8 67 #define USBPHY_CFG_REG 0x0cc 68 #define SPI3_CLK_CFG_REG 0x0d4 69 #define DRAM_GATING_REG 0x100 70 #define BE0_CFG_REG 0x104 71 #define BE1_CFG_REG 0x108 72 #define FE0_CFG_REG 0x10c 73 #define FE1_CFG_REG 0x110 74 #define MP_CFG_REG 0x114 75 #define LCD0CH0_CFG_REG 0x118 76 #define LCD1CH0_CFG_REG 0x11c 77 #define LCD0CH1_CFG_REG 0x12c 78 #define LCD1CH1_CFG_REG 0x130 79 #define CSI_CFG_REG 0x134 80 #define VE_CFG_REG 0x13c 81 #define AUDIO_CODEC_SCLK_CFG_REG 0x140 82 #define LVDS_CFG_REG 0x14c 83 #define HDMI_CLOCK_CFG_REG 0x150 84 #define MALI_CFG_REG 0x154 85 #define IEP_SCLK_CFG_REG 0x160 86 #define CLK_OUTA_REG 0x1f0 87 #define CLK_OUTB_REG 0x1f4 88 89 static int sun4i_a10_ccu_match(device_t, cfdata_t, void *); 90 static void sun4i_a10_ccu_attach(device_t, device_t, void *); 91 92 enum sun4i_a10_ccu_type { 93 CCU_A10 = 1, 94 CCU_A20, 95 }; 96 97 static const struct device_compatible_entry compat_data[] = { 98 { .compat = "allwinner,sun4i-a10-ccu", .value = CCU_A10 }, 99 { .compat = "allwinner,sun7i-a20-ccu", .value = CCU_A20 }, 100 DEVICE_COMPAT_EOL 101 }; 102 103 CFATTACH_DECL_NEW(sunxi_a10_ccu, sizeof(struct sunxi_ccu_softc), 104 sun4i_a10_ccu_match, sun4i_a10_ccu_attach, NULL, NULL); 105 106 static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = { 107 SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0), 108 SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1), 109 SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2), 110 SUNXI_CCU_RESET(A10_RST_DE_BE0, BE0_CFG_REG, 30), 111 SUNXI_CCU_RESET(A10_RST_DE_BE1, BE1_CFG_REG, 30), 112 SUNXI_CCU_RESET(A10_RST_DE_FE0, FE0_CFG_REG, 30), 113 SUNXI_CCU_RESET(A10_RST_DE_FE1, FE1_CFG_REG, 30), 114 SUNXI_CCU_RESET(A10_RST_DE_MP, MP_CFG_REG, 30), 115 SUNXI_CCU_RESET(A10_RST_TCON0, LCD0CH0_CFG_REG, 30), 116 SUNXI_CCU_RESET(A10_RST_TCON1, LCD1CH0_CFG_REG, 30), 117 SUNXI_CCU_RESET(A10_RST_LVDS, LVDS_CFG_REG, 0), 118 SUNXI_CCU_RESET(A10_RST_GPU, MALI_CFG_REG, 30), 119 }; 120 121 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 122 static const char *axi_parents[] = { "cpu" }; 123 static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" }; 124 static const char *apb0_parents[] = { "ahb" }; 125 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; 126 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr_other" }; 127 static const char *sata_parents[] = { "pll6_periph_sata", "external" }; 128 static const char *de_parents[] = { "pll_video0", "pll_video1", "pll_ddr_other" }; 129 static const char *lcd_parents[] = { "pll_video0", "pll_video1", "pll_video0x2", "pll_video1x2" }; 130 static const char *out_parents[] = { "losc" /* really OSC24MHz/750 */, "losc", "osc24m" }; 131 static const char *gpu_parents[] = { "pll_gpu" }; 132 133 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = { 134 { 1008000000, 21, 1, 0, 0 }, 135 { 960000000, 20, 1, 0, 0 }, 136 { 912000000, 19, 1, 0, 0 }, 137 { 864000000, 18, 1, 0, 0 }, 138 { 720000000, 30, 0, 0, 0 }, 139 { 624000000, 26, 0, 0, 0 }, 140 { 528000000, 22, 0, 0, 0 }, 141 { 312000000, 13, 0, 0, 0 }, 142 { 144000000, 12, 0, 0, 1 }, 143 { 0 } 144 }; 145 146 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = { 147 { 24576000, 86, 0, 21, 4 }, 148 { 0 } 149 }; 150 151 /* 152 * some special cases 153 * hardcode lcd0 (tcon0) to pll3 and lcd1 (tcon1) to pll7. 154 * compute pll rate based on desired pixel clock 155 */ 156 157 static int sun4i_a10_ccu_lcd0ch0_set_rate(struct sunxi_ccu_softc *, 158 struct sunxi_ccu_clk *, u_int); 159 static int sun4i_a10_ccu_lcd1ch0_set_rate(struct sunxi_ccu_softc *, 160 struct sunxi_ccu_clk *, u_int); 161 static u_int sun4i_a10_ccu_lcd0ch0_round_rate(struct sunxi_ccu_softc *, 162 struct sunxi_ccu_clk *, u_int); 163 static u_int sun4i_a10_ccu_lcd1ch0_round_rate(struct sunxi_ccu_softc *, 164 struct sunxi_ccu_clk *, u_int); 165 static int sun4i_a10_ccu_lcd0ch1_set_rate(struct sunxi_ccu_softc *, 166 struct sunxi_ccu_clk *, u_int); 167 static int sun4i_a10_ccu_lcd1ch1_set_rate(struct sunxi_ccu_softc *, 168 struct sunxi_ccu_clk *, u_int); 169 170 static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = { 171 SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc", 172 OSC24M_CFG_REG, 0), 173 174 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_CORE, "pll_core", "osc24m", 175 PLL1_CFG_REG, /* reg */ 176 __BITS(12,8), /* n */ 177 __BITS(5,4), /* k */ 178 __BITS(1,0), /* m */ 179 __BITS(17,16), /* p */ 180 __BIT(31), /* enable */ 181 0, /* lock */ 182 sun4i_a10_pll1_table, /* table */ 183 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT | 184 SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE | SUNXI_CCU_NKMP_SCALE_CLOCK), 185 186 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 187 PLL2_CFG_REG, /* reg */ 188 __BITS(14,8), /* n */ 189 0, /* k */ 190 __BITS(4,0), /* m */ 191 __BITS(29,26), /* p */ 192 __BIT(31), /* enable */ 193 0, /* lock */ 194 sun4i_a10_ac_dig_table, /* table */ 195 0), 196 197 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_BASE, "pll_periph_base", "osc24m", 198 PLL6_CFG_REG, /* reg */ 199 __BITS(12,8), /* n */ 200 __BITS(5,4), /* k */ 201 0, /* m */ 202 0, /* p */ 203 __BIT(31), /* enable */ 204 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 205 206 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_PERIPH, "pll_periph", "pll_periph_base", 207 2, 1), 208 209 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_SATA, "pll_periph_sata", "pll_periph_base", 210 PLL6_CFG_REG, /* reg */ 211 0, /* n */ 212 0, /* k */ 213 __BITS(1,0), /* m */ 214 0, /* p */ 215 __BIT(14), /* enable */ 216 0), 217 218 SUNXI_CCU_DIV_GATE(A10_CLK_SATA, "sata", sata_parents, 219 SATA_CFG_REG, /* reg */ 220 0, /* div */ 221 __BIT(24), /* sel */ 222 __BIT(31), /* enable */ 223 0), 224 225 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR_BASE, "pll_ddr_other", "osc24m", 226 PLL5_CFG_REG, /* reg */ 227 __BITS(12, 8), /* n */ 228 __BITS(5,4), /* k */ 229 0, /* m */ 230 __BITS(17,16), /* p */ 231 __BIT(31), /* enable */ 232 SUNXI_CCU_NKMP_FACTOR_N_EXACT | SUNXI_CCU_NKMP_FACTOR_P_POW2), 233 234 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR, "pll_ddr", "osc24m", 235 PLL5_CFG_REG, /* reg */ 236 __BITS(12, 8), /* n */ 237 __BITS(5,4), /* k */ 238 __BITS(1,0), /* m */ 239 0, /* p */ 240 __BIT(31), /* enable */ 241 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 242 243 SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents, 244 CPU_AHB_APB0_CFG_REG, /* reg */ 245 0, /* div */ 246 __BITS(17,16), /* sel */ 247 SUNXI_CCU_DIV_SET_RATE_PARENT), 248 249 SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents, 250 CPU_AHB_APB0_CFG_REG, /* reg */ 251 __BITS(1,0), /* div */ 252 0, /* sel */ 253 0), 254 255 SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents, 256 CPU_AHB_APB0_CFG_REG, /* reg */ 257 __BITS(5,4), /* div */ 258 __BITS(7,6), /* sel */ 259 SUNXI_CCU_DIV_POWER_OF_TWO), 260 261 SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents, 262 CPU_AHB_APB0_CFG_REG, /* reg */ 263 __BITS(9,8), /* div */ 264 0, /* sel */ 265 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 266 267 SUNXI_CCU_NM(A10_CLK_APB1, "apb1", apb1_parents, 268 APB1_CLK_DIV_REG, /* reg */ 269 __BITS(17,16), /* n */ 270 __BITS(4,0), /* m */ 271 __BITS(25,24), /* sel */ 272 0, /* enable */ 273 SUNXI_CCU_NM_POWER_OF_TWO), 274 275 SUNXI_CCU_NM(A10_CLK_NAND, "nand", mod_parents, 276 NAND_SCLK_CFG_REG, /* reg */ 277 __BITS(17,16), /* n */ 278 __BITS(3,0), /* m */ 279 __BITS(25,24), /* sel */ 280 __BIT(31), /* enable */ 281 SUNXI_CCU_NM_POWER_OF_TWO), 282 283 SUNXI_CCU_NM(A10_CLK_SPI0, "spi0", mod_parents, 284 SPI0_CLK_CFG_REG, /* reg */ 285 __BITS(17,16), /* n */ 286 __BITS(3,0), /* m */ 287 __BITS(25,24), /* sel */ 288 __BIT(31), /* enable */ 289 SUNXI_CCU_NM_POWER_OF_TWO), 290 291 SUNXI_CCU_NM(A10_CLK_SPI1, "spi1", mod_parents, 292 SPI1_CLK_CFG_REG, /* reg */ 293 __BITS(17,16), /* n */ 294 __BITS(3,0), /* m */ 295 __BITS(25,24), /* sel */ 296 __BIT(31), /* enable */ 297 SUNXI_CCU_NM_POWER_OF_TWO), 298 299 SUNXI_CCU_NM(A10_CLK_SPI2, "spi2", mod_parents, 300 SPI2_CLK_CFG_REG, /* reg */ 301 __BITS(17,16), /* n */ 302 __BITS(3,0), /* m */ 303 __BITS(25,24), /* sel */ 304 __BIT(31), /* enable */ 305 SUNXI_CCU_NM_POWER_OF_TWO), 306 307 SUNXI_CCU_NM(A10_CLK_SPI3, "spi3", mod_parents, 308 SPI3_CLK_CFG_REG, /* reg */ 309 __BITS(17,16), /* n */ 310 __BITS(3,0), /* m */ 311 __BITS(25,24), /* sel */ 312 __BIT(31), /* enable */ 313 SUNXI_CCU_NM_POWER_OF_TWO), 314 315 SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents, 316 SD0_SCLK_CFG_REG, /* reg */ 317 __BITS(17,16), /* n */ 318 __BITS(3,0), /* m */ 319 __BITS(25,24), /* sel */ 320 __BIT(31), /* enable */ 321 SUNXI_CCU_NM_POWER_OF_TWO), 322 SUNXI_CCU_PHASE(A10_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 323 SD0_SCLK_CFG_REG, __BITS(22,20)), 324 SUNXI_CCU_PHASE(A10_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 325 SD0_SCLK_CFG_REG, __BITS(10,8)), 326 SUNXI_CCU_NM(A10_CLK_MMC1, "mmc1", mod_parents, 327 SD1_SCLK_CFG_REG, /* reg */ 328 __BITS(17,16), /* n */ 329 __BITS(3,0), /* m */ 330 __BITS(25,24), /* sel */ 331 __BIT(31), /* enable */ 332 SUNXI_CCU_NM_POWER_OF_TWO), 333 SUNXI_CCU_PHASE(A10_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 334 SD1_SCLK_CFG_REG, __BITS(22,20)), 335 SUNXI_CCU_PHASE(A10_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 336 SD1_SCLK_CFG_REG, __BITS(10,8)), 337 SUNXI_CCU_NM(A10_CLK_MMC2, "mmc2", mod_parents, 338 SD2_SCLK_CFG_REG, /* reg */ 339 __BITS(17,16), /* n */ 340 __BITS(3,0), /* m */ 341 __BITS(25,24), /* sel */ 342 __BIT(31), /* enable */ 343 SUNXI_CCU_NM_POWER_OF_TWO), 344 SUNXI_CCU_PHASE(A10_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 345 SD2_SCLK_CFG_REG, __BITS(22,20)), 346 SUNXI_CCU_PHASE(A10_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 347 SD2_SCLK_CFG_REG, __BITS(10,8)), 348 SUNXI_CCU_NM(A10_CLK_MMC3, "mmc3", mod_parents, 349 SD3_SCLK_CFG_REG, /* reg */ 350 __BITS(17,16), /* n */ 351 __BITS(3,0), /* m */ 352 __BITS(25,24), /* sel */ 353 __BIT(31), /* enable */ 354 SUNXI_CCU_NM_POWER_OF_TWO), 355 SUNXI_CCU_PHASE(A10_CLK_MMC3_SAMPLE, "mmc3_sample", "mmc3", 356 SD3_SCLK_CFG_REG, __BITS(22,20)), 357 SUNXI_CCU_PHASE(A10_CLK_MMC3_OUTPUT, "mmc3_output", "mmc3", 358 SD3_SCLK_CFG_REG, __BITS(10,8)), 359 360 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO0, "pll_video0", "osc24m", 361 PLL3_CFG_REG, /* reg */ 362 __BITS(7,0), /* m */ 363 9, /* m_min */ 364 127, /* m_max */ 365 __BIT(15), /* div_en */ 366 __BIT(14), /* frac_sel */ 367 270000000, 297000000, /* frac values */ 368 0, /* prediv */ 369 8, /* prediv_val */ 370 __BIT(31), /* enable */ 371 0), 372 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO1, "pll_video1", "osc24m", 373 PLL7_CFG_REG, /* reg */ 374 __BITS(7,0), /* m */ 375 9, /* m_min */ 376 127, /* m_max */ 377 __BIT(15), /* div_en */ 378 __BIT(14), /* frac_sel */ 379 270000000, 297000000, /* frac values */ 380 0, /* prediv */ 381 8, /* prediv_val */ 382 __BIT(31), /* enable */ 383 0), 384 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO0_2X, 385 "pll_video0x2", "pll_video0", 386 1, 2), 387 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO1_2X, 388 "pll_video1x2", "pll_video1", 389 1, 2), 390 SUNXI_CCU_NKMP(A10_CLK_PLL_GPU, "pll_gpu", "osc24m", 391 PLL8_CFG_REG, /* reg */ 392 __BITS(12, 8), /* n */ 393 __BITS(5,4), /* k */ 394 0, /* m */ 395 0, /* p */ 396 __BIT(31), /* enable */ 397 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 398 399 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE0, "debe0-mod", de_parents, 400 BE0_CFG_REG, /* reg */ 401 __BITS(3,0), /* div */ 402 __BITS(25,24), /* sel */ 403 __BIT(31), /* enable */ 404 0 /* flags */ 405 ), 406 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE1, "debe1-mod", de_parents, 407 BE1_CFG_REG, /* reg */ 408 __BITS(3,0), /* div */ 409 __BITS(25,24), /* sel */ 410 __BIT(31), /* enable */ 411 0 /* flags */ 412 ), 413 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE0, "defe0-mod", de_parents, 414 FE0_CFG_REG, /* reg */ 415 __BITS(3,0), /* div */ 416 __BITS(25,24), /* sel */ 417 __BIT(31), /* enable */ 418 0 /* flags */ 419 ), 420 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE1, "defe1-mod", de_parents, 421 FE1_CFG_REG, /* reg */ 422 __BITS(3,0), /* div */ 423 __BITS(25,24), /* sel */ 424 __BIT(31), /* enable */ 425 0 /* flags */ 426 ), 427 [A10_CLK_TCON0_CH0] = { 428 .type = SUNXI_CCU_DIV, 429 .base.name = "tcon0-ch0", 430 .u.div.reg = LCD0CH0_CFG_REG, 431 .u.div.parents = lcd_parents, 432 .u.div.nparents = __arraycount(lcd_parents), 433 .u.div.div = 0, 434 .u.div.sel = __BITS(25,24), 435 .u.div.enable = __BIT(31), 436 .u.div.flags = 0, 437 .enable = sunxi_ccu_div_enable, 438 .get_rate = sunxi_ccu_div_get_rate, 439 .set_rate = sun4i_a10_ccu_lcd0ch0_set_rate, 440 .round_rate = sun4i_a10_ccu_lcd0ch0_round_rate, 441 .set_parent = sunxi_ccu_div_set_parent, 442 .get_parent = sunxi_ccu_div_get_parent, 443 }, 444 [A10_CLK_TCON1_CH0] = { 445 .type = SUNXI_CCU_DIV, 446 .base.name = "tcon1-ch0", 447 .u.div.reg = LCD1CH0_CFG_REG, 448 .u.div.parents = lcd_parents, 449 .u.div.nparents = __arraycount(lcd_parents), 450 .u.div.div = 0, 451 .u.div.sel = __BITS(25,24), 452 .u.div.enable = __BIT(31), 453 .u.div.flags = 0, 454 .enable = sunxi_ccu_div_enable, 455 .get_rate = sunxi_ccu_div_get_rate, 456 .set_rate = sun4i_a10_ccu_lcd1ch0_set_rate, 457 .round_rate = sun4i_a10_ccu_lcd1ch0_round_rate, 458 .set_parent = sunxi_ccu_div_set_parent, 459 .get_parent = sunxi_ccu_div_get_parent, 460 }, 461 [A10_CLK_TCON0_CH1] = { 462 .type = SUNXI_CCU_DIV, 463 .base.name = "tcon0-ch1", 464 .u.div.reg = LCD0CH1_CFG_REG, 465 .u.div.parents = lcd_parents, 466 .u.div.nparents = __arraycount(lcd_parents), 467 .u.div.div = __BITS(3,0), 468 .u.div.sel = __BITS(25,24), 469 .u.div.enable = __BIT(15) | __BIT(31), 470 .u.div.flags = 0, 471 .enable = sunxi_ccu_div_enable, 472 .get_rate = sunxi_ccu_div_get_rate, 473 .set_rate = sun4i_a10_ccu_lcd0ch1_set_rate, 474 .set_parent = sunxi_ccu_div_set_parent, 475 .get_parent = sunxi_ccu_div_get_parent, 476 }, 477 [A10_CLK_TCON1_CH1] = { 478 .type = SUNXI_CCU_DIV, 479 .base.name = "tcon1-ch1", 480 .u.div.reg = LCD1CH1_CFG_REG, 481 .u.div.parents = lcd_parents, 482 .u.div.nparents = __arraycount(lcd_parents), 483 .u.div.div = __BITS(3,0), 484 .u.div.sel = __BITS(25,24), 485 .u.div.enable = __BIT(15) | __BIT(31), 486 .u.div.flags = 0, 487 .enable = sunxi_ccu_div_enable, 488 .get_rate = sunxi_ccu_div_get_rate, 489 .set_rate = sun4i_a10_ccu_lcd1ch1_set_rate, 490 .set_parent = sunxi_ccu_div_set_parent, 491 .get_parent = sunxi_ccu_div_get_parent, 492 }, 493 SUNXI_CCU_DIV_GATE(A10_CLK_HDMI, "hdmi-mod", lcd_parents, 494 HDMI_CLOCK_CFG_REG, /* reg */ 495 __BITS(3,0), /* div */ 496 __BITS(25,24), /* sel */ 497 __BIT(31), /* enable */ 498 0 /* flags */ 499 ), 500 SUNXI_CCU_DIV_GATE(A10_CLK_GPU, "gpu", gpu_parents, 501 MALI_CFG_REG, /* reg */ 502 __BITS(3,0), /* div */ 503 __BITS(25,24), /* sel */ 504 __BIT(31), /* enable */ 505 0 /* flags */ 506 ), 507 508 /* A20 specific */ 509 SUNXI_CCU_NM(A20_CLK_OUT_A, "outa", out_parents, 510 CLK_OUTA_REG, /* reg */ 511 __BITS(21,20), /* n */ 512 __BITS(12,8), /* m */ 513 __BITS(25,24), /* sel */ 514 __BIT(31), /* enable */ 515 SUNXI_CCU_NM_POWER_OF_TWO), 516 517 SUNXI_CCU_NM(A20_CLK_OUT_B, "outb", out_parents, 518 CLK_OUTB_REG, /* reg */ 519 __BITS(21,20), /* n */ 520 __BITS(12,8), /* m */ 521 __BITS(25,24), /* sel */ 522 __BIT(31), /* enable */ 523 SUNXI_CCU_NM_POWER_OF_TWO), 524 525 /* AHB_GATING_REG0 */ 526 SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb", 527 AHB_GATING_REG0, 0), 528 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 529 AHB_GATING_REG0, 1), 530 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 531 AHB_GATING_REG0, 2), 532 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 533 AHB_GATING_REG0, 3), 534 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 535 AHB_GATING_REG0, 4), 536 SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb", 537 AHB_GATING_REG0, 5), 538 SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb", 539 AHB_GATING_REG0, 6), 540 SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb", 541 AHB_GATING_REG0, 7), 542 SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 543 AHB_GATING_REG0, 8), 544 SUNXI_CCU_GATE(A10_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 545 AHB_GATING_REG0, 9), 546 SUNXI_CCU_GATE(A10_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 547 AHB_GATING_REG0, 10), 548 SUNXI_CCU_GATE(A10_CLK_AHB_MMC3, "ahb-mmc3", "ahb", 549 AHB_GATING_REG0, 11), 550 SUNXI_CCU_GATE(A10_CLK_AHB_MS, "ahb-ms", "ahb", 551 AHB_GATING_REG0, 12), 552 SUNXI_CCU_GATE(A10_CLK_AHB_NAND, "ahb-nand", "ahb", 553 AHB_GATING_REG0, 13), 554 SUNXI_CCU_GATE(A10_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 555 AHB_GATING_REG0, 14), 556 SUNXI_CCU_GATE(A10_CLK_AHB_ACE, "ahb-ace", "ahb", 557 AHB_GATING_REG0, 16), 558 SUNXI_CCU_GATE(A10_CLK_AHB_EMAC, "ahb-emac", "ahb", 559 AHB_GATING_REG0, 17), 560 SUNXI_CCU_GATE(A10_CLK_AHB_TS, "ahb-ts", "ahb", 561 AHB_GATING_REG0, 18), 562 SUNXI_CCU_GATE(A10_CLK_AHB_SPI0, "ahb-spi0", "ahb", 563 AHB_GATING_REG0, 20), 564 SUNXI_CCU_GATE(A10_CLK_AHB_SPI1, "ahb-spi1", "ahb", 565 AHB_GATING_REG0, 21), 566 SUNXI_CCU_GATE(A10_CLK_AHB_SPI2, "ahb-spi2", "ahb", 567 AHB_GATING_REG0, 22), 568 SUNXI_CCU_GATE(A10_CLK_AHB_SPI3, "ahb-spi3", "ahb", 569 AHB_GATING_REG0, 23), 570 SUNXI_CCU_GATE(A10_CLK_AHB_SATA, "ahb-sata", "ahb", 571 AHB_GATING_REG0, 25), 572 SUNXI_CCU_GATE(A10_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 573 AHB_GATING_REG0, 28), 574 575 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 576 SUNXI_CCU_GATE(A10_CLK_AHB_VE, "ahb-ve", "ahb", 577 AHB_GATING_REG1, 0), 578 SUNXI_CCU_GATE(A10_CLK_AHB_TVD, "ahb-tvd", "ahb", 579 AHB_GATING_REG1, 1), 580 SUNXI_CCU_GATE(A10_CLK_AHB_TVE0, "ahb-tve0", "ahb", 581 AHB_GATING_REG1, 2), 582 SUNXI_CCU_GATE(A10_CLK_AHB_TVE1, "ahb-tve1", "ahb", 583 AHB_GATING_REG1, 3), 584 SUNXI_CCU_GATE(A10_CLK_AHB_LCD0, "ahb-lcd0", "ahb", 585 AHB_GATING_REG1, 4), 586 SUNXI_CCU_GATE(A10_CLK_AHB_LCD1, "ahb-lcd1", "ahb", 587 AHB_GATING_REG1, 5), 588 SUNXI_CCU_GATE(A10_CLK_AHB_CSI0, "ahb-csi0", "ahb", 589 AHB_GATING_REG1, 8), 590 SUNXI_CCU_GATE(A10_CLK_AHB_CSI1, "ahb-csi1", "ahb", 591 AHB_GATING_REG1, 9), 592 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 593 AHB_GATING_REG1, 10), 594 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 595 AHB_GATING_REG1, 11), 596 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 597 AHB_GATING_REG1, 12), 598 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 599 AHB_GATING_REG1, 13), 600 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 601 AHB_GATING_REG1, 14), 602 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 603 AHB_GATING_REG1, 15), 604 SUNXI_CCU_GATE(A10_CLK_AHB_GMAC, "ahb-gmac", "ahb", 605 AHB_GATING_REG1, 17), 606 SUNXI_CCU_GATE(A10_CLK_AHB_MP, "ahb-mp", "ahb", 607 AHB_GATING_REG1, 18), 608 SUNXI_CCU_GATE(A10_CLK_AHB_GPU, "ahb-gpu", "ahb", 609 AHB_GATING_REG1, 20), 610 611 /* APB0_GATING_REG */ 612 SUNXI_CCU_GATE(A10_CLK_APB0_CODEC, "apb0-codec", "apb0", 613 APB0_GATING_REG, 0), 614 SUNXI_CCU_GATE(A10_CLK_APB0_SPDIF, "apb0-spdif", "apb0", 615 APB0_GATING_REG, 1), 616 SUNXI_CCU_GATE(A10_CLK_APB0_AC97, "apb0-ac97", "apb0", 617 APB0_GATING_REG, 2), 618 SUNXI_CCU_GATE(A10_CLK_APB0_I2S0, "apb0-i2s0", "apb0", 619 APB0_GATING_REG, 3), 620 SUNXI_CCU_GATE(A10_CLK_APB0_I2S1, "apb0-i2s1", "apb0", 621 APB0_GATING_REG, 4), 622 SUNXI_CCU_GATE(A10_CLK_APB0_PIO, "apb0-pio", "apb0", 623 APB0_GATING_REG, 5), 624 SUNXI_CCU_GATE(A10_CLK_APB0_IR0, "apb0-ir0", "apb0", 625 APB0_GATING_REG, 6), 626 SUNXI_CCU_GATE(A10_CLK_APB0_IR1, "apb0-ir1", "apb0", 627 APB0_GATING_REG, 7), 628 SUNXI_CCU_GATE(A10_CLK_APB0_I2S2, "apb0-i2s2", "apb0", 629 APB0_GATING_REG, 8), 630 SUNXI_CCU_GATE(A10_CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 631 APB0_GATING_REG, 10), 632 633 /* APB1_GATING_REG */ 634 SUNXI_CCU_GATE(A10_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 635 APB1_GATING_REG, 0), 636 SUNXI_CCU_GATE(A10_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 637 APB1_GATING_REG, 1), 638 SUNXI_CCU_GATE(A10_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 639 APB1_GATING_REG, 2), 640 SUNXI_CCU_GATE(A10_CLK_APB1_I2C3, "apb1-i2c3", "apb1", 641 APB1_GATING_REG, 3), 642 SUNXI_CCU_GATE(A10_CLK_APB1_CAN, "apb1-can", "apb1", 643 APB1_GATING_REG, 4), 644 SUNXI_CCU_GATE(A10_CLK_APB1_SCR, "apb1-scr", "apb1", 645 APB1_GATING_REG, 5), 646 SUNXI_CCU_GATE(A10_CLK_APB1_PS20, "apb1-ps20", "apb1", 647 APB1_GATING_REG, 6), 648 SUNXI_CCU_GATE(A10_CLK_APB1_PS21, "apb1-ps21", "apb1", 649 APB1_GATING_REG, 7), 650 SUNXI_CCU_GATE(A10_CLK_APB1_I2C4, "apb1-i2c4", "apb1", 651 APB1_GATING_REG, 15), 652 SUNXI_CCU_GATE(A10_CLK_APB1_UART0, "apb1-uart0", "apb1", 653 APB1_GATING_REG, 16), 654 SUNXI_CCU_GATE(A10_CLK_APB1_UART1, "apb1-uart1", "apb1", 655 APB1_GATING_REG, 17), 656 SUNXI_CCU_GATE(A10_CLK_APB1_UART2, "apb1-uart2", "apb1", 657 APB1_GATING_REG, 18), 658 SUNXI_CCU_GATE(A10_CLK_APB1_UART3, "apb1-uart3", "apb1", 659 APB1_GATING_REG, 19), 660 SUNXI_CCU_GATE(A10_CLK_APB1_UART4, "apb1-uart4", "apb1", 661 APB1_GATING_REG, 20), 662 SUNXI_CCU_GATE(A10_CLK_APB1_UART5, "apb1-uart5", "apb1", 663 APB1_GATING_REG, 21), 664 SUNXI_CCU_GATE(A10_CLK_APB1_UART6, "apb1-uart6", "apb1", 665 APB1_GATING_REG, 22), 666 SUNXI_CCU_GATE(A10_CLK_APB1_UART7, "apb1-uart7", "apb1", 667 APB1_GATING_REG, 23), 668 669 /* DRAM GATING */ 670 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE0, "dram-de-be0", "pll_ddr_other", 671 DRAM_GATING_REG, 26), 672 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE1, "dram-de-be1", "pll_ddr_other", 673 DRAM_GATING_REG, 27), 674 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE0, "dram-de-fe0", "pll_ddr_other", 675 DRAM_GATING_REG, 25), 676 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE1, "dram-de-fe1", "pll_ddr_other", 677 DRAM_GATING_REG, 24), 678 679 /* AUDIO_CODEC_SCLK_CFG_REG */ 680 SUNXI_CCU_GATE(A10_CLK_CODEC, "codec", "pll_audio", 681 AUDIO_CODEC_SCLK_CFG_REG, 31), 682 683 /* USBPHY_CFG_REG */ 684 SUNXI_CCU_GATE(A10_CLK_USB_OHCI0, "usb-ohci0", "osc24m", 685 USBPHY_CFG_REG, 6), 686 SUNXI_CCU_GATE(A10_CLK_USB_OHCI1, "usb-ohci1", "osc24m", 687 USBPHY_CFG_REG, 7), 688 SUNXI_CCU_GATE(A10_CLK_USB_PHY, "usb-phy", "osc24m", 689 USBPHY_CFG_REG, 8), 690 }; 691 692 /* 693 * some special cases 694 * hardcode lcd0 (tcon0) to pll3 and lcd1 (tcon1) to pll7. 695 * compute pll rate based on desired pixel clock 696 */ 697 698 static int 699 sun4i_a10_ccu_lcd0ch0_set_rate(struct sunxi_ccu_softc *sc, 700 struct sunxi_ccu_clk * clk, u_int rate) 701 { 702 int error; 703 error = sunxi_ccu_lcdxch0_set_rate(sc, clk, 704 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 705 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 706 rate); 707 return error; 708 } 709 710 static int 711 sun4i_a10_ccu_lcd1ch0_set_rate(struct sunxi_ccu_softc *sc, 712 struct sunxi_ccu_clk * clk, u_int rate) 713 { 714 return sunxi_ccu_lcdxch0_set_rate(sc, clk, 715 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 716 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 717 rate); 718 } 719 720 static u_int 721 sun4i_a10_ccu_lcd0ch0_round_rate(struct sunxi_ccu_softc *sc, 722 struct sunxi_ccu_clk * clk, u_int rate) 723 { 724 return sunxi_ccu_lcdxch0_round_rate(sc, clk, 725 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 726 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 727 rate); 728 } 729 730 static u_int 731 sun4i_a10_ccu_lcd1ch0_round_rate(struct sunxi_ccu_softc *sc, 732 struct sunxi_ccu_clk * clk, u_int rate) 733 { 734 return sunxi_ccu_lcdxch0_round_rate(sc, clk, 735 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 736 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 737 rate); 738 } 739 740 static int 741 sun4i_a10_ccu_lcd0ch1_set_rate(struct sunxi_ccu_softc *sc, 742 struct sunxi_ccu_clk * clk, u_int rate) 743 { 744 return sunxi_ccu_lcdxch1_set_rate(sc, clk, 745 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 746 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 747 rate); 748 } 749 750 static int 751 sun4i_a10_ccu_lcd1ch1_set_rate(struct sunxi_ccu_softc *sc, 752 struct sunxi_ccu_clk * clk, u_int rate) 753 { 754 return sunxi_ccu_lcdxch1_set_rate(sc, clk, 755 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 756 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 757 rate); 758 } 759 760 #if 0 761 static int 762 sun4i_a10_ccu_lcdxch0_set_rate(struct sunxi_ccu_softc *sc, 763 struct sunxi_ccu_clk * clk, u_int rate, int unit) 764 { 765 int parent_index; 766 struct clk *clkp; 767 int error; 768 769 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 770 clkp = &sun4i_a10_ccu_clks[parent_index].base; 771 error = clk_set_rate(clkp, rate); 772 if (error) { 773 error = clk_set_rate(clkp, rate / 2); 774 if (error != 0) 775 return error; 776 parent_index = 777 (unit == 0) ? A10_CLK_PLL_VIDEO0_2X : A10_CLK_PLL_VIDEO1_2X; 778 clkp = &sun4i_a10_ccu_clks[parent_index].base; 779 } 780 error = clk_set_parent(&clk->base, clkp); 781 KASSERT(error == 0); 782 return error; 783 } 784 785 static u_int 786 sun4i_a10_ccu_lcdxch0_round_rate(struct sunxi_ccu_softc *sc, 787 struct sunxi_ccu_clk * clk, u_int try_rate, int unit) 788 { 789 int parent_index; 790 struct clk *clkp; 791 int diff, diff_x2; 792 int rate, rate_x2; 793 794 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 795 clkp = &sun4i_a10_ccu_clks[parent_index].base; 796 rate = clk_round_rate(clkp, try_rate); 797 diff = abs(try_rate - rate); 798 799 rate_x2 = (clk_round_rate(clkp, try_rate / 2) * 2); 800 diff_x2 = abs(try_rate - rate_x2); 801 802 if (diff_x2 < diff) 803 return rate_x2; 804 return rate; 805 } 806 807 static void 808 sun4i_a10_tcon_calc_pll(int f_ref, int f_out, int *pm, int *pn, int *pd) 809 { 810 int best = INT_MAX; 811 for (int d = 1; d <= 2 && best != 0; d++) { 812 for (int m = 1; m <= 16 && best != 0; m++) { 813 for (int n = 9; n <= 127 && best != 0; n++) { 814 int f_cur = (n * f_ref * d) / m; 815 int diff = abs(f_out - f_cur); 816 if (diff < best) { 817 best = diff; 818 *pm = m; 819 *pn = n; 820 *pd = d; 821 if (diff == 0) 822 return; 823 } 824 } 825 } 826 } 827 } 828 829 static int 830 sun4i_a10_ccu_lcdxch1_set_rate(struct sunxi_ccu_softc *sc, 831 struct sunxi_ccu_clk *clk, u_int rate, int unit) 832 { 833 int parent_index; 834 struct clk *clkp, *pllclk; 835 int error; 836 int n = 0, m = 0, d = 0; 837 838 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 839 clkp = &sun4i_a10_ccu_clks[parent_index].base; 840 pllclk = clkp; 841 842 sun4i_a10_tcon_calc_pll(3000000, rate, &m, &n, &d); 843 844 if (n == 0 || m == 0 || d == 0) 845 return ERANGE; 846 847 if (d == 2) { 848 parent_index = 849 (unit == 0) ? A10_CLK_PLL_VIDEO0_2X : A10_CLK_PLL_VIDEO1_2X; 850 clkp = &sun4i_a10_ccu_clks[parent_index].base; 851 } 852 853 error = clk_set_rate(pllclk, 3000000 * n); 854 KASSERT(error == 0); 855 error = clk_set_parent(&clk->base, clkp); 856 KASSERT(error == 0); 857 error = sunxi_ccu_div_set_rate(sc, clk, rate); 858 KASSERT(error == 0); 859 return error; 860 } 861 #endif 862 863 static int 864 sun4i_a10_ccu_match(device_t parent, cfdata_t cf, void *aux) 865 { 866 struct fdt_attach_args * const faa = aux; 867 868 return of_compatible_match(faa->faa_phandle, compat_data); 869 } 870 871 static struct sunxi_ccu_softc *sc0; 872 static void 873 sun4i_a10_ccu_attach(device_t parent, device_t self, void *aux) 874 { 875 struct sunxi_ccu_softc * const sc = device_private(self); 876 struct fdt_attach_args * const faa = aux; 877 enum sun4i_a10_ccu_type type; 878 struct clk *clk, *clkp; 879 int error; 880 881 sc->sc_dev = self; 882 sc->sc_phandle = faa->faa_phandle; 883 sc->sc_bst = faa->faa_bst; 884 885 sc->sc_resets = sun4i_a10_ccu_resets; 886 sc->sc_nresets = __arraycount(sun4i_a10_ccu_resets); 887 888 sc->sc_clks = sun4i_a10_ccu_clks; 889 sc->sc_nclks = __arraycount(sun4i_a10_ccu_clks); 890 891 if (sunxi_ccu_attach(sc) != 0) 892 return; 893 894 aprint_naive("\n"); 895 896 type = of_compatible_lookup(faa->faa_phandle, compat_data)->value; 897 898 switch (type) { 899 case CCU_A10: 900 aprint_normal(": A10 CCU\n"); 901 break; 902 case CCU_A20: 903 aprint_normal(": A20 CCU\n"); 904 break; 905 } 906 /* hardcode debe clocks parent to PLL5 */ 907 clkp = &sun4i_a10_ccu_clks[A10_CLK_PLL_DDR_BASE].base; 908 clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE0].base; 909 error = clk_set_parent(clk, clkp); 910 KASSERT(error == 0); 911 clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE1].base; 912 error = clk_set_parent(clk, clkp); 913 KASSERT(error == 0); 914 915 (void)error; 916 sunxi_ccu_print(sc); 917 sc0 = sc; 918 } 919 920 void sun4i_ccu_print(void); 921 void 922 sun4i_ccu_print(void) 923 { 924 sunxi_ccu_print(sc0); 925 } 926
Indexes created Mon Oct 20 05:10:11 GMT 2025