sun4i_a10_ccu.c revision 1.5.2.2
1 /* $NetBSD: sun4i_a10_ccu.c,v 1.5.2.2 2017/12/03 11:35:56 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.5.2.2 2017/12/03 11:35:56 jdolecek Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun4i_a10_ccu.h> 42 #include <arm/sunxi/sun7i_a20_ccu.h> 43 44 #define PLL1_CFG_REG 0x000 45 #define PLL2_CFG_REG 0x008 46 #define PLL6_CFG_REG 0x028 47 #define OSC24M_CFG_REG 0x050 48 #define CPU_AHB_APB0_CFG_REG 0x054 49 #define APB1_CLK_DIV_REG 0x058 50 #define AHB_GATING_REG0 0x060 51 #define AHB_GATING_REG1 0x064 52 #define APB0_GATING_REG 0x068 53 #define APB1_GATING_REG 0x06c 54 #define NAND_SCLK_CFG_REG 0x080 55 #define SD0_SCLK_CFG_REG 0x088 56 #define SD1_SCLK_CFG_REG 0x08c 57 #define SD2_SCLK_CFG_REG 0x090 58 #define SD3_SCLK_CFG_REG 0x094 59 #define SATA_CFG_REG 0x0c8 60 #define USBPHY_CFG_REG 0x0cc 61 #define BE_CFG_REG 0x104 62 #define FE_CFG_REG 0x10c 63 #define CSI_CFG_REG 0x134 64 #define VE_CFG_REG 0x13c 65 #define AUDIO_CODEC_SCLK_CFG_REG 0x140 66 #define MALI_CLOCK_CFG_REG 0x154 67 #define IEP_SCLK_CFG_REG 0x160 68 69 static int sun4i_a10_ccu_match(device_t, cfdata_t, void *); 70 static void sun4i_a10_ccu_attach(device_t, device_t, void *); 71 72 enum sun4i_a10_ccu_type { 73 CCU_A10 = 1, 74 CCU_A20, 75 }; 76 77 static const struct of_compat_data compat_data[] = { 78 { "allwinner,sun4i-a10-ccu", CCU_A10 }, 79 { "allwinner,sun7i-a20-ccu", CCU_A20 }, 80 { NULL } 81 }; 82 83 CFATTACH_DECL_NEW(sunxi_a10_ccu, sizeof(struct sunxi_ccu_softc), 84 sun4i_a10_ccu_match, sun4i_a10_ccu_attach, NULL, NULL); 85 86 static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = { 87 SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0), 88 SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1), 89 SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2), 90 }; 91 92 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 93 static const char *axi_parents[] = { "cpu" }; 94 static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" }; 95 static const char *apb0_parents[] = { "ahb" }; 96 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; 97 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr" }; 98 static const char *sata_parents[] = { "pll6_periph_sata", "external" }; 99 100 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = { 101 { 1008000000, 21, 1, 0, 0 }, 102 { 960000000, 20, 1, 0, 0 }, 103 { 912000000, 19, 1, 0, 0 }, 104 { 864000000, 18, 1, 0, 0 }, 105 { 720000000, 30, 0, 0, 0 }, 106 { 528000000, 22, 0, 0, 0 }, 107 { 312000000, 13, 0, 0, 0 }, 108 { 144000000, 12, 0, 0, 1 }, 109 { 0 } 110 }; 111 112 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = { 113 { 24576000, 86, 0, 21, 3 }, 114 { 0 } 115 }; 116 117 static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = { 118 SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc", 119 OSC24M_CFG_REG, 0), 120 121 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_CORE, "pll_core", "osc24m", 122 PLL1_CFG_REG, /* reg */ 123 __BITS(12,8), /* n */ 124 __BITS(5,4), /* k */ 125 __BITS(1,0), /* m */ 126 __BITS(17,16), /* p */ 127 __BIT(31), /* enable */ 128 0, /* lock */ 129 sun4i_a10_pll1_table, /* table */ 130 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT | 131 SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE | SUNXI_CCU_NKMP_SCALE_CLOCK), 132 133 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 134 PLL2_CFG_REG, /* reg */ 135 __BITS(14,8), /* n */ 136 0, /* k */ 137 __BITS(4,0), /* m */ 138 __BITS(29,26), /* p */ 139 __BIT(31), /* enable */ 140 0, /* lock */ 141 sun4i_a10_ac_dig_table, /* table */ 142 0), 143 144 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_BASE, "pll_periph_base", "osc24m", 145 PLL6_CFG_REG, /* reg */ 146 __BITS(12,8), /* n */ 147 __BITS(5,4), /* k */ 148 0, /* m */ 149 0, /* p */ 150 __BIT(31), /* enable */ 151 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 152 153 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_PERIPH, "pll_periph", "pll_periph_base", 154 2, 1), 155 156 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_SATA, "pll_periph_sata", "pll_periph_base", 157 PLL6_CFG_REG, /* reg */ 158 0, /* n */ 159 0, /* k */ 160 __BITS(1,0), /* m */ 161 0, /* p */ 162 __BIT(14), /* enable */ 163 0), 164 165 SUNXI_CCU_DIV_GATE(A10_CLK_SATA, "sata", sata_parents, 166 SATA_CFG_REG, /* reg */ 167 0, /* div */ 168 __BIT(24), /* sel */ 169 __BIT(31), /* enable */ 170 0), 171 172 SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents, 173 CPU_AHB_APB0_CFG_REG, /* reg */ 174 0, /* div */ 175 __BITS(17,16), /* sel */ 176 SUNXI_CCU_DIV_SET_RATE_PARENT), 177 178 SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents, 179 CPU_AHB_APB0_CFG_REG, /* reg */ 180 __BITS(1,0), /* div */ 181 0, /* sel */ 182 0), 183 184 SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents, 185 CPU_AHB_APB0_CFG_REG, /* reg */ 186 __BITS(5,4), /* div */ 187 __BITS(7,6), /* sel */ 188 SUNXI_CCU_DIV_POWER_OF_TWO), 189 190 SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents, 191 CPU_AHB_APB0_CFG_REG, /* reg */ 192 __BITS(9,8), /* div */ 193 0, /* sel */ 194 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 195 196 SUNXI_CCU_NM(A10_CLK_APB1, "apb1", apb1_parents, 197 APB1_CLK_DIV_REG, /* reg */ 198 __BITS(17,16), /* n */ 199 __BITS(4,0), /* m */ 200 __BITS(25,24), /* sel */ 201 0, /* enable */ 202 SUNXI_CCU_NM_POWER_OF_TWO), 203 204 SUNXI_CCU_NM(A10_CLK_NAND, "nand", mod_parents, 205 NAND_SCLK_CFG_REG, /* reg */ 206 __BITS(17,16), /* n */ 207 __BITS(3,0), /* m */ 208 __BITS(25,24), /* sel */ 209 __BIT(31), /* enable */ 210 SUNXI_CCU_NM_POWER_OF_TWO), 211 212 SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents, 213 SD0_SCLK_CFG_REG, /* reg */ 214 __BITS(17,16), /* n */ 215 __BITS(3,0), /* m */ 216 __BITS(25,24), /* sel */ 217 __BIT(31), /* enable */ 218 SUNXI_CCU_NM_POWER_OF_TWO), 219 SUNXI_CCU_PHASE(A10_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 220 SD0_SCLK_CFG_REG, __BITS(22,20)), 221 SUNXI_CCU_PHASE(A10_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 222 SD0_SCLK_CFG_REG, __BITS(10,8)), 223 SUNXI_CCU_NM(A10_CLK_MMC1, "mmc1", mod_parents, 224 SD1_SCLK_CFG_REG, /* reg */ 225 __BITS(17,16), /* n */ 226 __BITS(3,0), /* m */ 227 __BITS(25,24), /* sel */ 228 __BIT(31), /* enable */ 229 SUNXI_CCU_NM_POWER_OF_TWO), 230 SUNXI_CCU_PHASE(A10_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 231 SD1_SCLK_CFG_REG, __BITS(22,20)), 232 SUNXI_CCU_PHASE(A10_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 233 SD1_SCLK_CFG_REG, __BITS(10,8)), 234 SUNXI_CCU_NM(A10_CLK_MMC2, "mmc2", mod_parents, 235 SD2_SCLK_CFG_REG, /* reg */ 236 __BITS(17,16), /* n */ 237 __BITS(3,0), /* m */ 238 __BITS(25,24), /* sel */ 239 __BIT(31), /* enable */ 240 SUNXI_CCU_NM_POWER_OF_TWO), 241 SUNXI_CCU_PHASE(A10_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 242 SD2_SCLK_CFG_REG, __BITS(22,20)), 243 SUNXI_CCU_PHASE(A10_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 244 SD2_SCLK_CFG_REG, __BITS(10,8)), 245 SUNXI_CCU_NM(A10_CLK_MMC3, "mmc3", mod_parents, 246 SD3_SCLK_CFG_REG, /* reg */ 247 __BITS(17,16), /* n */ 248 __BITS(3,0), /* m */ 249 __BITS(25,24), /* sel */ 250 __BIT(31), /* enable */ 251 SUNXI_CCU_NM_POWER_OF_TWO), 252 SUNXI_CCU_PHASE(A10_CLK_MMC3_SAMPLE, "mmc3_sample", "mmc3", 253 SD3_SCLK_CFG_REG, __BITS(22,20)), 254 SUNXI_CCU_PHASE(A10_CLK_MMC3_OUTPUT, "mmc3_output", "mmc3", 255 SD3_SCLK_CFG_REG, __BITS(10,8)), 256 257 /* AHB_GATING_REG0 */ 258 SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb", 259 AHB_GATING_REG0, 0), 260 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 261 AHB_GATING_REG0, 1), 262 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 263 AHB_GATING_REG0, 2), 264 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 265 AHB_GATING_REG0, 3), 266 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 267 AHB_GATING_REG0, 4), 268 SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb", 269 AHB_GATING_REG0, 5), 270 SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb", 271 AHB_GATING_REG0, 6), 272 SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb", 273 AHB_GATING_REG0, 7), 274 SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 275 AHB_GATING_REG0, 8), 276 SUNXI_CCU_GATE(A10_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 277 AHB_GATING_REG0, 9), 278 SUNXI_CCU_GATE(A10_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 279 AHB_GATING_REG0, 10), 280 SUNXI_CCU_GATE(A10_CLK_AHB_MMC3, "ahb-mmc3", "ahb", 281 AHB_GATING_REG0, 11), 282 SUNXI_CCU_GATE(A10_CLK_AHB_MS, "ahb-ms", "ahb", 283 AHB_GATING_REG0, 12), 284 SUNXI_CCU_GATE(A10_CLK_AHB_NAND, "ahb-nand", "ahb", 285 AHB_GATING_REG0, 13), 286 SUNXI_CCU_GATE(A10_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 287 AHB_GATING_REG0, 14), 288 SUNXI_CCU_GATE(A10_CLK_AHB_ACE, "ahb-ace", "ahb", 289 AHB_GATING_REG0, 16), 290 SUNXI_CCU_GATE(A10_CLK_AHB_EMAC, "ahb-emac", "ahb", 291 AHB_GATING_REG0, 17), 292 SUNXI_CCU_GATE(A10_CLK_AHB_TS, "ahb-ts", "ahb", 293 AHB_GATING_REG0, 18), 294 SUNXI_CCU_GATE(A10_CLK_AHB_SPI0, "ahb-spi0", "ahb", 295 AHB_GATING_REG0, 20), 296 SUNXI_CCU_GATE(A10_CLK_AHB_SPI1, "ahb-spi1", "ahb", 297 AHB_GATING_REG0, 21), 298 SUNXI_CCU_GATE(A10_CLK_AHB_SPI2, "ahb-spi2", "ahb", 299 AHB_GATING_REG0, 22), 300 SUNXI_CCU_GATE(A10_CLK_AHB_SPI3, "ahb-spi3", "ahb", 301 AHB_GATING_REG0, 23), 302 SUNXI_CCU_GATE(A10_CLK_AHB_SATA, "ahb-sata", "ahb", 303 AHB_GATING_REG0, 25), 304 SUNXI_CCU_GATE(A10_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 305 AHB_GATING_REG0, 28), 306 307 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 308 SUNXI_CCU_GATE(A10_CLK_AHB_VE, "ahb-ve", "ahb", 309 AHB_GATING_REG1, 0), 310 SUNXI_CCU_GATE(A10_CLK_AHB_TVD, "ahb-tvd", "ahb", 311 AHB_GATING_REG1, 1), 312 SUNXI_CCU_GATE(A10_CLK_AHB_TVE0, "ahb-tve0", "ahb", 313 AHB_GATING_REG1, 2), 314 SUNXI_CCU_GATE(A10_CLK_AHB_TVE1, "ahb-tve1", "ahb", 315 AHB_GATING_REG1, 3), 316 SUNXI_CCU_GATE(A10_CLK_AHB_LCD0, "ahb-lcd0", "ahb", 317 AHB_GATING_REG1, 4), 318 SUNXI_CCU_GATE(A10_CLK_AHB_LCD1, "ahb-lcd1", "ahb", 319 AHB_GATING_REG1, 5), 320 SUNXI_CCU_GATE(A10_CLK_AHB_CSI0, "ahb-csi0", "ahb", 321 AHB_GATING_REG1, 8), 322 SUNXI_CCU_GATE(A10_CLK_AHB_CSI1, "ahb-csi1", "ahb", 323 AHB_GATING_REG1, 9), 324 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 325 AHB_GATING_REG1, 10), 326 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 327 AHB_GATING_REG1, 11), 328 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 329 AHB_GATING_REG1, 12), 330 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 331 AHB_GATING_REG1, 13), 332 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 333 AHB_GATING_REG1, 14), 334 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 335 AHB_GATING_REG1, 15), 336 SUNXI_CCU_GATE(A10_CLK_AHB_GMAC, "ahb-gmac", "ahb", 337 AHB_GATING_REG1, 17), 338 SUNXI_CCU_GATE(A10_CLK_AHB_MP, "ahb-mp", "ahb", 339 AHB_GATING_REG1, 18), 340 SUNXI_CCU_GATE(A10_CLK_AHB_GPU, "ahb-gpu", "ahb", 341 AHB_GATING_REG1, 20), 342 343 /* APB0_GATING_REG */ 344 SUNXI_CCU_GATE(A10_CLK_APB0_CODEC, "apb0-codec", "apb0", 345 APB0_GATING_REG, 0), 346 SUNXI_CCU_GATE(A10_CLK_APB0_SPDIF, "apb0-spdif", "apb0", 347 APB0_GATING_REG, 1), 348 SUNXI_CCU_GATE(A10_CLK_APB0_AC97, "apb0-ac97", "apb0", 349 APB0_GATING_REG, 2), 350 SUNXI_CCU_GATE(A10_CLK_APB0_I2S0, "apb0-i2s0", "apb0", 351 APB0_GATING_REG, 3), 352 SUNXI_CCU_GATE(A10_CLK_APB0_I2S1, "apb0-i2s1", "apb0", 353 APB0_GATING_REG, 4), 354 SUNXI_CCU_GATE(A10_CLK_APB0_PIO, "apb0-pio", "apb0", 355 APB0_GATING_REG, 5), 356 SUNXI_CCU_GATE(A10_CLK_APB0_IR0, "apb0-ir0", "apb0", 357 APB0_GATING_REG, 6), 358 SUNXI_CCU_GATE(A10_CLK_APB0_IR1, "apb0-ir1", "apb0", 359 APB0_GATING_REG, 7), 360 SUNXI_CCU_GATE(A10_CLK_APB0_I2S2, "apb0-i2s2", "apb0", 361 APB0_GATING_REG, 8), 362 SUNXI_CCU_GATE(A10_CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 363 APB0_GATING_REG, 10), 364 365 /* APB1_GATING_REG */ 366 SUNXI_CCU_GATE(A10_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 367 APB1_GATING_REG, 0), 368 SUNXI_CCU_GATE(A10_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 369 APB1_GATING_REG, 1), 370 SUNXI_CCU_GATE(A10_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 371 APB1_GATING_REG, 2), 372 SUNXI_CCU_GATE(A10_CLK_APB1_I2C3, "apb1-i2c3", "apb1", 373 APB1_GATING_REG, 3), 374 SUNXI_CCU_GATE(A10_CLK_APB1_CAN, "apb1-can", "apb1", 375 APB1_GATING_REG, 4), 376 SUNXI_CCU_GATE(A10_CLK_APB1_SCR, "apb1-scr", "apb1", 377 APB1_GATING_REG, 5), 378 SUNXI_CCU_GATE(A10_CLK_APB1_PS20, "apb1-ps20", "apb1", 379 APB1_GATING_REG, 6), 380 SUNXI_CCU_GATE(A10_CLK_APB1_PS21, "apb1-ps21", "apb1", 381 APB1_GATING_REG, 7), 382 SUNXI_CCU_GATE(A10_CLK_APB1_I2C4, "apb1-i2c4", "apb1", 383 APB1_GATING_REG, 15), 384 SUNXI_CCU_GATE(A10_CLK_APB1_UART0, "apb1-uart0", "apb1", 385 APB1_GATING_REG, 16), 386 SUNXI_CCU_GATE(A10_CLK_APB1_UART1, "apb1-uart1", "apb1", 387 APB1_GATING_REG, 17), 388 SUNXI_CCU_GATE(A10_CLK_APB1_UART2, "apb1-uart2", "apb1", 389 APB1_GATING_REG, 18), 390 SUNXI_CCU_GATE(A10_CLK_APB1_UART3, "apb1-uart3", "apb1", 391 APB1_GATING_REG, 19), 392 SUNXI_CCU_GATE(A10_CLK_APB1_UART4, "apb1-uart4", "apb1", 393 APB1_GATING_REG, 20), 394 SUNXI_CCU_GATE(A10_CLK_APB1_UART5, "apb1-uart5", "apb1", 395 APB1_GATING_REG, 21), 396 SUNXI_CCU_GATE(A10_CLK_APB1_UART6, "apb1-uart6", "apb1", 397 APB1_GATING_REG, 22), 398 SUNXI_CCU_GATE(A10_CLK_APB1_UART7, "apb1-uart7", "apb1", 399 APB1_GATING_REG, 23), 400 401 /* AUDIO_CODEC_SCLK_CFG_REG */ 402 SUNXI_CCU_GATE(A10_CLK_CODEC, "codec", "pll_audio", 403 AUDIO_CODEC_SCLK_CFG_REG, 31), 404 405 /* USBPHY_CFG_REG */ 406 SUNXI_CCU_GATE(A10_CLK_USB_OHCI0, "usb-ohci0", "osc24m", 407 USBPHY_CFG_REG, 6), 408 SUNXI_CCU_GATE(A10_CLK_USB_OHCI1, "usb-ohci1", "osc24m", 409 USBPHY_CFG_REG, 7), 410 SUNXI_CCU_GATE(A10_CLK_USB_PHY, "usb-phy", "osc24m", 411 USBPHY_CFG_REG, 8), 412 }; 413 414 static int 415 sun4i_a10_ccu_match(device_t parent, cfdata_t cf, void *aux) 416 { 417 struct fdt_attach_args * const faa = aux; 418 419 return of_match_compat_data(faa->faa_phandle, compat_data); 420 } 421 422 static void 423 sun4i_a10_ccu_attach(device_t parent, device_t self, void *aux) 424 { 425 struct sunxi_ccu_softc * const sc = device_private(self); 426 struct fdt_attach_args * const faa = aux; 427 enum sun4i_a10_ccu_type type; 428 429 sc->sc_dev = self; 430 sc->sc_phandle = faa->faa_phandle; 431 sc->sc_bst = faa->faa_bst; 432 433 sc->sc_resets = sun4i_a10_ccu_resets; 434 sc->sc_nresets = __arraycount(sun4i_a10_ccu_resets); 435 436 sc->sc_clks = sun4i_a10_ccu_clks; 437 sc->sc_nclks = __arraycount(sun4i_a10_ccu_clks); 438 439 if (sunxi_ccu_attach(sc) != 0) 440 return; 441 442 aprint_naive("\n"); 443 444 type = of_search_compatible(faa->faa_phandle, compat_data)->data; 445 446 switch (type) { 447 case CCU_A10: 448 aprint_normal(": A10 CCU\n"); 449 break; 450 case CCU_A20: 451 aprint_normal(": A20 CCU\n"); 452 break; 453 } 454 455 sunxi_ccu_print(sc); 456 } 457
Indexes created Mon Oct 20 03:09:53 GMT 2025