sun4i_a10_ccu.c revision 1.6
1 /* $NetBSD: sun4i_a10_ccu.c,v 1.6 2017/12/16 16:40:33 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.6 2017/12/16 16:40:33 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun4i_a10_ccu.h> 42 #include <arm/sunxi/sun7i_a20_ccu.h> 43 44 #define PLL1_CFG_REG 0x000 45 #define PLL2_CFG_REG 0x008 46 #define PLL6_CFG_REG 0x028 47 #define OSC24M_CFG_REG 0x050 48 #define CPU_AHB_APB0_CFG_REG 0x054 49 #define APB1_CLK_DIV_REG 0x058 50 #define AHB_GATING_REG0 0x060 51 #define AHB_GATING_REG1 0x064 52 #define APB0_GATING_REG 0x068 53 #define APB1_GATING_REG 0x06c 54 #define NAND_SCLK_CFG_REG 0x080 55 #define SD0_SCLK_CFG_REG 0x088 56 #define SD1_SCLK_CFG_REG 0x08c 57 #define SD2_SCLK_CFG_REG 0x090 58 #define SD3_SCLK_CFG_REG 0x094 59 #define SATA_CFG_REG 0x0c8 60 #define USBPHY_CFG_REG 0x0cc 61 #define BE_CFG_REG 0x104 62 #define FE_CFG_REG 0x10c 63 #define CSI_CFG_REG 0x134 64 #define VE_CFG_REG 0x13c 65 #define AUDIO_CODEC_SCLK_CFG_REG 0x140 66 #define MALI_CLOCK_CFG_REG 0x154 67 #define IEP_SCLK_CFG_REG 0x160 68 69 static int sun4i_a10_ccu_match(device_t, cfdata_t, void *); 70 static void sun4i_a10_ccu_attach(device_t, device_t, void *); 71 72 enum sun4i_a10_ccu_type { 73 CCU_A10 = 1, 74 CCU_A20, 75 }; 76 77 static const struct of_compat_data compat_data[] = { 78 { "allwinner,sun4i-a10-ccu", CCU_A10 }, 79 { "allwinner,sun7i-a20-ccu", CCU_A20 }, 80 { NULL } 81 }; 82 83 CFATTACH_DECL_NEW(sunxi_a10_ccu, sizeof(struct sunxi_ccu_softc), 84 sun4i_a10_ccu_match, sun4i_a10_ccu_attach, NULL, NULL); 85 86 static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = { 87 SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0), 88 SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1), 89 SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2), 90 }; 91 92 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 93 static const char *axi_parents[] = { "cpu" }; 94 static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" }; 95 static const char *apb0_parents[] = { "ahb" }; 96 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; 97 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr" }; 98 static const char *sata_parents[] = { "pll6_periph_sata", "external" }; 99 100 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = { 101 { 1008000000, 21, 1, 0, 0 }, 102 { 960000000, 20, 1, 0, 0 }, 103 { 912000000, 19, 1, 0, 0 }, 104 { 864000000, 18, 1, 0, 0 }, 105 { 720000000, 30, 0, 0, 0 }, 106 { 624000000, 26, 0, 0, 0 }, 107 { 528000000, 22, 0, 0, 0 }, 108 { 312000000, 13, 0, 0, 0 }, 109 { 144000000, 12, 0, 0, 1 }, 110 { 0 } 111 }; 112 113 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = { 114 { 24576000, 86, 0, 21, 3 }, 115 { 0 } 116 }; 117 118 static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = { 119 SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc", 120 OSC24M_CFG_REG, 0), 121 122 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_CORE, "pll_core", "osc24m", 123 PLL1_CFG_REG, /* reg */ 124 __BITS(12,8), /* n */ 125 __BITS(5,4), /* k */ 126 __BITS(1,0), /* m */ 127 __BITS(17,16), /* p */ 128 __BIT(31), /* enable */ 129 0, /* lock */ 130 sun4i_a10_pll1_table, /* table */ 131 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT | 132 SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE | SUNXI_CCU_NKMP_SCALE_CLOCK), 133 134 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 135 PLL2_CFG_REG, /* reg */ 136 __BITS(14,8), /* n */ 137 0, /* k */ 138 __BITS(4,0), /* m */ 139 __BITS(29,26), /* p */ 140 __BIT(31), /* enable */ 141 0, /* lock */ 142 sun4i_a10_ac_dig_table, /* table */ 143 0), 144 145 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_BASE, "pll_periph_base", "osc24m", 146 PLL6_CFG_REG, /* reg */ 147 __BITS(12,8), /* n */ 148 __BITS(5,4), /* k */ 149 0, /* m */ 150 0, /* p */ 151 __BIT(31), /* enable */ 152 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 153 154 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_PERIPH, "pll_periph", "pll_periph_base", 155 2, 1), 156 157 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_SATA, "pll_periph_sata", "pll_periph_base", 158 PLL6_CFG_REG, /* reg */ 159 0, /* n */ 160 0, /* k */ 161 __BITS(1,0), /* m */ 162 0, /* p */ 163 __BIT(14), /* enable */ 164 0), 165 166 SUNXI_CCU_DIV_GATE(A10_CLK_SATA, "sata", sata_parents, 167 SATA_CFG_REG, /* reg */ 168 0, /* div */ 169 __BIT(24), /* sel */ 170 __BIT(31), /* enable */ 171 0), 172 173 SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents, 174 CPU_AHB_APB0_CFG_REG, /* reg */ 175 0, /* div */ 176 __BITS(17,16), /* sel */ 177 SUNXI_CCU_DIV_SET_RATE_PARENT), 178 179 SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents, 180 CPU_AHB_APB0_CFG_REG, /* reg */ 181 __BITS(1,0), /* div */ 182 0, /* sel */ 183 0), 184 185 SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents, 186 CPU_AHB_APB0_CFG_REG, /* reg */ 187 __BITS(5,4), /* div */ 188 __BITS(7,6), /* sel */ 189 SUNXI_CCU_DIV_POWER_OF_TWO), 190 191 SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents, 192 CPU_AHB_APB0_CFG_REG, /* reg */ 193 __BITS(9,8), /* div */ 194 0, /* sel */ 195 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 196 197 SUNXI_CCU_NM(A10_CLK_APB1, "apb1", apb1_parents, 198 APB1_CLK_DIV_REG, /* reg */ 199 __BITS(17,16), /* n */ 200 __BITS(4,0), /* m */ 201 __BITS(25,24), /* sel */ 202 0, /* enable */ 203 SUNXI_CCU_NM_POWER_OF_TWO), 204 205 SUNXI_CCU_NM(A10_CLK_NAND, "nand", mod_parents, 206 NAND_SCLK_CFG_REG, /* reg */ 207 __BITS(17,16), /* n */ 208 __BITS(3,0), /* m */ 209 __BITS(25,24), /* sel */ 210 __BIT(31), /* enable */ 211 SUNXI_CCU_NM_POWER_OF_TWO), 212 213 SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents, 214 SD0_SCLK_CFG_REG, /* reg */ 215 __BITS(17,16), /* n */ 216 __BITS(3,0), /* m */ 217 __BITS(25,24), /* sel */ 218 __BIT(31), /* enable */ 219 SUNXI_CCU_NM_POWER_OF_TWO), 220 SUNXI_CCU_PHASE(A10_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 221 SD0_SCLK_CFG_REG, __BITS(22,20)), 222 SUNXI_CCU_PHASE(A10_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 223 SD0_SCLK_CFG_REG, __BITS(10,8)), 224 SUNXI_CCU_NM(A10_CLK_MMC1, "mmc1", mod_parents, 225 SD1_SCLK_CFG_REG, /* reg */ 226 __BITS(17,16), /* n */ 227 __BITS(3,0), /* m */ 228 __BITS(25,24), /* sel */ 229 __BIT(31), /* enable */ 230 SUNXI_CCU_NM_POWER_OF_TWO), 231 SUNXI_CCU_PHASE(A10_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 232 SD1_SCLK_CFG_REG, __BITS(22,20)), 233 SUNXI_CCU_PHASE(A10_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 234 SD1_SCLK_CFG_REG, __BITS(10,8)), 235 SUNXI_CCU_NM(A10_CLK_MMC2, "mmc2", mod_parents, 236 SD2_SCLK_CFG_REG, /* reg */ 237 __BITS(17,16), /* n */ 238 __BITS(3,0), /* m */ 239 __BITS(25,24), /* sel */ 240 __BIT(31), /* enable */ 241 SUNXI_CCU_NM_POWER_OF_TWO), 242 SUNXI_CCU_PHASE(A10_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 243 SD2_SCLK_CFG_REG, __BITS(22,20)), 244 SUNXI_CCU_PHASE(A10_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 245 SD2_SCLK_CFG_REG, __BITS(10,8)), 246 SUNXI_CCU_NM(A10_CLK_MMC3, "mmc3", mod_parents, 247 SD3_SCLK_CFG_REG, /* reg */ 248 __BITS(17,16), /* n */ 249 __BITS(3,0), /* m */ 250 __BITS(25,24), /* sel */ 251 __BIT(31), /* enable */ 252 SUNXI_CCU_NM_POWER_OF_TWO), 253 SUNXI_CCU_PHASE(A10_CLK_MMC3_SAMPLE, "mmc3_sample", "mmc3", 254 SD3_SCLK_CFG_REG, __BITS(22,20)), 255 SUNXI_CCU_PHASE(A10_CLK_MMC3_OUTPUT, "mmc3_output", "mmc3", 256 SD3_SCLK_CFG_REG, __BITS(10,8)), 257 258 /* AHB_GATING_REG0 */ 259 SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb", 260 AHB_GATING_REG0, 0), 261 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 262 AHB_GATING_REG0, 1), 263 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 264 AHB_GATING_REG0, 2), 265 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 266 AHB_GATING_REG0, 3), 267 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 268 AHB_GATING_REG0, 4), 269 SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb", 270 AHB_GATING_REG0, 5), 271 SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb", 272 AHB_GATING_REG0, 6), 273 SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb", 274 AHB_GATING_REG0, 7), 275 SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 276 AHB_GATING_REG0, 8), 277 SUNXI_CCU_GATE(A10_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 278 AHB_GATING_REG0, 9), 279 SUNXI_CCU_GATE(A10_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 280 AHB_GATING_REG0, 10), 281 SUNXI_CCU_GATE(A10_CLK_AHB_MMC3, "ahb-mmc3", "ahb", 282 AHB_GATING_REG0, 11), 283 SUNXI_CCU_GATE(A10_CLK_AHB_MS, "ahb-ms", "ahb", 284 AHB_GATING_REG0, 12), 285 SUNXI_CCU_GATE(A10_CLK_AHB_NAND, "ahb-nand", "ahb", 286 AHB_GATING_REG0, 13), 287 SUNXI_CCU_GATE(A10_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 288 AHB_GATING_REG0, 14), 289 SUNXI_CCU_GATE(A10_CLK_AHB_ACE, "ahb-ace", "ahb", 290 AHB_GATING_REG0, 16), 291 SUNXI_CCU_GATE(A10_CLK_AHB_EMAC, "ahb-emac", "ahb", 292 AHB_GATING_REG0, 17), 293 SUNXI_CCU_GATE(A10_CLK_AHB_TS, "ahb-ts", "ahb", 294 AHB_GATING_REG0, 18), 295 SUNXI_CCU_GATE(A10_CLK_AHB_SPI0, "ahb-spi0", "ahb", 296 AHB_GATING_REG0, 20), 297 SUNXI_CCU_GATE(A10_CLK_AHB_SPI1, "ahb-spi1", "ahb", 298 AHB_GATING_REG0, 21), 299 SUNXI_CCU_GATE(A10_CLK_AHB_SPI2, "ahb-spi2", "ahb", 300 AHB_GATING_REG0, 22), 301 SUNXI_CCU_GATE(A10_CLK_AHB_SPI3, "ahb-spi3", "ahb", 302 AHB_GATING_REG0, 23), 303 SUNXI_CCU_GATE(A10_CLK_AHB_SATA, "ahb-sata", "ahb", 304 AHB_GATING_REG0, 25), 305 SUNXI_CCU_GATE(A10_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 306 AHB_GATING_REG0, 28), 307 308 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 309 SUNXI_CCU_GATE(A10_CLK_AHB_VE, "ahb-ve", "ahb", 310 AHB_GATING_REG1, 0), 311 SUNXI_CCU_GATE(A10_CLK_AHB_TVD, "ahb-tvd", "ahb", 312 AHB_GATING_REG1, 1), 313 SUNXI_CCU_GATE(A10_CLK_AHB_TVE0, "ahb-tve0", "ahb", 314 AHB_GATING_REG1, 2), 315 SUNXI_CCU_GATE(A10_CLK_AHB_TVE1, "ahb-tve1", "ahb", 316 AHB_GATING_REG1, 3), 317 SUNXI_CCU_GATE(A10_CLK_AHB_LCD0, "ahb-lcd0", "ahb", 318 AHB_GATING_REG1, 4), 319 SUNXI_CCU_GATE(A10_CLK_AHB_LCD1, "ahb-lcd1", "ahb", 320 AHB_GATING_REG1, 5), 321 SUNXI_CCU_GATE(A10_CLK_AHB_CSI0, "ahb-csi0", "ahb", 322 AHB_GATING_REG1, 8), 323 SUNXI_CCU_GATE(A10_CLK_AHB_CSI1, "ahb-csi1", "ahb", 324 AHB_GATING_REG1, 9), 325 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 326 AHB_GATING_REG1, 10), 327 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 328 AHB_GATING_REG1, 11), 329 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 330 AHB_GATING_REG1, 12), 331 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 332 AHB_GATING_REG1, 13), 333 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 334 AHB_GATING_REG1, 14), 335 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 336 AHB_GATING_REG1, 15), 337 SUNXI_CCU_GATE(A10_CLK_AHB_GMAC, "ahb-gmac", "ahb", 338 AHB_GATING_REG1, 17), 339 SUNXI_CCU_GATE(A10_CLK_AHB_MP, "ahb-mp", "ahb", 340 AHB_GATING_REG1, 18), 341 SUNXI_CCU_GATE(A10_CLK_AHB_GPU, "ahb-gpu", "ahb", 342 AHB_GATING_REG1, 20), 343 344 /* APB0_GATING_REG */ 345 SUNXI_CCU_GATE(A10_CLK_APB0_CODEC, "apb0-codec", "apb0", 346 APB0_GATING_REG, 0), 347 SUNXI_CCU_GATE(A10_CLK_APB0_SPDIF, "apb0-spdif", "apb0", 348 APB0_GATING_REG, 1), 349 SUNXI_CCU_GATE(A10_CLK_APB0_AC97, "apb0-ac97", "apb0", 350 APB0_GATING_REG, 2), 351 SUNXI_CCU_GATE(A10_CLK_APB0_I2S0, "apb0-i2s0", "apb0", 352 APB0_GATING_REG, 3), 353 SUNXI_CCU_GATE(A10_CLK_APB0_I2S1, "apb0-i2s1", "apb0", 354 APB0_GATING_REG, 4), 355 SUNXI_CCU_GATE(A10_CLK_APB0_PIO, "apb0-pio", "apb0", 356 APB0_GATING_REG, 5), 357 SUNXI_CCU_GATE(A10_CLK_APB0_IR0, "apb0-ir0", "apb0", 358 APB0_GATING_REG, 6), 359 SUNXI_CCU_GATE(A10_CLK_APB0_IR1, "apb0-ir1", "apb0", 360 APB0_GATING_REG, 7), 361 SUNXI_CCU_GATE(A10_CLK_APB0_I2S2, "apb0-i2s2", "apb0", 362 APB0_GATING_REG, 8), 363 SUNXI_CCU_GATE(A10_CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 364 APB0_GATING_REG, 10), 365 366 /* APB1_GATING_REG */ 367 SUNXI_CCU_GATE(A10_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 368 APB1_GATING_REG, 0), 369 SUNXI_CCU_GATE(A10_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 370 APB1_GATING_REG, 1), 371 SUNXI_CCU_GATE(A10_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 372 APB1_GATING_REG, 2), 373 SUNXI_CCU_GATE(A10_CLK_APB1_I2C3, "apb1-i2c3", "apb1", 374 APB1_GATING_REG, 3), 375 SUNXI_CCU_GATE(A10_CLK_APB1_CAN, "apb1-can", "apb1", 376 APB1_GATING_REG, 4), 377 SUNXI_CCU_GATE(A10_CLK_APB1_SCR, "apb1-scr", "apb1", 378 APB1_GATING_REG, 5), 379 SUNXI_CCU_GATE(A10_CLK_APB1_PS20, "apb1-ps20", "apb1", 380 APB1_GATING_REG, 6), 381 SUNXI_CCU_GATE(A10_CLK_APB1_PS21, "apb1-ps21", "apb1", 382 APB1_GATING_REG, 7), 383 SUNXI_CCU_GATE(A10_CLK_APB1_I2C4, "apb1-i2c4", "apb1", 384 APB1_GATING_REG, 15), 385 SUNXI_CCU_GATE(A10_CLK_APB1_UART0, "apb1-uart0", "apb1", 386 APB1_GATING_REG, 16), 387 SUNXI_CCU_GATE(A10_CLK_APB1_UART1, "apb1-uart1", "apb1", 388 APB1_GATING_REG, 17), 389 SUNXI_CCU_GATE(A10_CLK_APB1_UART2, "apb1-uart2", "apb1", 390 APB1_GATING_REG, 18), 391 SUNXI_CCU_GATE(A10_CLK_APB1_UART3, "apb1-uart3", "apb1", 392 APB1_GATING_REG, 19), 393 SUNXI_CCU_GATE(A10_CLK_APB1_UART4, "apb1-uart4", "apb1", 394 APB1_GATING_REG, 20), 395 SUNXI_CCU_GATE(A10_CLK_APB1_UART5, "apb1-uart5", "apb1", 396 APB1_GATING_REG, 21), 397 SUNXI_CCU_GATE(A10_CLK_APB1_UART6, "apb1-uart6", "apb1", 398 APB1_GATING_REG, 22), 399 SUNXI_CCU_GATE(A10_CLK_APB1_UART7, "apb1-uart7", "apb1", 400 APB1_GATING_REG, 23), 401 402 /* AUDIO_CODEC_SCLK_CFG_REG */ 403 SUNXI_CCU_GATE(A10_CLK_CODEC, "codec", "pll_audio", 404 AUDIO_CODEC_SCLK_CFG_REG, 31), 405 406 /* USBPHY_CFG_REG */ 407 SUNXI_CCU_GATE(A10_CLK_USB_OHCI0, "usb-ohci0", "osc24m", 408 USBPHY_CFG_REG, 6), 409 SUNXI_CCU_GATE(A10_CLK_USB_OHCI1, "usb-ohci1", "osc24m", 410 USBPHY_CFG_REG, 7), 411 SUNXI_CCU_GATE(A10_CLK_USB_PHY, "usb-phy", "osc24m", 412 USBPHY_CFG_REG, 8), 413 }; 414 415 static int 416 sun4i_a10_ccu_match(device_t parent, cfdata_t cf, void *aux) 417 { 418 struct fdt_attach_args * const faa = aux; 419 420 return of_match_compat_data(faa->faa_phandle, compat_data); 421 } 422 423 static void 424 sun4i_a10_ccu_attach(device_t parent, device_t self, void *aux) 425 { 426 struct sunxi_ccu_softc * const sc = device_private(self); 427 struct fdt_attach_args * const faa = aux; 428 enum sun4i_a10_ccu_type type; 429 430 sc->sc_dev = self; 431 sc->sc_phandle = faa->faa_phandle; 432 sc->sc_bst = faa->faa_bst; 433 434 sc->sc_resets = sun4i_a10_ccu_resets; 435 sc->sc_nresets = __arraycount(sun4i_a10_ccu_resets); 436 437 sc->sc_clks = sun4i_a10_ccu_clks; 438 sc->sc_nclks = __arraycount(sun4i_a10_ccu_clks); 439 440 if (sunxi_ccu_attach(sc) != 0) 441 return; 442 443 aprint_naive("\n"); 444 445 type = of_search_compatible(faa->faa_phandle, compat_data)->data; 446 447 switch (type) { 448 case CCU_A10: 449 aprint_normal(": A10 CCU\n"); 450 break; 451 case CCU_A20: 452 aprint_normal(": A20 CCU\n"); 453 break; 454 } 455 456 sunxi_ccu_print(sc); 457 } 458
Indexes created Thu Oct 02 01:09:59 GMT 2025