sun4i_a10_ccu.c revision 1.7
1 /* $NetBSD: sun4i_a10_ccu.c,v 1.7 2018/03/19 16:18:30 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.7 2018/03/19 16:18:30 bouyer Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun4i_a10_ccu.h> 42 #include <arm/sunxi/sun7i_a20_ccu.h> 43 44 #define PLL1_CFG_REG 0x000 45 #define PLL2_CFG_REG 0x008 46 #define PLL3_CFG_REG 0x010 47 #define PLL5_CFG_REG 0x020 48 #define PLL6_CFG_REG 0x028 49 #define PLL7_CFG_REG 0x030 50 #define OSC24M_CFG_REG 0x050 51 #define CPU_AHB_APB0_CFG_REG 0x054 52 #define APB1_CLK_DIV_REG 0x058 53 #define AHB_GATING_REG0 0x060 54 #define AHB_GATING_REG1 0x064 55 #define APB0_GATING_REG 0x068 56 #define APB1_GATING_REG 0x06c 57 #define NAND_SCLK_CFG_REG 0x080 58 #define SD0_SCLK_CFG_REG 0x088 59 #define SD1_SCLK_CFG_REG 0x08c 60 #define SD2_SCLK_CFG_REG 0x090 61 #define SD3_SCLK_CFG_REG 0x094 62 #define SATA_CFG_REG 0x0c8 63 #define USBPHY_CFG_REG 0x0cc 64 #define DRAM_GATING_REG 0x100 65 #define BE0_CFG_REG 0x104 66 #define BE1_CFG_REG 0x108 67 #define FE0_CFG_REG 0x10c 68 #define FE1_CFG_REG 0x110 69 #define MP_CFG_REG 0x114 70 #define LCD0CH0_CFG_REG 0x118 71 #define LCD1CH0_CFG_REG 0x11c 72 #define LCD0CH1_CFG_REG 0x12c 73 #define LCD1CH1_CFG_REG 0x130 74 #define CSI_CFG_REG 0x134 75 #define VE_CFG_REG 0x13c 76 #define AUDIO_CODEC_SCLK_CFG_REG 0x140 77 #define HDMI_CLOCK_CFG_REG 0x150 78 #define MALI_CLOCK_CFG_REG 0x154 79 #define IEP_SCLK_CFG_REG 0x160 80 81 static int sun4i_a10_ccu_match(device_t, cfdata_t, void *); 82 static void sun4i_a10_ccu_attach(device_t, device_t, void *); 83 84 enum sun4i_a10_ccu_type { 85 CCU_A10 = 1, 86 CCU_A20, 87 }; 88 89 static const struct of_compat_data compat_data[] = { 90 { "allwinner,sun4i-a10-ccu", CCU_A10 }, 91 { "allwinner,sun7i-a20-ccu", CCU_A20 }, 92 { NULL } 93 }; 94 95 CFATTACH_DECL_NEW(sunxi_a10_ccu, sizeof(struct sunxi_ccu_softc), 96 sun4i_a10_ccu_match, sun4i_a10_ccu_attach, NULL, NULL); 97 98 static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = { 99 SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0), 100 SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1), 101 SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2), 102 SUNXI_CCU_RESET(A10_RST_DE_BE0, BE0_CFG_REG, 30), 103 SUNXI_CCU_RESET(A10_RST_DE_BE1, BE1_CFG_REG, 30), 104 SUNXI_CCU_RESET(A10_RST_DE_FE0, FE0_CFG_REG, 30), 105 SUNXI_CCU_RESET(A10_RST_DE_FE1, FE1_CFG_REG, 30), 106 SUNXI_CCU_RESET(A10_RST_DE_MP, MP_CFG_REG, 30), 107 SUNXI_CCU_RESET(A10_RST_TCON0, LCD0CH0_CFG_REG, 30), 108 SUNXI_CCU_RESET(A10_RST_TCON1, LCD1CH0_CFG_REG, 30), 109 }; 110 111 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 112 static const char *axi_parents[] = { "cpu" }; 113 static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" }; 114 static const char *apb0_parents[] = { "ahb" }; 115 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; 116 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr_other" }; 117 static const char *sata_parents[] = { "pll6_periph_sata", "external" }; 118 static const char *de_parents[] = { "pll_video0", "pll_video1", "pll_ddr_other" }; 119 static const char *lcd0_parents[] = { "pll_video0", "pll_video1", "pll_video0x2" }; 120 static const char *lcd1_parents[] = { "pll_video0", "pll_video1", "pll_video0x2", "pll_video1x2" }; 121 static const char *lcd0ch1c2[] = { "tcon0-ch1-clk2" }; 122 static const char *lcd1ch1c2[] = { "tcon1-ch1-clk2" }; 123 124 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = { 125 { 1008000000, 21, 1, 0, 0 }, 126 { 960000000, 20, 1, 0, 0 }, 127 { 912000000, 19, 1, 0, 0 }, 128 { 864000000, 18, 1, 0, 0 }, 129 { 720000000, 30, 0, 0, 0 }, 130 { 624000000, 26, 0, 0, 0 }, 131 { 528000000, 22, 0, 0, 0 }, 132 { 312000000, 13, 0, 0, 0 }, 133 { 144000000, 12, 0, 0, 1 }, 134 { 0 } 135 }; 136 137 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = { 138 { 24576000, 86, 0, 21, 3 }, 139 { 0 } 140 }; 141 142 static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = { 143 SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc", 144 OSC24M_CFG_REG, 0), 145 146 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_CORE, "pll_core", "osc24m", 147 PLL1_CFG_REG, /* reg */ 148 __BITS(12,8), /* n */ 149 __BITS(5,4), /* k */ 150 __BITS(1,0), /* m */ 151 __BITS(17,16), /* p */ 152 __BIT(31), /* enable */ 153 0, /* lock */ 154 sun4i_a10_pll1_table, /* table */ 155 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT | 156 SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE | SUNXI_CCU_NKMP_SCALE_CLOCK), 157 158 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 159 PLL2_CFG_REG, /* reg */ 160 __BITS(14,8), /* n */ 161 0, /* k */ 162 __BITS(4,0), /* m */ 163 __BITS(29,26), /* p */ 164 __BIT(31), /* enable */ 165 0, /* lock */ 166 sun4i_a10_ac_dig_table, /* table */ 167 0), 168 169 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_BASE, "pll_periph_base", "osc24m", 170 PLL6_CFG_REG, /* reg */ 171 __BITS(12,8), /* n */ 172 __BITS(5,4), /* k */ 173 0, /* m */ 174 0, /* p */ 175 __BIT(31), /* enable */ 176 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 177 178 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_PERIPH, "pll_periph", "pll_periph_base", 179 2, 1), 180 181 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_SATA, "pll_periph_sata", "pll_periph_base", 182 PLL6_CFG_REG, /* reg */ 183 0, /* n */ 184 0, /* k */ 185 __BITS(1,0), /* m */ 186 0, /* p */ 187 __BIT(14), /* enable */ 188 0), 189 190 SUNXI_CCU_DIV_GATE(A10_CLK_SATA, "sata", sata_parents, 191 SATA_CFG_REG, /* reg */ 192 0, /* div */ 193 __BIT(24), /* sel */ 194 __BIT(31), /* enable */ 195 0), 196 197 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR_BASE, "pll_ddr_other", "osc24m", 198 PLL5_CFG_REG, /* reg */ 199 __BITS(12, 8), /* n */ 200 __BITS(5,4), /* k */ 201 0, /* m */ 202 __BITS(17,16), /* p */ 203 __BIT(31), /* enable */ 204 SUNXI_CCU_NKMP_FACTOR_N_EXACT | SUNXI_CCU_NKMP_FACTOR_P_POW2), 205 206 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR, "pll_ddr", "osc24m", 207 PLL5_CFG_REG, /* reg */ 208 __BITS(12, 8), /* n */ 209 __BITS(5,4), /* k */ 210 __BITS(1,0), /* m */ 211 0, /* p */ 212 __BIT(31), /* enable */ 213 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 214 215 SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents, 216 CPU_AHB_APB0_CFG_REG, /* reg */ 217 0, /* div */ 218 __BITS(17,16), /* sel */ 219 SUNXI_CCU_DIV_SET_RATE_PARENT), 220 221 SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents, 222 CPU_AHB_APB0_CFG_REG, /* reg */ 223 __BITS(1,0), /* div */ 224 0, /* sel */ 225 0), 226 227 SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents, 228 CPU_AHB_APB0_CFG_REG, /* reg */ 229 __BITS(5,4), /* div */ 230 __BITS(7,6), /* sel */ 231 SUNXI_CCU_DIV_POWER_OF_TWO), 232 233 SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents, 234 CPU_AHB_APB0_CFG_REG, /* reg */ 235 __BITS(9,8), /* div */ 236 0, /* sel */ 237 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 238 239 SUNXI_CCU_NM(A10_CLK_APB1, "apb1", apb1_parents, 240 APB1_CLK_DIV_REG, /* reg */ 241 __BITS(17,16), /* n */ 242 __BITS(4,0), /* m */ 243 __BITS(25,24), /* sel */ 244 0, /* enable */ 245 SUNXI_CCU_NM_POWER_OF_TWO), 246 247 SUNXI_CCU_NM(A10_CLK_NAND, "nand", mod_parents, 248 NAND_SCLK_CFG_REG, /* reg */ 249 __BITS(17,16), /* n */ 250 __BITS(3,0), /* m */ 251 __BITS(25,24), /* sel */ 252 __BIT(31), /* enable */ 253 SUNXI_CCU_NM_POWER_OF_TWO), 254 255 SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents, 256 SD0_SCLK_CFG_REG, /* reg */ 257 __BITS(17,16), /* n */ 258 __BITS(3,0), /* m */ 259 __BITS(25,24), /* sel */ 260 __BIT(31), /* enable */ 261 SUNXI_CCU_NM_POWER_OF_TWO), 262 SUNXI_CCU_PHASE(A10_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 263 SD0_SCLK_CFG_REG, __BITS(22,20)), 264 SUNXI_CCU_PHASE(A10_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 265 SD0_SCLK_CFG_REG, __BITS(10,8)), 266 SUNXI_CCU_NM(A10_CLK_MMC1, "mmc1", mod_parents, 267 SD1_SCLK_CFG_REG, /* reg */ 268 __BITS(17,16), /* n */ 269 __BITS(3,0), /* m */ 270 __BITS(25,24), /* sel */ 271 __BIT(31), /* enable */ 272 SUNXI_CCU_NM_POWER_OF_TWO), 273 SUNXI_CCU_PHASE(A10_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 274 SD1_SCLK_CFG_REG, __BITS(22,20)), 275 SUNXI_CCU_PHASE(A10_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 276 SD1_SCLK_CFG_REG, __BITS(10,8)), 277 SUNXI_CCU_NM(A10_CLK_MMC2, "mmc2", mod_parents, 278 SD2_SCLK_CFG_REG, /* reg */ 279 __BITS(17,16), /* n */ 280 __BITS(3,0), /* m */ 281 __BITS(25,24), /* sel */ 282 __BIT(31), /* enable */ 283 SUNXI_CCU_NM_POWER_OF_TWO), 284 SUNXI_CCU_PHASE(A10_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 285 SD2_SCLK_CFG_REG, __BITS(22,20)), 286 SUNXI_CCU_PHASE(A10_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 287 SD2_SCLK_CFG_REG, __BITS(10,8)), 288 SUNXI_CCU_NM(A10_CLK_MMC3, "mmc3", mod_parents, 289 SD3_SCLK_CFG_REG, /* reg */ 290 __BITS(17,16), /* n */ 291 __BITS(3,0), /* m */ 292 __BITS(25,24), /* sel */ 293 __BIT(31), /* enable */ 294 SUNXI_CCU_NM_POWER_OF_TWO), 295 SUNXI_CCU_PHASE(A10_CLK_MMC3_SAMPLE, "mmc3_sample", "mmc3", 296 SD3_SCLK_CFG_REG, __BITS(22,20)), 297 SUNXI_CCU_PHASE(A10_CLK_MMC3_OUTPUT, "mmc3_output", "mmc3", 298 SD3_SCLK_CFG_REG, __BITS(10,8)), 299 300 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO0, "pll_video0", "osc24m", 301 PLL3_CFG_REG, /* reg */ 302 __BITS(7,0), /* m */ 303 9, /* m_min */ 304 127, /* m_max */ 305 __BIT(15), /* frac_en */ 306 __BIT(14), /* frac_sel */ 307 270000000, 297000000, /* frac values */ 308 8, /* prediv */ 309 __BIT(31) /* enable */ 310 ), 311 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO1, "pll_video1", "osc24m", 312 PLL7_CFG_REG, /* reg */ 313 __BITS(7,0), /* m */ 314 9, /* m_min */ 315 127, /* m_max */ 316 __BIT(15), /* frac_en */ 317 __BIT(14), /* frac_sel */ 318 270000000, 297000000, /* frac values */ 319 8, /* prediv */ 320 __BIT(31) /* enable */ 321 ), 322 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO0_2X, 323 "pll_video0x2", "pll_video0", 324 1, 2), 325 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO1_2X, 326 "pll_video1x2", "pll_video1", 327 1, 2), 328 329 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE0, "debe0-mod", de_parents, 330 BE0_CFG_REG, /* reg */ 331 __BITS(3,0), /* div */ 332 __BITS(25,24), /* sel */ 333 __BIT(31), /* enable */ 334 0 /* flags */ 335 ), 336 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE1, "debe1-mod", de_parents, 337 BE1_CFG_REG, /* reg */ 338 __BITS(3,0), /* div */ 339 __BITS(25,24), /* sel */ 340 __BIT(31), /* enable */ 341 0 /* flags */ 342 ), 343 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE0, "defe0-mod", de_parents, 344 FE0_CFG_REG, /* reg */ 345 __BITS(3,0), /* div */ 346 __BITS(25,24), /* sel */ 347 __BIT(31), /* enable */ 348 0 /* flags */ 349 ), 350 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE1, "defe1-mod", de_parents, 351 FE1_CFG_REG, /* reg */ 352 __BITS(3,0), /* div */ 353 __BITS(25,24), /* sel */ 354 __BIT(31), /* enable */ 355 0 /* flags */ 356 ), 357 SUNXI_CCU_DIV_GATE(A10_CLK_TCON0_CH0, "tcon0-ch0", lcd0_parents, 358 LCD0CH0_CFG_REG, /* reg */ 359 0, /* div */ 360 __BITS(25,24), /* sel */ 361 __BIT(31), /* enable */ 362 SUNXI_CCU_DIV_SET_RATE_PARENT /* flags */ 363 ), 364 SUNXI_CCU_DIV_GATE(A10_CLK_TCON1_CH0, "tcon1-ch0", lcd1_parents, 365 LCD1CH0_CFG_REG, /* reg */ 366 0, /* div */ 367 __BITS(25,24), /* sel */ 368 __BIT(31), /* enable */ 369 SUNXI_CCU_DIV_SET_RATE_PARENT /* flags */ 370 ), 371 SUNXI_CCU_DIV_GATE(A10_CLK_TCON0_CH1_SCLK2, "tcon0-ch1-clk2", lcd1_parents, 372 LCD0CH1_CFG_REG, /* reg */ 373 __BITS(3,0), /* div */ 374 __BITS(25,24), /* sel */ 375 __BIT(31), /* enable */ 376 SUNXI_CCU_DIV_SET_RATE_PARENT /* flags */ 377 ), 378 SUNXI_CCU_DIV_GATE(A10_CLK_TCON0_CH1, "tcon0-ch1", lcd0ch1c2, 379 LCD0CH1_CFG_REG, /* reg */ 380 __BIT(11), /* div */ 381 0, /* sel */ 382 __BIT(15), /* enable */ 383 SUNXI_CCU_DIV_SET_RATE_PARENT /* flags */ 384 ), 385 SUNXI_CCU_DIV_GATE(A10_CLK_TCON1_CH1_SCLK2, "tcon1-ch1-clk2", lcd1_parents, 386 LCD1CH1_CFG_REG, /* reg */ 387 __BITS(3,0), /* div */ 388 __BITS(25,24), /* sel */ 389 __BIT(31), /* enable */ 390 SUNXI_CCU_DIV_SET_RATE_PARENT /* flags */ 391 ), 392 SUNXI_CCU_DIV_GATE(A10_CLK_TCON1_CH1, "tcon1-ch1", lcd1ch1c2, 393 LCD1CH1_CFG_REG, /* reg */ 394 __BIT(11), /* div */ 395 0, /* sel */ 396 __BIT(15), /* enable */ 397 SUNXI_CCU_DIV_SET_RATE_PARENT /* flags */ 398 ), 399 SUNXI_CCU_DIV_GATE(A10_CLK_HDMI, "hdmi-mod", lcd1_parents, 400 HDMI_CLOCK_CFG_REG, /* reg */ 401 __BITS(3,0), /* div */ 402 __BITS(25,24), /* sel */ 403 __BIT(31), /* enable */ 404 0 /* flags */ 405 ), 406 407 /* AHB_GATING_REG0 */ 408 SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb", 409 AHB_GATING_REG0, 0), 410 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 411 AHB_GATING_REG0, 1), 412 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 413 AHB_GATING_REG0, 2), 414 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 415 AHB_GATING_REG0, 3), 416 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 417 AHB_GATING_REG0, 4), 418 SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb", 419 AHB_GATING_REG0, 5), 420 SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb", 421 AHB_GATING_REG0, 6), 422 SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb", 423 AHB_GATING_REG0, 7), 424 SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 425 AHB_GATING_REG0, 8), 426 SUNXI_CCU_GATE(A10_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 427 AHB_GATING_REG0, 9), 428 SUNXI_CCU_GATE(A10_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 429 AHB_GATING_REG0, 10), 430 SUNXI_CCU_GATE(A10_CLK_AHB_MMC3, "ahb-mmc3", "ahb", 431 AHB_GATING_REG0, 11), 432 SUNXI_CCU_GATE(A10_CLK_AHB_MS, "ahb-ms", "ahb", 433 AHB_GATING_REG0, 12), 434 SUNXI_CCU_GATE(A10_CLK_AHB_NAND, "ahb-nand", "ahb", 435 AHB_GATING_REG0, 13), 436 SUNXI_CCU_GATE(A10_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 437 AHB_GATING_REG0, 14), 438 SUNXI_CCU_GATE(A10_CLK_AHB_ACE, "ahb-ace", "ahb", 439 AHB_GATING_REG0, 16), 440 SUNXI_CCU_GATE(A10_CLK_AHB_EMAC, "ahb-emac", "ahb", 441 AHB_GATING_REG0, 17), 442 SUNXI_CCU_GATE(A10_CLK_AHB_TS, "ahb-ts", "ahb", 443 AHB_GATING_REG0, 18), 444 SUNXI_CCU_GATE(A10_CLK_AHB_SPI0, "ahb-spi0", "ahb", 445 AHB_GATING_REG0, 20), 446 SUNXI_CCU_GATE(A10_CLK_AHB_SPI1, "ahb-spi1", "ahb", 447 AHB_GATING_REG0, 21), 448 SUNXI_CCU_GATE(A10_CLK_AHB_SPI2, "ahb-spi2", "ahb", 449 AHB_GATING_REG0, 22), 450 SUNXI_CCU_GATE(A10_CLK_AHB_SPI3, "ahb-spi3", "ahb", 451 AHB_GATING_REG0, 23), 452 SUNXI_CCU_GATE(A10_CLK_AHB_SATA, "ahb-sata", "ahb", 453 AHB_GATING_REG0, 25), 454 SUNXI_CCU_GATE(A10_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 455 AHB_GATING_REG0, 28), 456 457 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 458 SUNXI_CCU_GATE(A10_CLK_AHB_VE, "ahb-ve", "ahb", 459 AHB_GATING_REG1, 0), 460 SUNXI_CCU_GATE(A10_CLK_AHB_TVD, "ahb-tvd", "ahb", 461 AHB_GATING_REG1, 1), 462 SUNXI_CCU_GATE(A10_CLK_AHB_TVE0, "ahb-tve0", "ahb", 463 AHB_GATING_REG1, 2), 464 SUNXI_CCU_GATE(A10_CLK_AHB_TVE1, "ahb-tve1", "ahb", 465 AHB_GATING_REG1, 3), 466 SUNXI_CCU_GATE(A10_CLK_AHB_LCD0, "ahb-lcd0", "ahb", 467 AHB_GATING_REG1, 4), 468 SUNXI_CCU_GATE(A10_CLK_AHB_LCD1, "ahb-lcd1", "ahb", 469 AHB_GATING_REG1, 5), 470 SUNXI_CCU_GATE(A10_CLK_AHB_CSI0, "ahb-csi0", "ahb", 471 AHB_GATING_REG1, 8), 472 SUNXI_CCU_GATE(A10_CLK_AHB_CSI1, "ahb-csi1", "ahb", 473 AHB_GATING_REG1, 9), 474 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 475 AHB_GATING_REG1, 10), 476 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 477 AHB_GATING_REG1, 11), 478 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 479 AHB_GATING_REG1, 12), 480 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 481 AHB_GATING_REG1, 13), 482 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 483 AHB_GATING_REG1, 14), 484 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 485 AHB_GATING_REG1, 15), 486 SUNXI_CCU_GATE(A10_CLK_AHB_GMAC, "ahb-gmac", "ahb", 487 AHB_GATING_REG1, 17), 488 SUNXI_CCU_GATE(A10_CLK_AHB_MP, "ahb-mp", "ahb", 489 AHB_GATING_REG1, 18), 490 SUNXI_CCU_GATE(A10_CLK_AHB_GPU, "ahb-gpu", "ahb", 491 AHB_GATING_REG1, 20), 492 493 /* APB0_GATING_REG */ 494 SUNXI_CCU_GATE(A10_CLK_APB0_CODEC, "apb0-codec", "apb0", 495 APB0_GATING_REG, 0), 496 SUNXI_CCU_GATE(A10_CLK_APB0_SPDIF, "apb0-spdif", "apb0", 497 APB0_GATING_REG, 1), 498 SUNXI_CCU_GATE(A10_CLK_APB0_AC97, "apb0-ac97", "apb0", 499 APB0_GATING_REG, 2), 500 SUNXI_CCU_GATE(A10_CLK_APB0_I2S0, "apb0-i2s0", "apb0", 501 APB0_GATING_REG, 3), 502 SUNXI_CCU_GATE(A10_CLK_APB0_I2S1, "apb0-i2s1", "apb0", 503 APB0_GATING_REG, 4), 504 SUNXI_CCU_GATE(A10_CLK_APB0_PIO, "apb0-pio", "apb0", 505 APB0_GATING_REG, 5), 506 SUNXI_CCU_GATE(A10_CLK_APB0_IR0, "apb0-ir0", "apb0", 507 APB0_GATING_REG, 6), 508 SUNXI_CCU_GATE(A10_CLK_APB0_IR1, "apb0-ir1", "apb0", 509 APB0_GATING_REG, 7), 510 SUNXI_CCU_GATE(A10_CLK_APB0_I2S2, "apb0-i2s2", "apb0", 511 APB0_GATING_REG, 8), 512 SUNXI_CCU_GATE(A10_CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 513 APB0_GATING_REG, 10), 514 515 /* APB1_GATING_REG */ 516 SUNXI_CCU_GATE(A10_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 517 APB1_GATING_REG, 0), 518 SUNXI_CCU_GATE(A10_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 519 APB1_GATING_REG, 1), 520 SUNXI_CCU_GATE(A10_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 521 APB1_GATING_REG, 2), 522 SUNXI_CCU_GATE(A10_CLK_APB1_I2C3, "apb1-i2c3", "apb1", 523 APB1_GATING_REG, 3), 524 SUNXI_CCU_GATE(A10_CLK_APB1_CAN, "apb1-can", "apb1", 525 APB1_GATING_REG, 4), 526 SUNXI_CCU_GATE(A10_CLK_APB1_SCR, "apb1-scr", "apb1", 527 APB1_GATING_REG, 5), 528 SUNXI_CCU_GATE(A10_CLK_APB1_PS20, "apb1-ps20", "apb1", 529 APB1_GATING_REG, 6), 530 SUNXI_CCU_GATE(A10_CLK_APB1_PS21, "apb1-ps21", "apb1", 531 APB1_GATING_REG, 7), 532 SUNXI_CCU_GATE(A10_CLK_APB1_I2C4, "apb1-i2c4", "apb1", 533 APB1_GATING_REG, 15), 534 SUNXI_CCU_GATE(A10_CLK_APB1_UART0, "apb1-uart0", "apb1", 535 APB1_GATING_REG, 16), 536 SUNXI_CCU_GATE(A10_CLK_APB1_UART1, "apb1-uart1", "apb1", 537 APB1_GATING_REG, 17), 538 SUNXI_CCU_GATE(A10_CLK_APB1_UART2, "apb1-uart2", "apb1", 539 APB1_GATING_REG, 18), 540 SUNXI_CCU_GATE(A10_CLK_APB1_UART3, "apb1-uart3", "apb1", 541 APB1_GATING_REG, 19), 542 SUNXI_CCU_GATE(A10_CLK_APB1_UART4, "apb1-uart4", "apb1", 543 APB1_GATING_REG, 20), 544 SUNXI_CCU_GATE(A10_CLK_APB1_UART5, "apb1-uart5", "apb1", 545 APB1_GATING_REG, 21), 546 SUNXI_CCU_GATE(A10_CLK_APB1_UART6, "apb1-uart6", "apb1", 547 APB1_GATING_REG, 22), 548 SUNXI_CCU_GATE(A10_CLK_APB1_UART7, "apb1-uart7", "apb1", 549 APB1_GATING_REG, 23), 550 551 /* DRAM GATING */ 552 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE0, "dram-de-be0", "pll_ddr_other", 553 DRAM_GATING_REG, 26), 554 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE1, "dram-de-be1", "pll_ddr_other", 555 DRAM_GATING_REG, 27), 556 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE0, "dram-de-fe0", "pll_ddr_other", 557 DRAM_GATING_REG, 25), 558 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE1, "dram-de-fe1", "pll_ddr_other", 559 DRAM_GATING_REG, 24), 560 561 /* AUDIO_CODEC_SCLK_CFG_REG */ 562 SUNXI_CCU_GATE(A10_CLK_CODEC, "codec", "pll_audio", 563 AUDIO_CODEC_SCLK_CFG_REG, 31), 564 565 /* USBPHY_CFG_REG */ 566 SUNXI_CCU_GATE(A10_CLK_USB_OHCI0, "usb-ohci0", "osc24m", 567 USBPHY_CFG_REG, 6), 568 SUNXI_CCU_GATE(A10_CLK_USB_OHCI1, "usb-ohci1", "osc24m", 569 USBPHY_CFG_REG, 7), 570 SUNXI_CCU_GATE(A10_CLK_USB_PHY, "usb-phy", "osc24m", 571 USBPHY_CFG_REG, 8), 572 }; 573 574 static int 575 sun4i_a10_ccu_match(device_t parent, cfdata_t cf, void *aux) 576 { 577 struct fdt_attach_args * const faa = aux; 578 579 return of_match_compat_data(faa->faa_phandle, compat_data); 580 } 581 582 static void 583 sun4i_a10_ccu_attach(device_t parent, device_t self, void *aux) 584 { 585 struct sunxi_ccu_softc * const sc = device_private(self); 586 struct fdt_attach_args * const faa = aux; 587 enum sun4i_a10_ccu_type type; 588 589 sc->sc_dev = self; 590 sc->sc_phandle = faa->faa_phandle; 591 sc->sc_bst = faa->faa_bst; 592 593 sc->sc_resets = sun4i_a10_ccu_resets; 594 sc->sc_nresets = __arraycount(sun4i_a10_ccu_resets); 595 596 sc->sc_clks = sun4i_a10_ccu_clks; 597 sc->sc_nclks = __arraycount(sun4i_a10_ccu_clks); 598 599 if (sunxi_ccu_attach(sc) != 0) 600 return; 601 602 aprint_naive("\n"); 603 604 type = of_search_compatible(faa->faa_phandle, compat_data)->data; 605 606 switch (type) { 607 case CCU_A10: 608 aprint_normal(": A10 CCU\n"); 609 break; 610 case CCU_A20: 611 aprint_normal(": A20 CCU\n"); 612 break; 613 } 614 615 sunxi_ccu_print(sc); 616 } 617
Indexes created Thu Oct 02 01:09:59 GMT 2025