sun4i_a10_ccu.c revision 1.8
1 /* $NetBSD: sun4i_a10_ccu.c,v 1.8 2018/04/01 21:19:17 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.8 2018/04/01 21:19:17 bouyer Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun4i_a10_ccu.h> 42 #include <arm/sunxi/sun7i_a20_ccu.h> 43 44 #define PLL1_CFG_REG 0x000 45 #define PLL2_CFG_REG 0x008 46 #define PLL3_CFG_REG 0x010 47 #define PLL5_CFG_REG 0x020 48 #define PLL6_CFG_REG 0x028 49 #define PLL7_CFG_REG 0x030 50 #define OSC24M_CFG_REG 0x050 51 #define CPU_AHB_APB0_CFG_REG 0x054 52 #define APB1_CLK_DIV_REG 0x058 53 #define AHB_GATING_REG0 0x060 54 #define AHB_GATING_REG1 0x064 55 #define APB0_GATING_REG 0x068 56 #define APB1_GATING_REG 0x06c 57 #define NAND_SCLK_CFG_REG 0x080 58 #define SD0_SCLK_CFG_REG 0x088 59 #define SD1_SCLK_CFG_REG 0x08c 60 #define SD2_SCLK_CFG_REG 0x090 61 #define SD3_SCLK_CFG_REG 0x094 62 #define SATA_CFG_REG 0x0c8 63 #define USBPHY_CFG_REG 0x0cc 64 #define DRAM_GATING_REG 0x100 65 #define BE0_CFG_REG 0x104 66 #define BE1_CFG_REG 0x108 67 #define FE0_CFG_REG 0x10c 68 #define FE1_CFG_REG 0x110 69 #define MP_CFG_REG 0x114 70 #define LCD0CH0_CFG_REG 0x118 71 #define LCD1CH0_CFG_REG 0x11c 72 #define LCD0CH1_CFG_REG 0x12c 73 #define LCD1CH1_CFG_REG 0x130 74 #define CSI_CFG_REG 0x134 75 #define VE_CFG_REG 0x13c 76 #define AUDIO_CODEC_SCLK_CFG_REG 0x140 77 #define HDMI_CLOCK_CFG_REG 0x150 78 #define MALI_CLOCK_CFG_REG 0x154 79 #define IEP_SCLK_CFG_REG 0x160 80 81 static int sun4i_a10_ccu_match(device_t, cfdata_t, void *); 82 static void sun4i_a10_ccu_attach(device_t, device_t, void *); 83 84 enum sun4i_a10_ccu_type { 85 CCU_A10 = 1, 86 CCU_A20, 87 }; 88 89 static const struct of_compat_data compat_data[] = { 90 { "allwinner,sun4i-a10-ccu", CCU_A10 }, 91 { "allwinner,sun7i-a20-ccu", CCU_A20 }, 92 { NULL } 93 }; 94 95 CFATTACH_DECL_NEW(sunxi_a10_ccu, sizeof(struct sunxi_ccu_softc), 96 sun4i_a10_ccu_match, sun4i_a10_ccu_attach, NULL, NULL); 97 98 static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = { 99 SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0), 100 SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1), 101 SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2), 102 SUNXI_CCU_RESET(A10_RST_DE_BE0, BE0_CFG_REG, 30), 103 SUNXI_CCU_RESET(A10_RST_DE_BE1, BE1_CFG_REG, 30), 104 SUNXI_CCU_RESET(A10_RST_DE_FE0, FE0_CFG_REG, 30), 105 SUNXI_CCU_RESET(A10_RST_DE_FE1, FE1_CFG_REG, 30), 106 SUNXI_CCU_RESET(A10_RST_DE_MP, MP_CFG_REG, 30), 107 SUNXI_CCU_RESET(A10_RST_TCON0, LCD0CH0_CFG_REG, 30), 108 SUNXI_CCU_RESET(A10_RST_TCON1, LCD1CH0_CFG_REG, 30), 109 }; 110 111 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 112 static const char *axi_parents[] = { "cpu" }; 113 static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" }; 114 static const char *apb0_parents[] = { "ahb" }; 115 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; 116 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr_other" }; 117 static const char *sata_parents[] = { "pll6_periph_sata", "external" }; 118 static const char *de_parents[] = { "pll_video0", "pll_video1", "pll_ddr_other" }; 119 static const char *lcd_parents[] = { "pll_video0", "pll_video1", "pll_video0x2", "pll_video1x2" }; 120 121 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = { 122 { 1008000000, 21, 1, 0, 0 }, 123 { 960000000, 20, 1, 0, 0 }, 124 { 912000000, 19, 1, 0, 0 }, 125 { 864000000, 18, 1, 0, 0 }, 126 { 720000000, 30, 0, 0, 0 }, 127 { 624000000, 26, 0, 0, 0 }, 128 { 528000000, 22, 0, 0, 0 }, 129 { 312000000, 13, 0, 0, 0 }, 130 { 144000000, 12, 0, 0, 1 }, 131 { 0 } 132 }; 133 134 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = { 135 { 24576000, 86, 0, 21, 3 }, 136 { 0 } 137 }; 138 139 /* 140 * some special cases 141 * hardcode lcd0 (tcon0) to pll3 and lcd1 (tcon1) to pll7. 142 * compute pll rate based on desired pixel clock 143 */ 144 145 static int sun4i_a10_ccu_lcd0ch0_set_rate(struct sunxi_ccu_softc *, 146 struct sunxi_ccu_clk *, u_int); 147 static int sun4i_a10_ccu_lcd1ch0_set_rate(struct sunxi_ccu_softc *, 148 struct sunxi_ccu_clk *, u_int); 149 static u_int sun4i_a10_ccu_lcd0ch0_round_rate(struct sunxi_ccu_softc *, 150 struct sunxi_ccu_clk *, u_int); 151 static u_int sun4i_a10_ccu_lcd1ch0_round_rate(struct sunxi_ccu_softc *, 152 struct sunxi_ccu_clk *, u_int); 153 static int sun4i_a10_ccu_lcd0ch1_set_rate(struct sunxi_ccu_softc *, 154 struct sunxi_ccu_clk *, u_int); 155 static int sun4i_a10_ccu_lcd1ch1_set_rate(struct sunxi_ccu_softc *, 156 struct sunxi_ccu_clk *, u_int); 157 158 static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = { 159 SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc", 160 OSC24M_CFG_REG, 0), 161 162 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_CORE, "pll_core", "osc24m", 163 PLL1_CFG_REG, /* reg */ 164 __BITS(12,8), /* n */ 165 __BITS(5,4), /* k */ 166 __BITS(1,0), /* m */ 167 __BITS(17,16), /* p */ 168 __BIT(31), /* enable */ 169 0, /* lock */ 170 sun4i_a10_pll1_table, /* table */ 171 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT | 172 SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE | SUNXI_CCU_NKMP_SCALE_CLOCK), 173 174 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 175 PLL2_CFG_REG, /* reg */ 176 __BITS(14,8), /* n */ 177 0, /* k */ 178 __BITS(4,0), /* m */ 179 __BITS(29,26), /* p */ 180 __BIT(31), /* enable */ 181 0, /* lock */ 182 sun4i_a10_ac_dig_table, /* table */ 183 0), 184 185 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_BASE, "pll_periph_base", "osc24m", 186 PLL6_CFG_REG, /* reg */ 187 __BITS(12,8), /* n */ 188 __BITS(5,4), /* k */ 189 0, /* m */ 190 0, /* p */ 191 __BIT(31), /* enable */ 192 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 193 194 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_PERIPH, "pll_periph", "pll_periph_base", 195 2, 1), 196 197 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_SATA, "pll_periph_sata", "pll_periph_base", 198 PLL6_CFG_REG, /* reg */ 199 0, /* n */ 200 0, /* k */ 201 __BITS(1,0), /* m */ 202 0, /* p */ 203 __BIT(14), /* enable */ 204 0), 205 206 SUNXI_CCU_DIV_GATE(A10_CLK_SATA, "sata", sata_parents, 207 SATA_CFG_REG, /* reg */ 208 0, /* div */ 209 __BIT(24), /* sel */ 210 __BIT(31), /* enable */ 211 0), 212 213 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR_BASE, "pll_ddr_other", "osc24m", 214 PLL5_CFG_REG, /* reg */ 215 __BITS(12, 8), /* n */ 216 __BITS(5,4), /* k */ 217 0, /* m */ 218 __BITS(17,16), /* p */ 219 __BIT(31), /* enable */ 220 SUNXI_CCU_NKMP_FACTOR_N_EXACT | SUNXI_CCU_NKMP_FACTOR_P_POW2), 221 222 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR, "pll_ddr", "osc24m", 223 PLL5_CFG_REG, /* reg */ 224 __BITS(12, 8), /* n */ 225 __BITS(5,4), /* k */ 226 __BITS(1,0), /* m */ 227 0, /* p */ 228 __BIT(31), /* enable */ 229 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 230 231 SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents, 232 CPU_AHB_APB0_CFG_REG, /* reg */ 233 0, /* div */ 234 __BITS(17,16), /* sel */ 235 SUNXI_CCU_DIV_SET_RATE_PARENT), 236 237 SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents, 238 CPU_AHB_APB0_CFG_REG, /* reg */ 239 __BITS(1,0), /* div */ 240 0, /* sel */ 241 0), 242 243 SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents, 244 CPU_AHB_APB0_CFG_REG, /* reg */ 245 __BITS(5,4), /* div */ 246 __BITS(7,6), /* sel */ 247 SUNXI_CCU_DIV_POWER_OF_TWO), 248 249 SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents, 250 CPU_AHB_APB0_CFG_REG, /* reg */ 251 __BITS(9,8), /* div */ 252 0, /* sel */ 253 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 254 255 SUNXI_CCU_NM(A10_CLK_APB1, "apb1", apb1_parents, 256 APB1_CLK_DIV_REG, /* reg */ 257 __BITS(17,16), /* n */ 258 __BITS(4,0), /* m */ 259 __BITS(25,24), /* sel */ 260 0, /* enable */ 261 SUNXI_CCU_NM_POWER_OF_TWO), 262 263 SUNXI_CCU_NM(A10_CLK_NAND, "nand", mod_parents, 264 NAND_SCLK_CFG_REG, /* reg */ 265 __BITS(17,16), /* n */ 266 __BITS(3,0), /* m */ 267 __BITS(25,24), /* sel */ 268 __BIT(31), /* enable */ 269 SUNXI_CCU_NM_POWER_OF_TWO), 270 271 SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents, 272 SD0_SCLK_CFG_REG, /* reg */ 273 __BITS(17,16), /* n */ 274 __BITS(3,0), /* m */ 275 __BITS(25,24), /* sel */ 276 __BIT(31), /* enable */ 277 SUNXI_CCU_NM_POWER_OF_TWO), 278 SUNXI_CCU_PHASE(A10_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 279 SD0_SCLK_CFG_REG, __BITS(22,20)), 280 SUNXI_CCU_PHASE(A10_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 281 SD0_SCLK_CFG_REG, __BITS(10,8)), 282 SUNXI_CCU_NM(A10_CLK_MMC1, "mmc1", mod_parents, 283 SD1_SCLK_CFG_REG, /* reg */ 284 __BITS(17,16), /* n */ 285 __BITS(3,0), /* m */ 286 __BITS(25,24), /* sel */ 287 __BIT(31), /* enable */ 288 SUNXI_CCU_NM_POWER_OF_TWO), 289 SUNXI_CCU_PHASE(A10_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 290 SD1_SCLK_CFG_REG, __BITS(22,20)), 291 SUNXI_CCU_PHASE(A10_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 292 SD1_SCLK_CFG_REG, __BITS(10,8)), 293 SUNXI_CCU_NM(A10_CLK_MMC2, "mmc2", mod_parents, 294 SD2_SCLK_CFG_REG, /* reg */ 295 __BITS(17,16), /* n */ 296 __BITS(3,0), /* m */ 297 __BITS(25,24), /* sel */ 298 __BIT(31), /* enable */ 299 SUNXI_CCU_NM_POWER_OF_TWO), 300 SUNXI_CCU_PHASE(A10_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 301 SD2_SCLK_CFG_REG, __BITS(22,20)), 302 SUNXI_CCU_PHASE(A10_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 303 SD2_SCLK_CFG_REG, __BITS(10,8)), 304 SUNXI_CCU_NM(A10_CLK_MMC3, "mmc3", mod_parents, 305 SD3_SCLK_CFG_REG, /* reg */ 306 __BITS(17,16), /* n */ 307 __BITS(3,0), /* m */ 308 __BITS(25,24), /* sel */ 309 __BIT(31), /* enable */ 310 SUNXI_CCU_NM_POWER_OF_TWO), 311 SUNXI_CCU_PHASE(A10_CLK_MMC3_SAMPLE, "mmc3_sample", "mmc3", 312 SD3_SCLK_CFG_REG, __BITS(22,20)), 313 SUNXI_CCU_PHASE(A10_CLK_MMC3_OUTPUT, "mmc3_output", "mmc3", 314 SD3_SCLK_CFG_REG, __BITS(10,8)), 315 316 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO0, "pll_video0", "osc24m", 317 PLL3_CFG_REG, /* reg */ 318 __BITS(7,0), /* m */ 319 9, /* m_min */ 320 127, /* m_max */ 321 __BIT(15), /* div_en */ 322 __BIT(14), /* frac_sel */ 323 270000000, 297000000, /* frac values */ 324 8, /* prediv */ 325 __BIT(31) /* enable */ 326 ), 327 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO1, "pll_video1", "osc24m", 328 PLL7_CFG_REG, /* reg */ 329 __BITS(7,0), /* m */ 330 9, /* m_min */ 331 127, /* m_max */ 332 __BIT(15), /* div_en */ 333 __BIT(14), /* frac_sel */ 334 270000000, 297000000, /* frac values */ 335 8, /* prediv */ 336 __BIT(31) /* enable */ 337 ), 338 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO0_2X, 339 "pll_video0x2", "pll_video0", 340 1, 2), 341 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO1_2X, 342 "pll_video1x2", "pll_video1", 343 1, 2), 344 345 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE0, "debe0-mod", de_parents, 346 BE0_CFG_REG, /* reg */ 347 __BITS(3,0), /* div */ 348 __BITS(25,24), /* sel */ 349 __BIT(31), /* enable */ 350 0 /* flags */ 351 ), 352 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE1, "debe1-mod", de_parents, 353 BE1_CFG_REG, /* reg */ 354 __BITS(3,0), /* div */ 355 __BITS(25,24), /* sel */ 356 __BIT(31), /* enable */ 357 0 /* flags */ 358 ), 359 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE0, "defe0-mod", de_parents, 360 FE0_CFG_REG, /* reg */ 361 __BITS(3,0), /* div */ 362 __BITS(25,24), /* sel */ 363 __BIT(31), /* enable */ 364 0 /* flags */ 365 ), 366 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE1, "defe1-mod", de_parents, 367 FE1_CFG_REG, /* reg */ 368 __BITS(3,0), /* div */ 369 __BITS(25,24), /* sel */ 370 __BIT(31), /* enable */ 371 0 /* flags */ 372 ), 373 [A10_CLK_TCON0_CH0] = { 374 .type = SUNXI_CCU_DIV, 375 .base.name = "tcon0-ch0", 376 .u.div.reg = LCD0CH0_CFG_REG, 377 .u.div.parents = lcd_parents, 378 .u.div.nparents = __arraycount(lcd_parents), 379 .u.div.div = 0, 380 .u.div.sel = __BITS(25,24), 381 .u.div.enable = __BIT(31), 382 .u.div.flags = 0, 383 .enable = sunxi_ccu_div_enable, 384 .get_rate = sunxi_ccu_div_get_rate, 385 .set_rate = sun4i_a10_ccu_lcd0ch0_set_rate, 386 .round_rate = sun4i_a10_ccu_lcd0ch0_round_rate, 387 .set_parent = sunxi_ccu_div_set_parent, 388 .get_parent = sunxi_ccu_div_get_parent, 389 }, 390 [A10_CLK_TCON1_CH0] = { 391 .type = SUNXI_CCU_DIV, 392 .base.name = "tcon1-ch0", 393 .u.div.reg = LCD1CH0_CFG_REG, 394 .u.div.parents = lcd_parents, 395 .u.div.nparents = __arraycount(lcd_parents), 396 .u.div.div = 0, 397 .u.div.sel = __BITS(25,24), 398 .u.div.enable = __BIT(31), 399 .u.div.flags = 0, 400 .enable = sunxi_ccu_div_enable, 401 .get_rate = sunxi_ccu_div_get_rate, 402 .set_rate = sun4i_a10_ccu_lcd1ch0_set_rate, 403 .round_rate = sun4i_a10_ccu_lcd1ch0_round_rate, 404 .set_parent = sunxi_ccu_div_set_parent, 405 .get_parent = sunxi_ccu_div_get_parent, 406 }, 407 [A10_CLK_TCON0_CH1] = { 408 .type = SUNXI_CCU_DIV, 409 .base.name = "tcon0-ch1", 410 .u.div.reg = LCD0CH1_CFG_REG, 411 .u.div.parents = lcd_parents, 412 .u.div.nparents = __arraycount(lcd_parents), 413 .u.div.div = __BITS(3,0), 414 .u.div.sel = __BITS(25,24), 415 .u.div.enable = __BIT(15) | __BIT(31), 416 .u.div.flags = 0, 417 .enable = sunxi_ccu_div_enable, 418 .get_rate = sunxi_ccu_div_get_rate, 419 .set_rate = sun4i_a10_ccu_lcd0ch1_set_rate, 420 .set_parent = sunxi_ccu_div_set_parent, 421 .get_parent = sunxi_ccu_div_get_parent, 422 }, 423 [A10_CLK_TCON1_CH1] = { 424 .type = SUNXI_CCU_DIV, 425 .base.name = "tcon1-ch1", 426 .u.div.reg = LCD1CH1_CFG_REG, 427 .u.div.parents = lcd_parents, 428 .u.div.nparents = __arraycount(lcd_parents), 429 .u.div.div = __BITS(3,0), 430 .u.div.sel = __BITS(25,24), 431 .u.div.enable = __BIT(15) | __BIT(31), 432 .u.div.flags = 0, 433 .enable = sunxi_ccu_div_enable, 434 .get_rate = sunxi_ccu_div_get_rate, 435 .set_rate = sun4i_a10_ccu_lcd1ch1_set_rate, 436 .set_parent = sunxi_ccu_div_set_parent, 437 .get_parent = sunxi_ccu_div_get_parent, 438 }, 439 SUNXI_CCU_DIV_GATE(A10_CLK_HDMI, "hdmi-mod", lcd_parents, 440 HDMI_CLOCK_CFG_REG, /* reg */ 441 __BITS(3,0), /* div */ 442 __BITS(25,24), /* sel */ 443 __BIT(31), /* enable */ 444 0 /* flags */ 445 ), 446 447 /* AHB_GATING_REG0 */ 448 SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb", 449 AHB_GATING_REG0, 0), 450 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 451 AHB_GATING_REG0, 1), 452 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 453 AHB_GATING_REG0, 2), 454 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 455 AHB_GATING_REG0, 3), 456 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 457 AHB_GATING_REG0, 4), 458 SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb", 459 AHB_GATING_REG0, 5), 460 SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb", 461 AHB_GATING_REG0, 6), 462 SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb", 463 AHB_GATING_REG0, 7), 464 SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 465 AHB_GATING_REG0, 8), 466 SUNXI_CCU_GATE(A10_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 467 AHB_GATING_REG0, 9), 468 SUNXI_CCU_GATE(A10_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 469 AHB_GATING_REG0, 10), 470 SUNXI_CCU_GATE(A10_CLK_AHB_MMC3, "ahb-mmc3", "ahb", 471 AHB_GATING_REG0, 11), 472 SUNXI_CCU_GATE(A10_CLK_AHB_MS, "ahb-ms", "ahb", 473 AHB_GATING_REG0, 12), 474 SUNXI_CCU_GATE(A10_CLK_AHB_NAND, "ahb-nand", "ahb", 475 AHB_GATING_REG0, 13), 476 SUNXI_CCU_GATE(A10_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 477 AHB_GATING_REG0, 14), 478 SUNXI_CCU_GATE(A10_CLK_AHB_ACE, "ahb-ace", "ahb", 479 AHB_GATING_REG0, 16), 480 SUNXI_CCU_GATE(A10_CLK_AHB_EMAC, "ahb-emac", "ahb", 481 AHB_GATING_REG0, 17), 482 SUNXI_CCU_GATE(A10_CLK_AHB_TS, "ahb-ts", "ahb", 483 AHB_GATING_REG0, 18), 484 SUNXI_CCU_GATE(A10_CLK_AHB_SPI0, "ahb-spi0", "ahb", 485 AHB_GATING_REG0, 20), 486 SUNXI_CCU_GATE(A10_CLK_AHB_SPI1, "ahb-spi1", "ahb", 487 AHB_GATING_REG0, 21), 488 SUNXI_CCU_GATE(A10_CLK_AHB_SPI2, "ahb-spi2", "ahb", 489 AHB_GATING_REG0, 22), 490 SUNXI_CCU_GATE(A10_CLK_AHB_SPI3, "ahb-spi3", "ahb", 491 AHB_GATING_REG0, 23), 492 SUNXI_CCU_GATE(A10_CLK_AHB_SATA, "ahb-sata", "ahb", 493 AHB_GATING_REG0, 25), 494 SUNXI_CCU_GATE(A10_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 495 AHB_GATING_REG0, 28), 496 497 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 498 SUNXI_CCU_GATE(A10_CLK_AHB_VE, "ahb-ve", "ahb", 499 AHB_GATING_REG1, 0), 500 SUNXI_CCU_GATE(A10_CLK_AHB_TVD, "ahb-tvd", "ahb", 501 AHB_GATING_REG1, 1), 502 SUNXI_CCU_GATE(A10_CLK_AHB_TVE0, "ahb-tve0", "ahb", 503 AHB_GATING_REG1, 2), 504 SUNXI_CCU_GATE(A10_CLK_AHB_TVE1, "ahb-tve1", "ahb", 505 AHB_GATING_REG1, 3), 506 SUNXI_CCU_GATE(A10_CLK_AHB_LCD0, "ahb-lcd0", "ahb", 507 AHB_GATING_REG1, 4), 508 SUNXI_CCU_GATE(A10_CLK_AHB_LCD1, "ahb-lcd1", "ahb", 509 AHB_GATING_REG1, 5), 510 SUNXI_CCU_GATE(A10_CLK_AHB_CSI0, "ahb-csi0", "ahb", 511 AHB_GATING_REG1, 8), 512 SUNXI_CCU_GATE(A10_CLK_AHB_CSI1, "ahb-csi1", "ahb", 513 AHB_GATING_REG1, 9), 514 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 515 AHB_GATING_REG1, 10), 516 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 517 AHB_GATING_REG1, 11), 518 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 519 AHB_GATING_REG1, 12), 520 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 521 AHB_GATING_REG1, 13), 522 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 523 AHB_GATING_REG1, 14), 524 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 525 AHB_GATING_REG1, 15), 526 SUNXI_CCU_GATE(A10_CLK_AHB_GMAC, "ahb-gmac", "ahb", 527 AHB_GATING_REG1, 17), 528 SUNXI_CCU_GATE(A10_CLK_AHB_MP, "ahb-mp", "ahb", 529 AHB_GATING_REG1, 18), 530 SUNXI_CCU_GATE(A10_CLK_AHB_GPU, "ahb-gpu", "ahb", 531 AHB_GATING_REG1, 20), 532 533 /* APB0_GATING_REG */ 534 SUNXI_CCU_GATE(A10_CLK_APB0_CODEC, "apb0-codec", "apb0", 535 APB0_GATING_REG, 0), 536 SUNXI_CCU_GATE(A10_CLK_APB0_SPDIF, "apb0-spdif", "apb0", 537 APB0_GATING_REG, 1), 538 SUNXI_CCU_GATE(A10_CLK_APB0_AC97, "apb0-ac97", "apb0", 539 APB0_GATING_REG, 2), 540 SUNXI_CCU_GATE(A10_CLK_APB0_I2S0, "apb0-i2s0", "apb0", 541 APB0_GATING_REG, 3), 542 SUNXI_CCU_GATE(A10_CLK_APB0_I2S1, "apb0-i2s1", "apb0", 543 APB0_GATING_REG, 4), 544 SUNXI_CCU_GATE(A10_CLK_APB0_PIO, "apb0-pio", "apb0", 545 APB0_GATING_REG, 5), 546 SUNXI_CCU_GATE(A10_CLK_APB0_IR0, "apb0-ir0", "apb0", 547 APB0_GATING_REG, 6), 548 SUNXI_CCU_GATE(A10_CLK_APB0_IR1, "apb0-ir1", "apb0", 549 APB0_GATING_REG, 7), 550 SUNXI_CCU_GATE(A10_CLK_APB0_I2S2, "apb0-i2s2", "apb0", 551 APB0_GATING_REG, 8), 552 SUNXI_CCU_GATE(A10_CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 553 APB0_GATING_REG, 10), 554 555 /* APB1_GATING_REG */ 556 SUNXI_CCU_GATE(A10_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 557 APB1_GATING_REG, 0), 558 SUNXI_CCU_GATE(A10_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 559 APB1_GATING_REG, 1), 560 SUNXI_CCU_GATE(A10_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 561 APB1_GATING_REG, 2), 562 SUNXI_CCU_GATE(A10_CLK_APB1_I2C3, "apb1-i2c3", "apb1", 563 APB1_GATING_REG, 3), 564 SUNXI_CCU_GATE(A10_CLK_APB1_CAN, "apb1-can", "apb1", 565 APB1_GATING_REG, 4), 566 SUNXI_CCU_GATE(A10_CLK_APB1_SCR, "apb1-scr", "apb1", 567 APB1_GATING_REG, 5), 568 SUNXI_CCU_GATE(A10_CLK_APB1_PS20, "apb1-ps20", "apb1", 569 APB1_GATING_REG, 6), 570 SUNXI_CCU_GATE(A10_CLK_APB1_PS21, "apb1-ps21", "apb1", 571 APB1_GATING_REG, 7), 572 SUNXI_CCU_GATE(A10_CLK_APB1_I2C4, "apb1-i2c4", "apb1", 573 APB1_GATING_REG, 15), 574 SUNXI_CCU_GATE(A10_CLK_APB1_UART0, "apb1-uart0", "apb1", 575 APB1_GATING_REG, 16), 576 SUNXI_CCU_GATE(A10_CLK_APB1_UART1, "apb1-uart1", "apb1", 577 APB1_GATING_REG, 17), 578 SUNXI_CCU_GATE(A10_CLK_APB1_UART2, "apb1-uart2", "apb1", 579 APB1_GATING_REG, 18), 580 SUNXI_CCU_GATE(A10_CLK_APB1_UART3, "apb1-uart3", "apb1", 581 APB1_GATING_REG, 19), 582 SUNXI_CCU_GATE(A10_CLK_APB1_UART4, "apb1-uart4", "apb1", 583 APB1_GATING_REG, 20), 584 SUNXI_CCU_GATE(A10_CLK_APB1_UART5, "apb1-uart5", "apb1", 585 APB1_GATING_REG, 21), 586 SUNXI_CCU_GATE(A10_CLK_APB1_UART6, "apb1-uart6", "apb1", 587 APB1_GATING_REG, 22), 588 SUNXI_CCU_GATE(A10_CLK_APB1_UART7, "apb1-uart7", "apb1", 589 APB1_GATING_REG, 23), 590 591 /* DRAM GATING */ 592 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE0, "dram-de-be0", "pll_ddr_other", 593 DRAM_GATING_REG, 26), 594 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE1, "dram-de-be1", "pll_ddr_other", 595 DRAM_GATING_REG, 27), 596 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE0, "dram-de-fe0", "pll_ddr_other", 597 DRAM_GATING_REG, 25), 598 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE1, "dram-de-fe1", "pll_ddr_other", 599 DRAM_GATING_REG, 24), 600 601 /* AUDIO_CODEC_SCLK_CFG_REG */ 602 SUNXI_CCU_GATE(A10_CLK_CODEC, "codec", "pll_audio", 603 AUDIO_CODEC_SCLK_CFG_REG, 31), 604 605 /* USBPHY_CFG_REG */ 606 SUNXI_CCU_GATE(A10_CLK_USB_OHCI0, "usb-ohci0", "osc24m", 607 USBPHY_CFG_REG, 6), 608 SUNXI_CCU_GATE(A10_CLK_USB_OHCI1, "usb-ohci1", "osc24m", 609 USBPHY_CFG_REG, 7), 610 SUNXI_CCU_GATE(A10_CLK_USB_PHY, "usb-phy", "osc24m", 611 USBPHY_CFG_REG, 8), 612 }; 613 614 /* 615 * some special cases 616 * hardcode lcd0 (tcon0) to pll3 and lcd1 (tcon1) to pll7. 617 * compute pll rate based on desired pixel clock 618 */ 619 620 static int 621 sun4i_a10_ccu_lcd0ch0_set_rate(struct sunxi_ccu_softc *sc, 622 struct sunxi_ccu_clk * clk, u_int rate) 623 { 624 int error; 625 error = sunxi_ccu_lcdxch0_set_rate(sc, clk, 626 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 627 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 628 rate); 629 return error; 630 } 631 632 static int 633 sun4i_a10_ccu_lcd1ch0_set_rate(struct sunxi_ccu_softc *sc, 634 struct sunxi_ccu_clk * clk, u_int rate) 635 { 636 return sunxi_ccu_lcdxch0_set_rate(sc, clk, 637 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 638 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 639 rate); 640 } 641 642 static u_int 643 sun4i_a10_ccu_lcd0ch0_round_rate(struct sunxi_ccu_softc *sc, 644 struct sunxi_ccu_clk * clk, u_int rate) 645 { 646 return sunxi_ccu_lcdxch0_round_rate(sc, clk, 647 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 648 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 649 rate); 650 } 651 652 static u_int 653 sun4i_a10_ccu_lcd1ch0_round_rate(struct sunxi_ccu_softc *sc, 654 struct sunxi_ccu_clk * clk, u_int rate) 655 { 656 return sunxi_ccu_lcdxch0_round_rate(sc, clk, 657 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 658 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 659 rate); 660 } 661 662 static int 663 sun4i_a10_ccu_lcd0ch1_set_rate(struct sunxi_ccu_softc *sc, 664 struct sunxi_ccu_clk * clk, u_int rate) 665 { 666 return sunxi_ccu_lcdxch1_set_rate(sc, clk, 667 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 668 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 669 rate); 670 } 671 672 static int 673 sun4i_a10_ccu_lcd1ch1_set_rate(struct sunxi_ccu_softc *sc, 674 struct sunxi_ccu_clk * clk, u_int rate) 675 { 676 return sunxi_ccu_lcdxch1_set_rate(sc, clk, 677 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 678 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 679 rate); 680 } 681 682 #if 0 683 static int 684 sun4i_a10_ccu_lcdxch0_set_rate(struct sunxi_ccu_softc *sc, 685 struct sunxi_ccu_clk * clk, u_int rate, int unit) 686 { 687 int parent_index; 688 struct clk *clkp; 689 int error; 690 691 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 692 clkp = &sun4i_a10_ccu_clks[parent_index].base; 693 error = clk_set_rate(clkp, rate); 694 if (error) { 695 error = clk_set_rate(clkp, rate / 2); 696 if (error != 0) 697 return error; 698 parent_index = 699 (unit == 0) ? A10_CLK_PLL_VIDEO0_2X : A10_CLK_PLL_VIDEO1_2X; 700 clkp = &sun4i_a10_ccu_clks[parent_index].base; 701 } 702 error = clk_set_parent(&clk->base, clkp); 703 KASSERT(error == 0); 704 return error; 705 } 706 707 static u_int 708 sun4i_a10_ccu_lcdxch0_round_rate(struct sunxi_ccu_softc *sc, 709 struct sunxi_ccu_clk * clk, u_int try_rate, int unit) 710 { 711 int parent_index; 712 struct clk *clkp; 713 int diff, diff_x2; 714 int rate, rate_x2; 715 716 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 717 clkp = &sun4i_a10_ccu_clks[parent_index].base; 718 rate = clk_round_rate(clkp, try_rate); 719 diff = abs(try_rate - rate); 720 721 rate_x2 = (clk_round_rate(clkp, try_rate / 2) * 2); 722 diff_x2 = abs(try_rate - rate_x2); 723 724 if (diff_x2 < diff) 725 return rate_x2; 726 return rate; 727 } 728 729 static void 730 sun4i_a10_tcon_calc_pll(int f_ref, int f_out, int *pm, int *pn, int *pd) 731 { 732 int best = INT_MAX; 733 for (int d = 1; d <= 2 && best != 0; d++) { 734 for (int m = 1; m <= 16 && best != 0; m++) { 735 for (int n = 9; n <= 127 && best != 0; n++) { 736 int f_cur = (n * f_ref * d) / m; 737 int diff = abs(f_out - f_cur); 738 if (diff < best) { 739 best = diff; 740 *pm = m; 741 *pn = n; 742 *pd = d; 743 if (diff == 0) 744 return; 745 } 746 } 747 } 748 } 749 } 750 751 static int 752 sun4i_a10_ccu_lcdxch1_set_rate(struct sunxi_ccu_softc *sc, 753 struct sunxi_ccu_clk *clk, u_int rate, int unit) 754 { 755 int parent_index; 756 struct clk *clkp, *pllclk; 757 int error; 758 int n = 0, m = 0, d = 0; 759 760 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 761 clkp = &sun4i_a10_ccu_clks[parent_index].base; 762 pllclk = clkp; 763 764 sun4i_a10_tcon_calc_pll(3000000, rate, &m, &n, &d); 765 766 if (n == 0 || m == 0 || d == 0) 767 return ERANGE; 768 769 if (d == 2) { 770 parent_index = 771 (unit == 0) ? A10_CLK_PLL_VIDEO0_2X : A10_CLK_PLL_VIDEO1_2X; 772 clkp = &sun4i_a10_ccu_clks[parent_index].base; 773 } 774 775 error = clk_set_rate(pllclk, 3000000 * n); 776 KASSERT(error == 0); 777 error = clk_set_parent(&clk->base, clkp); 778 KASSERT(error == 0); 779 error = sunxi_ccu_div_set_rate(sc, clk, rate); 780 KASSERT(error == 0); 781 return error; 782 } 783 #endif 784 785 static int 786 sun4i_a10_ccu_match(device_t parent, cfdata_t cf, void *aux) 787 { 788 struct fdt_attach_args * const faa = aux; 789 790 return of_match_compat_data(faa->faa_phandle, compat_data); 791 } 792 793 static struct sunxi_ccu_softc *sc0; 794 static void 795 sun4i_a10_ccu_attach(device_t parent, device_t self, void *aux) 796 { 797 struct sunxi_ccu_softc * const sc = device_private(self); 798 struct fdt_attach_args * const faa = aux; 799 enum sun4i_a10_ccu_type type; 800 struct clk *clk, *clkp; 801 int error; 802 803 sc->sc_dev = self; 804 sc->sc_phandle = faa->faa_phandle; 805 sc->sc_bst = faa->faa_bst; 806 807 sc->sc_resets = sun4i_a10_ccu_resets; 808 sc->sc_nresets = __arraycount(sun4i_a10_ccu_resets); 809 810 sc->sc_clks = sun4i_a10_ccu_clks; 811 sc->sc_nclks = __arraycount(sun4i_a10_ccu_clks); 812 813 if (sunxi_ccu_attach(sc) != 0) 814 return; 815 816 aprint_naive("\n"); 817 818 type = of_search_compatible(faa->faa_phandle, compat_data)->data; 819 820 switch (type) { 821 case CCU_A10: 822 aprint_normal(": A10 CCU\n"); 823 break; 824 case CCU_A20: 825 aprint_normal(": A20 CCU\n"); 826 break; 827 } 828 /* hardcode debe clocks parent to PLL5 */ 829 clkp = &sun4i_a10_ccu_clks[A10_CLK_PLL_DDR_BASE].base; 830 clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE0].base; 831 error = clk_set_parent(clk, clkp); 832 KASSERT(error == 0); 833 clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE1].base; 834 error = clk_set_parent(clk, clkp); 835 KASSERT(error == 0); 836 837 (void)error; 838 sunxi_ccu_print(sc); 839 sc0 = sc; 840 } 841 842 void sun4i_ccu_print(void); 843 void 844 sun4i_ccu_print(void) 845 { 846 sunxi_ccu_print(sc0); 847 } 848
Indexes created Thu Oct 02 01:09:59 GMT 2025