sun4i_spi.c revision 1.11
1 /* $NetBSD: sun4i_spi.c,v 1.11 2025/09/10 04:17:19 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Tobias Nygren 5 * Copyright (c) 2018 Jonathan A. Kollasch 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 27 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: sun4i_spi.c,v 1.11 2025/09/10 04:17:19 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/device.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 #include <sys/bitops.h> 40 #include <dev/spi/spivar.h> 41 #include <arm/sunxi/sun4i_spireg.h> 42 #include <dev/fdt/fdtvar.h> 43 44 static const struct device_compatible_entry compat_data[] = { 45 { .compat = "allwinner,sun4i-a10-spi" }, 46 DEVICE_COMPAT_EOL 47 }; 48 49 struct sun4ispi_softc { 50 device_t sc_dev; 51 bus_space_tag_t sc_bst; 52 bus_space_handle_t sc_bsh; 53 void *sc_intrh; 54 struct spi_controller sc_spi; 55 SIMPLEQ_HEAD(,spi_transfer) sc_q; 56 struct spi_transfer *sc_transfer; 57 struct spi_chunk *sc_rchunk, *sc_wchunk; 58 uint32_t sc_CTL; 59 u_int sc_modclkrate; 60 volatile bool sc_running; 61 }; 62 63 #define SPIREG_READ(sc, reg) \ 64 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 65 #define SPIREG_WRITE(sc, reg, val) \ 66 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 67 68 static int sun4ispi_match(device_t, cfdata_t, void *); 69 static void sun4ispi_attach(device_t, device_t, void *); 70 71 static int sun4ispi_configure(void *, int, int, int); 72 static int sun4ispi_transfer(void *, struct spi_transfer *); 73 74 static void sun4ispi_txfifo_fill(struct sun4ispi_softc * const, size_t); 75 static void sun4ispi_rxfifo_drain(struct sun4ispi_softc * const, size_t); 76 static void sun4ispi_rxtx(struct sun4ispi_softc * const); 77 static void sun4ispi_set_interrupt_mask(struct sun4ispi_softc * const); 78 static void sun4ispi_start(struct sun4ispi_softc * const); 79 static int sun4ispi_intr(void *); 80 81 CFATTACH_DECL_NEW(sun4i_spi, sizeof(struct sun4ispi_softc), 82 sun4ispi_match, sun4ispi_attach, NULL, NULL); 83 84 static int 85 sun4ispi_match(device_t parent, cfdata_t cf, void *aux) 86 { 87 struct fdt_attach_args * const faa = aux; 88 89 return of_compatible_match(faa->faa_phandle, compat_data); 90 } 91 92 static void 93 sun4ispi_attach(device_t parent, device_t self, void *aux) 94 { 95 struct sun4ispi_softc * const sc = device_private(self); 96 struct fdt_attach_args * const faa = aux; 97 const int phandle = faa->faa_phandle; 98 bus_addr_t addr; 99 bus_size_t size; 100 struct clk *clk, *modclk; 101 char intrstr[128]; 102 103 sc->sc_dev = self; 104 sc->sc_bst = faa->faa_bst; 105 SIMPLEQ_INIT(&sc->sc_q); 106 107 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL 108 || clk_enable(clk) != 0) { 109 aprint_error(": couldn't enable clock\n"); 110 return; 111 } 112 113 if ((modclk = fdtbus_clock_get(phandle, "mod")) == NULL 114 || clk_set_rate(modclk, clk_get_rate(clk)) != 0 115 || clk_enable(modclk) != 0) { 116 aprint_error(": couldn't enable module clock\n"); 117 return; 118 } 119 sc->sc_modclkrate = clk_get_rate(modclk); 120 121 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 122 || bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 123 aprint_error(": couldn't map registers\n"); 124 return; 125 } 126 127 SPIREG_WRITE(sc, SPI_CTL, SPI_CTL_SSPOL | SPI_CTL_RF_RST 128 | SPI_CTL_TF_RST | SPI_CTL_MODE); 129 SPIREG_WRITE(sc, SPI_DMACTL, 0); 130 SPIREG_WRITE(sc, SPI_WAIT, 0); 131 SPIREG_WRITE(sc, SPI_INTCTL, 0); 132 SPIREG_WRITE(sc, SPI_INT_STA, ~0); 133 134 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 135 aprint_error(": failed to decode interrupt\n"); 136 return; 137 } 138 139 sc->sc_intrh = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 0, 140 sun4ispi_intr, sc, device_xname(self)); 141 if (sc->sc_intrh == NULL) { 142 aprint_error(": unable to establish interrupt\n"); 143 return; 144 } 145 146 aprint_naive("\n"); 147 aprint_normal(": SPI\n"); 148 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 149 150 sc->sc_spi.sct_cookie = sc; 151 sc->sc_spi.sct_configure = sun4ispi_configure; 152 sc->sc_spi.sct_transfer = sun4ispi_transfer; 153 (void) of_getprop_uint32(phandle, "num-cs", &sc->sc_spi.sct_nslaves); 154 155 spibus_attach(self, &sc->sc_spi); 156 } 157 158 static int 159 sun4ispi_configure(void *cookie, int slave, int mode, int speed) 160 { 161 struct sun4ispi_softc * const sc = cookie; 162 uint32_t ctl, cctl; 163 uint32_t minfreq, maxfreq; 164 165 minfreq = sc->sc_modclkrate >> 16; 166 maxfreq = sc->sc_modclkrate >> 1; 167 168 if (speed <= 0 || speed < minfreq || speed > maxfreq) 169 return EINVAL; 170 171 if (slave >= sc->sc_spi.sct_nslaves) 172 return EINVAL; 173 174 ctl = SPI_CTL_SDM | SPI_CTL_TP_EN | SPI_CTL_SSPOL | SPI_CTL_MODE | SPI_CTL_EN; 175 176 switch (mode) { 177 case SPI_MODE_0: 178 ctl |= 0; 179 break; 180 case SPI_MODE_1: 181 ctl |= SPI_CTL_PHA; 182 break; 183 case SPI_MODE_2: 184 ctl |= SPI_CTL_POL; 185 break; 186 case SPI_MODE_3: 187 ctl |= SPI_CTL_PHA | SPI_CTL_POL; 188 break; 189 default: 190 return EINVAL; 191 } 192 193 if (speed < sc->sc_modclkrate / 512) { 194 for (cctl = 0; cctl <= __SHIFTOUT_MASK(SPI_CCTL_CDR1); cctl++) { 195 if ((sc->sc_modclkrate / (1 << cctl)) <= speed) 196 goto cdr1_found; 197 } 198 return EINVAL; 199 cdr1_found: 200 cctl = __SHIFTIN(cctl, SPI_CCTL_CDR1); 201 } else { 202 cctl = howmany(sc->sc_modclkrate, 2 * speed) - 1; 203 cctl = SPI_CCTL_DRS|__SHIFTIN(cctl, SPI_CCTL_CDR2); 204 } 205 206 device_printf(sc->sc_dev, "ctl 0x%x, cctl 0x%x, CLK %uHz, SCLK %uHz\n", 207 ctl, cctl, sc->sc_modclkrate, 208 (cctl & SPI_CCTL_DRS) 209 ? (sc->sc_modclkrate / (u_int)(2 * (__SHIFTOUT(cctl, SPI_CCTL_CDR2) + 1))) 210 : (sc->sc_modclkrate >> (__SHIFTOUT(cctl, SPI_CCTL_CDR1) + 1)) 211 ); 212 213 sc->sc_CTL = ctl; 214 SPIREG_WRITE(sc, SPI_CTL, (ctl | SPI_CTL_RF_RST | SPI_CTL_TF_RST) & ~SPI_CTL_EN); 215 SPIREG_WRITE(sc, SPI_CCTL, cctl); 216 SPIREG_WRITE(sc, SPI_CTL, ctl); 217 218 return 0; 219 } 220 221 static int 222 sun4ispi_transfer(void *cookie, struct spi_transfer *st) 223 { 224 struct sun4ispi_softc * const sc = cookie; 225 int s; 226 227 s = splbio(); 228 spi_transq_enqueue(&sc->sc_q, st); 229 if (sc->sc_running == false) { 230 sun4ispi_start(sc); 231 } 232 splx(s); 233 234 return 0; 235 } 236 237 static void 238 sun4ispi_txfifo_fill(struct sun4ispi_softc * const sc, size_t maxlen) 239 { 240 struct spi_chunk *chunk = sc->sc_wchunk; 241 size_t len; 242 uint8_t b; 243 244 if (chunk == NULL) 245 return; 246 247 len = MIN(maxlen, chunk->chunk_wresid); 248 chunk->chunk_wresid -= len; 249 while (len--) { 250 if (chunk->chunk_wptr) { 251 b = *chunk->chunk_wptr++; 252 } else { 253 b = 0; 254 } 255 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SPI_TXDATA, b); 256 } 257 if (sc->sc_wchunk->chunk_wresid == 0) { 258 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 259 } 260 } 261 262 static void 263 sun4ispi_rxfifo_drain(struct sun4ispi_softc * const sc, size_t maxlen) 264 { 265 struct spi_chunk *chunk = sc->sc_rchunk; 266 size_t len; 267 uint8_t b; 268 269 if (chunk == NULL) 270 return; 271 272 len = MIN(maxlen, chunk->chunk_rresid); 273 chunk->chunk_rresid -= len; 274 275 while (len--) { 276 b = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SPI_RXDATA); 277 if (chunk->chunk_rptr) { 278 *chunk->chunk_rptr++ = b; 279 } 280 } 281 if (sc->sc_rchunk->chunk_rresid == 0) { 282 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 283 } 284 } 285 286 static void 287 sun4ispi_rxtx(struct sun4ispi_softc * const sc) 288 { 289 bool again; 290 size_t rxavail, txavail; 291 uint32_t fsr; 292 293 /* service both FIFOs until no more progress can be made */ 294 again = true; 295 while (again) { 296 again = false; 297 fsr = SPIREG_READ(sc, SPI_FIFO_STA); 298 rxavail = __SHIFTOUT(fsr, SPI_FIFO_STA_RF_CNT); 299 txavail = 64 - __SHIFTOUT(fsr, SPI_FIFO_STA_TF_CNT); 300 if (rxavail > 0) { 301 KASSERT(sc->sc_rchunk != NULL); 302 sun4ispi_rxfifo_drain(sc, rxavail); 303 again = true; 304 } 305 if (txavail > 0 && sc->sc_wchunk != NULL) { 306 sun4ispi_txfifo_fill(sc, txavail); 307 again = true; 308 } 309 } 310 } 311 312 static void 313 sun4ispi_set_interrupt_mask(struct sun4ispi_softc * const sc) 314 { 315 uint32_t intctl; 316 317 intctl = SPI_INTCTL_TX_INT_EN; 318 intctl |= SPI_INTCTL_RF_OF_INT_EN; 319 intctl |= SPI_INTCTL_TF_UR_INT_EN; 320 321 if (sc->sc_rchunk) { 322 if (sc->sc_rchunk->chunk_rresid >= 32) { 323 intctl |= SPI_INTCTL_RF_HALF_FU_INT_EN; 324 } else { 325 intctl |= SPI_INTCTL_RF_RDY_INT_EN; 326 } 327 } 328 if (sc->sc_wchunk) { 329 intctl |= SPI_INTCTL_TF_HALF_EMP_INT_EN; 330 } 331 SPIREG_WRITE(sc, SPI_INTCTL, intctl); 332 } 333 334 static void 335 sun4ispi_start(struct sun4ispi_softc * const sc) 336 { 337 struct spi_transfer *st; 338 uint32_t ctl; 339 struct spi_chunk *chunk; 340 size_t burstcount; 341 342 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 343 344 spi_transq_dequeue(&sc->sc_q); 345 346 KASSERT(sc->sc_transfer == NULL); 347 sc->sc_transfer = st; 348 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 349 sc->sc_running = true; 350 351 burstcount = 0; 352 for (chunk = st->st_chunks; chunk; chunk = chunk->chunk_next) { 353 burstcount += chunk->chunk_count; 354 } 355 KASSERT(burstcount <= SPI_BC_BC); 356 SPIREG_WRITE(sc, SPI_BC, __SHIFTIN(burstcount, SPI_BC_BC)); 357 SPIREG_WRITE(sc, SPI_TC, __SHIFTIN(burstcount, SPI_TC_WTC)); 358 359 sun4ispi_rxtx(sc); 360 sun4ispi_set_interrupt_mask(sc); 361 362 KASSERT(st->st_slave < sc->sc_spi.sct_nslaves); 363 ctl = sc->sc_CTL | __SHIFTIN(st->st_slave, SPI_CTL_SS) | SPI_CTL_XCH; 364 SPIREG_WRITE(sc, SPI_CTL, ctl); 365 366 if (!cold) 367 return; 368 369 for (;;) { 370 (void) sun4ispi_intr(sc); 371 if (ISSET(st->st_flags, SPI_F_DONE)) 372 break; 373 } 374 } 375 sc->sc_running = false; 376 } 377 378 static int 379 sun4ispi_intr(void *cookie) 380 { 381 struct sun4ispi_softc * const sc = cookie; 382 struct spi_transfer *st; 383 uint32_t isr; 384 385 isr = SPIREG_READ(sc, SPI_INT_STA); 386 if (!isr) 387 return 0; 388 389 if (ISSET(isr, SPI_INT_STA_RO)) { 390 device_printf(sc->sc_dev, "RXFIFO overflow\n"); 391 } 392 if (ISSET(isr, SPI_INT_STA_TU)) { 393 device_printf(sc->sc_dev, "TXFIFO underrun\n"); 394 } 395 396 sun4ispi_rxtx(sc); 397 398 if (ISSET(isr, SPI_INT_STA_TC)) { 399 SPIREG_WRITE(sc, SPI_INTCTL, 0); 400 KASSERT(sc->sc_rchunk == NULL); 401 KASSERT(sc->sc_wchunk == NULL); 402 st = sc->sc_transfer; 403 sc->sc_transfer = NULL; 404 KASSERT(st != NULL); 405 spi_done(st, 0); 406 sc->sc_running = false; 407 } else { 408 sun4ispi_set_interrupt_mask(sc); 409 } 410 SPIREG_WRITE(sc, SPI_INT_STA, isr); 411 412 return 1; 413 } 414
Indexes created Mon Sep 22 10:09:38 GMT 2025