sun4i_spi.c revision 1.4
1 /* $NetBSD: sun4i_spi.c,v 1.4 2019/08/13 17:03:10 tnn Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Tobias Nygren 5 * Copyright (c) 2018 Jonathan A. Kollasch 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 27 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: sun4i_spi.c,v 1.4 2019/08/13 17:03:10 tnn Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/device.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 #include <sys/bitops.h> 40 #include <dev/spi/spivar.h> 41 #include <arm/sunxi/sun4i_spireg.h> 42 #include <dev/fdt/fdtvar.h> 43 44 static const char * const compatible[] = { 45 "allwinner,sun4i-a10-spi", 46 NULL 47 }; 48 49 struct sun4ispi_softc { 50 device_t sc_dev; 51 bus_space_tag_t sc_bst; 52 bus_space_handle_t sc_bsh; 53 void *sc_intrh; 54 struct spi_controller sc_spi; 55 SIMPLEQ_HEAD(,spi_transfer) sc_q; 56 struct spi_transfer *sc_transfer; 57 struct spi_chunk *sc_rchunk, *sc_wchunk; 58 uint32_t sc_CTL; 59 u_int sc_modclkrate; 60 volatile bool sc_running; 61 }; 62 63 #define SPIREG_READ(sc, reg) \ 64 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 65 #define SPIREG_WRITE(sc, reg, val) \ 66 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 67 68 static int sun4ispi_match(device_t, cfdata_t, void *); 69 static void sun4ispi_attach(device_t, device_t, void *); 70 71 static int sun4ispi_configure(void *, int, int, int); 72 static int sun4ispi_transfer(void *, struct spi_transfer *); 73 74 static void sun4ispi_txfifo_fill(struct sun4ispi_softc * const, size_t); 75 static void sun4ispi_rxfifo_drain(struct sun4ispi_softc * const, size_t); 76 static void sun4ispi_rxtx(struct sun4ispi_softc * const); 77 static void sun4ispi_set_interrupt_mask(struct sun4ispi_softc * const); 78 static void sun4ispi_start(struct sun4ispi_softc * const); 79 static int sun4ispi_intr(void *); 80 81 CFATTACH_DECL_NEW(sun4i_spi, sizeof(struct sun4ispi_softc), 82 sun4ispi_match, sun4ispi_attach, NULL, NULL); 83 84 static int 85 sun4ispi_match(device_t parent, cfdata_t cf, void *aux) 86 { 87 struct fdt_attach_args * const faa = aux; 88 89 return of_match_compatible(faa->faa_phandle, compatible); 90 } 91 92 static void 93 sun4ispi_attach(device_t parent, device_t self, void *aux) 94 { 95 struct sun4ispi_softc * const sc = device_private(self); 96 struct fdt_attach_args * const faa = aux; 97 const int phandle = faa->faa_phandle; 98 bus_addr_t addr; 99 bus_size_t size; 100 struct clk *clk, *modclk; 101 char intrstr[128]; 102 struct spibus_attach_args sba; 103 104 sc->sc_dev = self; 105 sc->sc_bst = faa->faa_bst; 106 SIMPLEQ_INIT(&sc->sc_q); 107 108 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL 109 || clk_enable(clk) != 0) { 110 aprint_error(": couldn't enable clock\n"); 111 return; 112 } 113 114 if ((modclk = fdtbus_clock_get(phandle, "mod")) == NULL 115 || clk_set_rate(modclk, clk_get_rate(clk)) != 0 116 || clk_enable(modclk) != 0) { 117 aprint_error(": couldn't enable module clock\n"); 118 return; 119 } 120 sc->sc_modclkrate = clk_get_rate(modclk); 121 122 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 123 || bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 124 aprint_error(": couldn't map registers\n"); 125 return; 126 } 127 128 SPIREG_WRITE(sc, SPI_CTL, SPI_CTL_SSPOL | SPI_CTL_RF_RST 129 | SPI_CTL_TF_RST | SPI_CTL_MODE); 130 SPIREG_WRITE(sc, SPI_DMACTL, 0); 131 SPIREG_WRITE(sc, SPI_WAIT, 0); 132 SPIREG_WRITE(sc, SPI_INTCTL, 0); 133 SPIREG_WRITE(sc, SPI_INT_STA, ~0); 134 135 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 136 aprint_error(": failed to decode interrupt\n"); 137 return; 138 } 139 140 sc->sc_intrh = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, sun4ispi_intr, sc); 141 if (sc->sc_intrh == NULL) { 142 aprint_error(": unable to establish interrupt\n"); 143 return; 144 } 145 146 aprint_naive("\n"); 147 aprint_normal(": SPI\n"); 148 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 149 150 sc->sc_spi.sct_cookie = sc; 151 sc->sc_spi.sct_configure = sun4ispi_configure; 152 sc->sc_spi.sct_transfer = sun4ispi_transfer; 153 (void) of_getprop_uint32(phandle, "num-cs", &sc->sc_spi.sct_nslaves); 154 memset(&sba, 0, sizeof(sba)); 155 sba.sba_controller = &sc->sc_spi; 156 157 (void) config_found_ia(self, "spibus", &sba, spibus_print); 158 } 159 160 static int 161 sun4ispi_configure(void *cookie, int slave, int mode, int speed) 162 { 163 struct sun4ispi_softc * const sc = cookie; 164 uint32_t ctl, cctl; 165 uint32_t minfreq, maxfreq; 166 167 minfreq = sc->sc_modclkrate >> 16; 168 maxfreq = sc->sc_modclkrate >> 1; 169 170 if (speed <= 0 || speed < minfreq || speed > maxfreq) 171 return EINVAL; 172 173 if (slave >= sc->sc_spi.sct_nslaves) 174 return EINVAL; 175 176 ctl = SPI_CTL_SDM | SPI_CTL_TP_EN | SPI_CTL_SSPOL | SPI_CTL_MODE | SPI_CTL_EN; 177 178 switch (mode) { 179 case SPI_MODE_0: 180 ctl |= 0; 181 break; 182 case SPI_MODE_1: 183 ctl |= SPI_CTL_PHA; 184 break; 185 case SPI_MODE_2: 186 ctl |= SPI_CTL_POL; 187 break; 188 case SPI_MODE_3: 189 ctl |= SPI_CTL_PHA | SPI_CTL_POL; 190 break; 191 default: 192 return EINVAL; 193 } 194 195 if (speed < sc->sc_modclkrate / 512) { 196 for (cctl = 0; cctl <= __SHIFTOUT_MASK(SPI_CCTL_CDR1); cctl++) { 197 if ((sc->sc_modclkrate / (1 << cctl)) <= speed) 198 goto cdr1_found; 199 } 200 return EINVAL; 201 cdr1_found: 202 cctl = __SHIFTIN(cctl, SPI_CCTL_CDR1); 203 } else { 204 cctl = howmany(sc->sc_modclkrate, 2 * speed) - 1; 205 cctl = SPI_CCTL_DRS|__SHIFTIN(cctl, SPI_CCTL_CDR2); 206 } 207 208 device_printf(sc->sc_dev, "ctl 0x%x, cctl 0x%x, CLK %uHz, SCLK %uHz\n", 209 ctl, cctl, sc->sc_modclkrate, 210 (cctl & SPI_CCTL_DRS) 211 ? (sc->sc_modclkrate / (u_int)(2 * (__SHIFTOUT(cctl, SPI_CCTL_CDR2) + 1))) 212 : (sc->sc_modclkrate >> (__SHIFTOUT(cctl, SPI_CCTL_CDR1) + 1)) 213 ); 214 215 sc->sc_CTL = ctl; 216 SPIREG_WRITE(sc, SPI_CTL, (ctl | SPI_CTL_RF_RST | SPI_CTL_TF_RST) & ~SPI_CTL_EN); 217 SPIREG_WRITE(sc, SPI_CCTL, cctl); 218 SPIREG_WRITE(sc, SPI_CTL, ctl); 219 220 return 0; 221 } 222 223 static int 224 sun4ispi_transfer(void *cookie, struct spi_transfer *st) 225 { 226 struct sun4ispi_softc * const sc = cookie; 227 int s; 228 229 s = splbio(); 230 spi_transq_enqueue(&sc->sc_q, st); 231 if (sc->sc_running == false) { 232 sun4ispi_start(sc); 233 } 234 splx(s); 235 236 return 0; 237 } 238 239 static void 240 sun4ispi_txfifo_fill(struct sun4ispi_softc * const sc, size_t maxlen) 241 { 242 struct spi_chunk *chunk = sc->sc_wchunk; 243 size_t len; 244 uint8_t b; 245 246 if (chunk == NULL) 247 return; 248 249 len = MIN(maxlen, chunk->chunk_wresid); 250 chunk->chunk_wresid -= len; 251 while (len--) { 252 if (chunk->chunk_wptr) { 253 b = *chunk->chunk_wptr++; 254 } else { 255 b = 0; 256 } 257 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SPI_TXDATA, b); 258 } 259 if (sc->sc_wchunk->chunk_wresid == 0) { 260 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 261 } 262 } 263 264 static void 265 sun4ispi_rxfifo_drain(struct sun4ispi_softc * const sc, size_t maxlen) 266 { 267 struct spi_chunk *chunk = sc->sc_rchunk; 268 size_t len; 269 uint8_t b; 270 271 if (chunk == NULL) 272 return; 273 274 len = MIN(maxlen, chunk->chunk_rresid); 275 chunk->chunk_rresid -= len; 276 277 while (len--) { 278 b = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SPI_RXDATA); 279 if (chunk->chunk_rptr) { 280 *chunk->chunk_rptr++ = b; 281 } 282 } 283 if (sc->sc_rchunk->chunk_rresid == 0) { 284 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 285 } 286 } 287 288 static void 289 sun4ispi_rxtx(struct sun4ispi_softc * const sc) 290 { 291 bool again; 292 size_t rxavail, txavail; 293 uint32_t fsr; 294 295 /* service both FIFOs until no more progress can be made */ 296 again = true; 297 while (again) { 298 again = false; 299 fsr = SPIREG_READ(sc, SPI_FIFO_STA); 300 rxavail = __SHIFTOUT(fsr, SPI_FIFO_STA_RF_CNT); 301 txavail = 64 - __SHIFTOUT(fsr, SPI_FIFO_STA_TF_CNT); 302 if (rxavail > 0) { 303 KASSERT(sc->sc_rchunk != NULL); 304 sun4ispi_rxfifo_drain(sc, rxavail); 305 again = true; 306 } 307 if (txavail > 0 && sc->sc_wchunk != NULL) { 308 sun4ispi_txfifo_fill(sc, txavail); 309 again = true; 310 } 311 } 312 } 313 314 static void 315 sun4ispi_set_interrupt_mask(struct sun4ispi_softc * const sc) 316 { 317 uint32_t intctl; 318 319 intctl = SPI_INTCTL_TX_INT_EN; 320 intctl |= SPI_INTCTL_RF_OF_INT_EN; 321 intctl |= SPI_INTCTL_TF_UR_INT_EN; 322 323 if (sc->sc_rchunk) { 324 if (sc->sc_rchunk->chunk_rresid >= 32) { 325 intctl |= SPI_INTCTL_RF_HALF_FU_INT_EN; 326 } else { 327 intctl |= SPI_INTCTL_RF_RDY_INT_EN; 328 } 329 } 330 if (sc->sc_wchunk) { 331 intctl |= SPI_INTCTL_TF_HALF_EMP_INT_EN; 332 } 333 SPIREG_WRITE(sc, SPI_INTCTL, intctl); 334 } 335 336 static void 337 sun4ispi_start(struct sun4ispi_softc * const sc) 338 { 339 struct spi_transfer *st; 340 uint32_t ctl; 341 struct spi_chunk *chunk; 342 size_t burstcount; 343 344 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 345 346 spi_transq_dequeue(&sc->sc_q); 347 348 KASSERT(sc->sc_transfer == NULL); 349 sc->sc_transfer = st; 350 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 351 sc->sc_running = true; 352 353 burstcount = 0; 354 for (chunk = st->st_chunks; chunk; chunk = chunk->chunk_next) { 355 burstcount += chunk->chunk_count; 356 } 357 KASSERT(burstcount <= SPI_BC_BC); 358 SPIREG_WRITE(sc, SPI_BC, __SHIFTIN(burstcount, SPI_BC_BC)); 359 SPIREG_WRITE(sc, SPI_TC, __SHIFTIN(burstcount, SPI_TC_WTC)); 360 361 sun4ispi_rxtx(sc); 362 sun4ispi_set_interrupt_mask(sc); 363 364 KASSERT(st->st_slave < sc->sc_spi.sct_nslaves); 365 ctl = sc->sc_CTL | __SHIFTIN(st->st_slave, SPI_CTL_SS) | SPI_CTL_XCH; 366 SPIREG_WRITE(sc, SPI_CTL, ctl); 367 368 if (!cold) 369 return; 370 371 for (;;) { 372 (void) sun4ispi_intr(sc); 373 if (ISSET(st->st_flags, SPI_F_DONE)) 374 break; 375 } 376 } 377 sc->sc_running = false; 378 } 379 380 static int 381 sun4ispi_intr(void *cookie) 382 { 383 struct sun4ispi_softc * const sc = cookie; 384 struct spi_transfer *st; 385 uint32_t isr; 386 387 isr = SPIREG_READ(sc, SPI_INT_STA); 388 if (!isr) 389 return 0; 390 391 if (ISSET(isr, SPI_INT_STA_RO)) { 392 device_printf(sc->sc_dev, "RXFIFO overflow\n"); 393 } 394 if (ISSET(isr, SPI_INT_STA_TU)) { 395 device_printf(sc->sc_dev, "TXFIFO underrun\n"); 396 } 397 398 sun4ispi_rxtx(sc); 399 400 if (ISSET(isr, SPI_INT_STA_TC)) { 401 SPIREG_WRITE(sc, SPI_INTCTL, 0); 402 KASSERT(sc->sc_rchunk == NULL); 403 KASSERT(sc->sc_wchunk == NULL); 404 st = sc->sc_transfer; 405 sc->sc_transfer = NULL; 406 KASSERT(st != NULL); 407 spi_done(st, 0); 408 sc->sc_running = false; 409 } else { 410 sun4ispi_set_interrupt_mask(sc); 411 } 412 SPIREG_WRITE(sc, SPI_INT_STA, isr); 413 414 return 1; 415 } 416
Indexes created Fri Oct 17 00:09:41 GMT 2025