sun4i_spi.c revision 1.5
1 /* $NetBSD: sun4i_spi.c,v 1.5 2019/09/11 15:03:52 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Tobias Nygren 5 * Copyright (c) 2018 Jonathan A. Kollasch 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 27 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: sun4i_spi.c,v 1.5 2019/09/11 15:03:52 bouyer Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/device.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 #include <sys/bitops.h> 40 #include <dev/spi/spivar.h> 41 #include <arm/sunxi/sun4i_spireg.h> 42 #include <dev/fdt/fdtvar.h> 43 44 static const char * const compatible[] = { 45 "allwinner,sun4i-a10-spi", 46 NULL 47 }; 48 49 struct sun4ispi_softc { 50 device_t sc_dev; 51 bus_space_tag_t sc_bst; 52 bus_space_handle_t sc_bsh; 53 void *sc_intrh; 54 struct spi_controller sc_spi; 55 SIMPLEQ_HEAD(,spi_transfer) sc_q; 56 struct spi_transfer *sc_transfer; 57 struct spi_chunk *sc_rchunk, *sc_wchunk; 58 uint32_t sc_CTL; 59 u_int sc_modclkrate; 60 volatile bool sc_running; 61 }; 62 63 #define SPIREG_READ(sc, reg) \ 64 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 65 #define SPIREG_WRITE(sc, reg, val) \ 66 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 67 68 static struct spi_controller * sun4i_spi_get_controller(device_t); 69 static int sun4ispi_match(device_t, cfdata_t, void *); 70 static void sun4ispi_attach(device_t, device_t, void *); 71 72 static int sun4ispi_configure(void *, int, int, int); 73 static int sun4ispi_transfer(void *, struct spi_transfer *); 74 75 static void sun4ispi_txfifo_fill(struct sun4ispi_softc * const, size_t); 76 static void sun4ispi_rxfifo_drain(struct sun4ispi_softc * const, size_t); 77 static void sun4ispi_rxtx(struct sun4ispi_softc * const); 78 static void sun4ispi_set_interrupt_mask(struct sun4ispi_softc * const); 79 static void sun4ispi_start(struct sun4ispi_softc * const); 80 static int sun4ispi_intr(void *); 81 82 CFATTACH_DECL_NEW(sun4i_spi, sizeof(struct sun4ispi_softc), 83 sun4ispi_match, sun4ispi_attach, NULL, NULL); 84 85 static const struct fdtbus_spi_controller_func sun4i_spi_funcs = { 86 .get_controller = sun4i_spi_get_controller 87 }; 88 89 static struct spi_controller * 90 sun4i_spi_get_controller(device_t dev) 91 { 92 struct sun4ispi_softc * const sc = device_private(dev); 93 94 return &sc->sc_spi; 95 } 96 97 static int 98 sun4ispi_match(device_t parent, cfdata_t cf, void *aux) 99 { 100 struct fdt_attach_args * const faa = aux; 101 102 return of_match_compatible(faa->faa_phandle, compatible); 103 } 104 105 static void 106 sun4ispi_attach(device_t parent, device_t self, void *aux) 107 { 108 struct sun4ispi_softc * const sc = device_private(self); 109 struct fdt_attach_args * const faa = aux; 110 const int phandle = faa->faa_phandle; 111 bus_addr_t addr; 112 bus_size_t size; 113 struct clk *clk, *modclk; 114 char intrstr[128]; 115 116 sc->sc_dev = self; 117 sc->sc_bst = faa->faa_bst; 118 SIMPLEQ_INIT(&sc->sc_q); 119 120 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL 121 || clk_enable(clk) != 0) { 122 aprint_error(": couldn't enable clock\n"); 123 return; 124 } 125 126 if ((modclk = fdtbus_clock_get(phandle, "mod")) == NULL 127 || clk_set_rate(modclk, clk_get_rate(clk)) != 0 128 || clk_enable(modclk) != 0) { 129 aprint_error(": couldn't enable module clock\n"); 130 return; 131 } 132 sc->sc_modclkrate = clk_get_rate(modclk); 133 134 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 135 || bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 136 aprint_error(": couldn't map registers\n"); 137 return; 138 } 139 140 SPIREG_WRITE(sc, SPI_CTL, SPI_CTL_SSPOL | SPI_CTL_RF_RST 141 | SPI_CTL_TF_RST | SPI_CTL_MODE); 142 SPIREG_WRITE(sc, SPI_DMACTL, 0); 143 SPIREG_WRITE(sc, SPI_WAIT, 0); 144 SPIREG_WRITE(sc, SPI_INTCTL, 0); 145 SPIREG_WRITE(sc, SPI_INT_STA, ~0); 146 147 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 148 aprint_error(": failed to decode interrupt\n"); 149 return; 150 } 151 152 sc->sc_intrh = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, sun4ispi_intr, sc); 153 if (sc->sc_intrh == NULL) { 154 aprint_error(": unable to establish interrupt\n"); 155 return; 156 } 157 158 aprint_naive("\n"); 159 aprint_normal(": SPI\n"); 160 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 161 162 sc->sc_spi.sct_cookie = sc; 163 sc->sc_spi.sct_configure = sun4ispi_configure; 164 sc->sc_spi.sct_transfer = sun4ispi_transfer; 165 (void) of_getprop_uint32(phandle, "num-cs", &sc->sc_spi.sct_nslaves); 166 fdtbus_register_spi_controller(self, phandle, &sun4i_spi_funcs); 167 (void) fdtbus_attach_spibus(self, phandle, spibus_print); 168 } 169 170 static int 171 sun4ispi_configure(void *cookie, int slave, int mode, int speed) 172 { 173 struct sun4ispi_softc * const sc = cookie; 174 uint32_t ctl, cctl; 175 uint32_t minfreq, maxfreq; 176 177 minfreq = sc->sc_modclkrate >> 16; 178 maxfreq = sc->sc_modclkrate >> 1; 179 180 if (speed <= 0 || speed < minfreq || speed > maxfreq) 181 return EINVAL; 182 183 if (slave >= sc->sc_spi.sct_nslaves) 184 return EINVAL; 185 186 ctl = SPI_CTL_SDM | SPI_CTL_TP_EN | SPI_CTL_SSPOL | SPI_CTL_MODE | SPI_CTL_EN; 187 188 switch (mode) { 189 case SPI_MODE_0: 190 ctl |= 0; 191 break; 192 case SPI_MODE_1: 193 ctl |= SPI_CTL_PHA; 194 break; 195 case SPI_MODE_2: 196 ctl |= SPI_CTL_POL; 197 break; 198 case SPI_MODE_3: 199 ctl |= SPI_CTL_PHA | SPI_CTL_POL; 200 break; 201 default: 202 return EINVAL; 203 } 204 205 if (speed < sc->sc_modclkrate / 512) { 206 for (cctl = 0; cctl <= __SHIFTOUT_MASK(SPI_CCTL_CDR1); cctl++) { 207 if ((sc->sc_modclkrate / (1 << cctl)) <= speed) 208 goto cdr1_found; 209 } 210 return EINVAL; 211 cdr1_found: 212 cctl = __SHIFTIN(cctl, SPI_CCTL_CDR1); 213 } else { 214 cctl = howmany(sc->sc_modclkrate, 2 * speed) - 1; 215 cctl = SPI_CCTL_DRS|__SHIFTIN(cctl, SPI_CCTL_CDR2); 216 } 217 218 device_printf(sc->sc_dev, "ctl 0x%x, cctl 0x%x, CLK %uHz, SCLK %uHz\n", 219 ctl, cctl, sc->sc_modclkrate, 220 (cctl & SPI_CCTL_DRS) 221 ? (sc->sc_modclkrate / (u_int)(2 * (__SHIFTOUT(cctl, SPI_CCTL_CDR2) + 1))) 222 : (sc->sc_modclkrate >> (__SHIFTOUT(cctl, SPI_CCTL_CDR1) + 1)) 223 ); 224 225 sc->sc_CTL = ctl; 226 SPIREG_WRITE(sc, SPI_CTL, (ctl | SPI_CTL_RF_RST | SPI_CTL_TF_RST) & ~SPI_CTL_EN); 227 SPIREG_WRITE(sc, SPI_CCTL, cctl); 228 SPIREG_WRITE(sc, SPI_CTL, ctl); 229 230 return 0; 231 } 232 233 static int 234 sun4ispi_transfer(void *cookie, struct spi_transfer *st) 235 { 236 struct sun4ispi_softc * const sc = cookie; 237 int s; 238 239 s = splbio(); 240 spi_transq_enqueue(&sc->sc_q, st); 241 if (sc->sc_running == false) { 242 sun4ispi_start(sc); 243 } 244 splx(s); 245 246 return 0; 247 } 248 249 static void 250 sun4ispi_txfifo_fill(struct sun4ispi_softc * const sc, size_t maxlen) 251 { 252 struct spi_chunk *chunk = sc->sc_wchunk; 253 size_t len; 254 uint8_t b; 255 256 if (chunk == NULL) 257 return; 258 259 len = MIN(maxlen, chunk->chunk_wresid); 260 chunk->chunk_wresid -= len; 261 while (len--) { 262 if (chunk->chunk_wptr) { 263 b = *chunk->chunk_wptr++; 264 } else { 265 b = 0; 266 } 267 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SPI_TXDATA, b); 268 } 269 if (sc->sc_wchunk->chunk_wresid == 0) { 270 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 271 } 272 } 273 274 static void 275 sun4ispi_rxfifo_drain(struct sun4ispi_softc * const sc, size_t maxlen) 276 { 277 struct spi_chunk *chunk = sc->sc_rchunk; 278 size_t len; 279 uint8_t b; 280 281 if (chunk == NULL) 282 return; 283 284 len = MIN(maxlen, chunk->chunk_rresid); 285 chunk->chunk_rresid -= len; 286 287 while (len--) { 288 b = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SPI_RXDATA); 289 if (chunk->chunk_rptr) { 290 *chunk->chunk_rptr++ = b; 291 } 292 } 293 if (sc->sc_rchunk->chunk_rresid == 0) { 294 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 295 } 296 } 297 298 static void 299 sun4ispi_rxtx(struct sun4ispi_softc * const sc) 300 { 301 bool again; 302 size_t rxavail, txavail; 303 uint32_t fsr; 304 305 /* service both FIFOs until no more progress can be made */ 306 again = true; 307 while (again) { 308 again = false; 309 fsr = SPIREG_READ(sc, SPI_FIFO_STA); 310 rxavail = __SHIFTOUT(fsr, SPI_FIFO_STA_RF_CNT); 311 txavail = 64 - __SHIFTOUT(fsr, SPI_FIFO_STA_TF_CNT); 312 if (rxavail > 0) { 313 KASSERT(sc->sc_rchunk != NULL); 314 sun4ispi_rxfifo_drain(sc, rxavail); 315 again = true; 316 } 317 if (txavail > 0 && sc->sc_wchunk != NULL) { 318 sun4ispi_txfifo_fill(sc, txavail); 319 again = true; 320 } 321 } 322 } 323 324 static void 325 sun4ispi_set_interrupt_mask(struct sun4ispi_softc * const sc) 326 { 327 uint32_t intctl; 328 329 intctl = SPI_INTCTL_TX_INT_EN; 330 intctl |= SPI_INTCTL_RF_OF_INT_EN; 331 intctl |= SPI_INTCTL_TF_UR_INT_EN; 332 333 if (sc->sc_rchunk) { 334 if (sc->sc_rchunk->chunk_rresid >= 32) { 335 intctl |= SPI_INTCTL_RF_HALF_FU_INT_EN; 336 } else { 337 intctl |= SPI_INTCTL_RF_RDY_INT_EN; 338 } 339 } 340 if (sc->sc_wchunk) { 341 intctl |= SPI_INTCTL_TF_HALF_EMP_INT_EN; 342 } 343 SPIREG_WRITE(sc, SPI_INTCTL, intctl); 344 } 345 346 static void 347 sun4ispi_start(struct sun4ispi_softc * const sc) 348 { 349 struct spi_transfer *st; 350 uint32_t ctl; 351 struct spi_chunk *chunk; 352 size_t burstcount; 353 354 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 355 356 spi_transq_dequeue(&sc->sc_q); 357 358 KASSERT(sc->sc_transfer == NULL); 359 sc->sc_transfer = st; 360 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 361 sc->sc_running = true; 362 363 burstcount = 0; 364 for (chunk = st->st_chunks; chunk; chunk = chunk->chunk_next) { 365 burstcount += chunk->chunk_count; 366 } 367 KASSERT(burstcount <= SPI_BC_BC); 368 SPIREG_WRITE(sc, SPI_BC, __SHIFTIN(burstcount, SPI_BC_BC)); 369 SPIREG_WRITE(sc, SPI_TC, __SHIFTIN(burstcount, SPI_TC_WTC)); 370 371 sun4ispi_rxtx(sc); 372 sun4ispi_set_interrupt_mask(sc); 373 374 KASSERT(st->st_slave < sc->sc_spi.sct_nslaves); 375 ctl = sc->sc_CTL | __SHIFTIN(st->st_slave, SPI_CTL_SS) | SPI_CTL_XCH; 376 SPIREG_WRITE(sc, SPI_CTL, ctl); 377 378 if (!cold) 379 return; 380 381 for (;;) { 382 (void) sun4ispi_intr(sc); 383 if (ISSET(st->st_flags, SPI_F_DONE)) 384 break; 385 } 386 } 387 sc->sc_running = false; 388 } 389 390 static int 391 sun4ispi_intr(void *cookie) 392 { 393 struct sun4ispi_softc * const sc = cookie; 394 struct spi_transfer *st; 395 uint32_t isr; 396 397 isr = SPIREG_READ(sc, SPI_INT_STA); 398 if (!isr) 399 return 0; 400 401 if (ISSET(isr, SPI_INT_STA_RO)) { 402 device_printf(sc->sc_dev, "RXFIFO overflow\n"); 403 } 404 if (ISSET(isr, SPI_INT_STA_TU)) { 405 device_printf(sc->sc_dev, "TXFIFO underrun\n"); 406 } 407 408 sun4ispi_rxtx(sc); 409 410 if (ISSET(isr, SPI_INT_STA_TC)) { 411 SPIREG_WRITE(sc, SPI_INTCTL, 0); 412 KASSERT(sc->sc_rchunk == NULL); 413 KASSERT(sc->sc_wchunk == NULL); 414 st = sc->sc_transfer; 415 sc->sc_transfer = NULL; 416 KASSERT(st != NULL); 417 spi_done(st, 0); 418 sc->sc_running = false; 419 } else { 420 sun4ispi_set_interrupt_mask(sc); 421 } 422 SPIREG_WRITE(sc, SPI_INT_STA, isr); 423 424 return 1; 425 } 426
Indexes created Tue Sep 23 02:09:52 GMT 2025