sun50i_a64_ccu.c revision 1.11
1 /* $NetBSD: sun50i_a64_ccu.c,v 1.11 2019/01/30 01:24:00 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.11 2019/01/30 01:24:00 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_a64_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_VIDEO0_CTRL_REG 0x010 46 #define PLL_PERIPH0_CTRL_REG 0x028 47 #define PLL_PERIPH1_CTRL_REG 0x02c 48 #define PLL_VIDEO1_CTRL_REG 0x030 49 #define PLL_DE_CTRL_REG 0x048 50 #define AHB1_APB1_CFG_REG 0x054 51 #define APB2_CFG_REG 0x058 52 #define AHB2_CFG_REG 0x05c 53 #define BUS_CLK_GATING_REG0 0x060 54 #define BUS_CLK_GATING_REG1 0x064 55 #define BUS_CLK_GATING_REG2 0x068 56 #define BUS_CLK_GATING_REG3 0x06c 57 #define BUS_CLK_GATING_REG4 0x070 58 #define THS_CLK_REG 0x074 59 #define SDMMC0_CLK_REG 0x088 60 #define SDMMC1_CLK_REG 0x08c 61 #define SDMMC2_CLK_REG 0x090 62 #define USBPHY_CFG_REG 0x0cc 63 #define DRAM_CFG_REG 0x0f4 64 #define MBUS_RST_REG 0x0fc 65 #define DE_CLK_REG 0x104 66 #define TCON1_CLK_REG 0x11c 67 #define AC_DIG_CLK_REG 0x140 68 #define HDMI_CLK_REG 0x150 69 #define HDMI_SLOW_CLK_REG 0x154 70 #define BUS_SOFT_RST_REG0 0x2c0 71 #define BUS_SOFT_RST_REG1 0x2c4 72 #define BUS_SOFT_RST_REG2 0x2c8 73 #define BUS_SOFT_RST_REG3 0x2d0 74 #define BUS_SOFT_RST_REG4 0x2d8 75 76 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *); 77 static void sun50i_a64_ccu_attach(device_t, device_t, void *); 78 79 static const char * const compatible[] = { 80 "allwinner,sun50i-a64-ccu", 81 NULL 82 }; 83 84 CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc), 85 sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL); 86 87 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = { 88 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0), 89 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1), 90 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2), 91 92 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31), 93 94 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31), 95 96 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 97 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 98 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 99 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 100 SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 101 SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 102 SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 103 SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 104 SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 105 SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 106 SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 107 SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 108 SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 109 SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 110 SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 111 SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 112 SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 113 SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 114 115 SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 116 SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 117 SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 118 SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 119 SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 120 SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 121 SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 122 SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 123 SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 124 SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 125 SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 126 SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 127 128 SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0), 129 130 SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 131 SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 132 SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 133 SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 134 SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 135 SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 136 137 SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 138 SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 139 SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 140 SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5), 141 SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 142 SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 143 SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 144 SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 145 }; 146 147 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 148 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 149 static const char *apb1_parents[] = { "ahb1" }; 150 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 151 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 152 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL }; 153 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" }; 154 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" }; 155 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL }; 156 157 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = { 158 { 60000000, 9, 0, 0, 2 }, 159 { 66000000, 10, 0, 0, 2 }, 160 { 72000000, 11, 0, 0, 2 }, 161 { 78000000, 12, 0, 0, 2 }, 162 { 84000000, 13, 0, 0, 2 }, 163 { 90000000, 14, 0, 0, 2 }, 164 { 96000000, 15, 0, 0, 2 }, 165 { 102000000, 16, 0, 0, 2 }, 166 { 108000000, 17, 0, 0, 2 }, 167 { 114000000, 18, 0, 0, 2 }, 168 { 120000000, 9, 0, 0, 1 }, 169 { 132000000, 10, 0, 0, 1 }, 170 { 144000000, 11, 0, 0, 1 }, 171 { 156000000, 12, 0, 0, 1 }, 172 { 168000000, 13, 0, 0, 1 }, 173 { 180000000, 14, 0, 0, 1 }, 174 { 192000000, 15, 0, 0, 1 }, 175 { 204000000, 16, 0, 0, 1 }, 176 { 216000000, 17, 0, 0, 1 }, 177 { 228000000, 18, 0, 0, 1 }, 178 { 240000000, 9, 0, 0, 0 }, 179 { 264000000, 10, 0, 0, 0 }, 180 { 288000000, 11, 0, 0, 0 }, 181 { 312000000, 12, 0, 0, 0 }, 182 { 336000000, 13, 0, 0, 0 }, 183 { 360000000, 14, 0, 0, 0 }, 184 { 384000000, 15, 0, 0, 0 }, 185 { 408000000, 16, 0, 0, 0 }, 186 { 432000000, 17, 0, 0, 0 }, 187 { 456000000, 18, 0, 0, 0 }, 188 { 480000000, 19, 0, 0, 0 }, 189 { 504000000, 20, 0, 0, 0 }, 190 { 528000000, 21, 0, 0, 0 }, 191 { 552000000, 22, 0, 0, 0 }, 192 { 576000000, 23, 0, 0, 0 }, 193 { 600000000, 24, 0, 0, 0 }, 194 { 624000000, 25, 0, 0, 0 }, 195 { 648000000, 26, 0, 0, 0 }, 196 { 672000000, 27, 0, 0, 0 }, 197 { 696000000, 28, 0, 0, 0 }, 198 { 720000000, 29, 0, 0, 0 }, 199 { 768000000, 15, 1, 0, 0 }, 200 { 792000000, 10, 2, 0, 0 }, 201 { 816000000, 16, 1, 0, 0 }, 202 { 864000000, 17, 1, 0, 0 }, 203 { 912000000, 18, 1, 0, 0 }, 204 { 936000000, 12, 2, 0, 0 }, 205 { 960000000, 19, 1, 0, 0 }, 206 { 1008000000, 20, 1, 0, 0 }, 207 { 1056000000, 21, 1, 0, 0 }, 208 { 1080000000, 14, 2, 0, 0 }, 209 { 1104000000, 22, 1, 0, 0 }, 210 { 1152000000, 23, 1, 0, 0 }, 211 { 1200000000, 24, 1, 0, 0 }, 212 { 1224000000, 16, 2, 0, 0 }, 213 { 1248000000, 25, 1, 0, 0 }, 214 { 1296000000, 26, 1, 0, 0 }, 215 { 1344000000, 27, 1, 0, 0 }, 216 { 1368000000, 18, 2, 0, 0 }, 217 { 1440000000, 19, 2, 0, 0 }, 218 { 1512000000, 20, 2, 0, 0 }, 219 { 1536000000, 15, 3, 0, 0 }, 220 { 1584000000, 21, 2, 0, 0 }, 221 { 1632000000, 16, 3, 0, 0 }, 222 { 1656000000, 22, 2, 0, 0 }, 223 { 1728000000, 23, 2, 0, 0 }, 224 { 1800000000, 24, 2, 0, 0 }, 225 { 1872000000, 25, 2, 0, 0 }, 226 { 0 } 227 }; 228 229 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_ac_dig_table[] = { 230 { 24576000, 0x55, 0, 0x14, 0x3 }, 231 { 0 } 232 }; 233 234 static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = { 235 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_CPUX, "pll_cpux", "hosc", 236 PLL_CPUX_CTRL_REG, /* reg */ 237 __BITS(12,8), /* n */ 238 __BITS(5,4), /* k */ 239 __BITS(1,0), /* m */ 240 __BITS(17,16), /* p */ 241 __BIT(31), /* enable */ 242 __BIT(28), /* lock */ 243 sun50i_a64_cpux_table, /* table */ 244 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 245 246 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 247 PLL_PERIPH0_CTRL_REG, /* reg */ 248 __BITS(12,8), /* n */ 249 __BITS(5,4), /* k */ 250 0, /* m */ 251 __BITS(17,16), /* p */ 252 __BIT(31), /* enable */ 253 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 254 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2), 255 256 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_AUDIO_BASE, "pll_audio_base", "hosc", 257 PLL_AUDIO_CTRL_REG, /* reg */ 258 __BITS(14,8), /* n */ 259 0, /* k */ 260 __BITS(4,0), /* m */ 261 __BITS(19,16), /* p */ 262 __BIT(31), /* enable */ 263 __BIT(28), /* lock */ 264 sun50i_a64_ac_dig_table, /* table */ 265 0), 266 267 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO, "pll_audio", "pll_audio_base", 1, 1), 268 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_2X, "pll_audio_2x", "pll_audio_base", 1, 2), 269 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_4X, "pll_audio_4x", "pll_audio_base", 1, 4), 270 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_8X, "pll_audio_8x", "pll_audio_base", 1, 8), 271 272 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO0, "pll_video0", "hosc", 273 PLL_VIDEO0_CTRL_REG, /* reg */ 274 __BITS(14,8), /* m */ 275 16, /* m_min */ 276 50, /* m_max */ 277 __BIT(24), /* div_en */ 278 __BIT(25), /* frac_sel */ 279 270000000, 297000000, /* frac values */ 280 __BITS(3,0), /* prediv */ 281 4, /* prediv_val */ 282 __BIT(31), /* enable */ 283 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 284 285 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_VIDEO0_2X, "pll_video0_2x", "pll_video0", 1, 2), 286 287 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO1, "pll_video1", "hosc", 288 PLL_VIDEO1_CTRL_REG, /* reg */ 289 __BITS(14,8), /* m */ 290 16, /* m_min */ 291 50, /* m_max */ 292 __BIT(24), /* div_en */ 293 __BIT(25), /* frac_sel */ 294 270000000, 297000000, /* frac values */ 295 __BITS(3,0), /* prediv */ 296 4, /* prediv_val */ 297 __BIT(31), /* enable */ 298 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 299 300 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_DE, "pll_de", "hosc", 301 PLL_DE_CTRL_REG, /* reg */ 302 __BITS(14,8), /* m */ 303 16, /* m_min */ 304 50, /* m_max */ 305 __BIT(24), /* div_en */ 306 __BIT(25), /* frac_sel */ 307 270000000, 297000000, /* frac values */ 308 __BITS(3,0), /* prediv */ 309 2, /* prediv_val */ 310 __BIT(31), /* enable */ 311 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 312 313 SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents, 314 AHB1_APB1_CFG_REG, /* reg */ 315 __BITS(7,6), /* prediv */ 316 __BIT(3), /* prediv_sel */ 317 __BITS(5,4), /* div */ 318 __BITS(13,12), /* sel */ 319 SUNXI_CCU_PREDIV_POWER_OF_TWO), 320 321 SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents, 322 AHB2_CFG_REG, /* reg */ 323 0, /* prediv */ 324 __BIT(1), /* prediv_sel */ 325 0, /* div */ 326 __BITS(1,0), /* sel */ 327 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 328 329 SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents, 330 AHB1_APB1_CFG_REG, /* reg */ 331 __BITS(9,8), /* div */ 332 0, /* sel */ 333 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 334 335 SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents, 336 APB2_CFG_REG, /* reg */ 337 __BITS(17,16), /* n */ 338 __BITS(4,0), /* m */ 339 __BITS(25,24), /* sel */ 340 0, /* enable */ 341 SUNXI_CCU_NM_POWER_OF_TWO), 342 343 SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mmc_parents, 344 SDMMC0_CLK_REG, /* reg */ 345 __BITS(17,16), /* n */ 346 __BITS(3,0), /* m */ 347 __BITS(25,24), /* sel */ 348 __BIT(31), /* enable */ 349 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 350 SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mmc_parents, 351 SDMMC1_CLK_REG, /* reg */ 352 __BITS(17,16), /* n */ 353 __BITS(3,0), /* m */ 354 __BITS(25,24), /* sel */ 355 __BIT(31), /* enable */ 356 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 357 SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mmc_parents, 358 SDMMC2_CLK_REG, /* reg */ 359 __BITS(17,16), /* n */ 360 __BITS(3,0), /* m */ 361 __BITS(25,24), /* sel */ 362 __BIT(31), /* enable */ 363 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 364 365 SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents, 366 THS_CLK_REG, /* reg */ 367 __BITS(1,0), /* div */ 368 __BITS(25,24), /* sel */ 369 __BIT(31), /* enable */ 370 SUNXI_CCU_DIV_TIMES_TWO), 371 372 SUNXI_CCU_DIV_GATE(A64_CLK_DE, "de", de_parents, 373 DE_CLK_REG, /* reg */ 374 __BITS(3,0), /* div */ 375 __BITS(26,24), /* sel */ 376 __BIT(31), /* enable */ 377 0), 378 379 SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 380 AC_DIG_CLK_REG, 31), 381 SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x", 382 AC_DIG_CLK_REG, 30), 383 384 SUNXI_CCU_DIV_GATE(A64_CLK_HDMI, "hdmi", hdmi_parents, 385 HDMI_CLK_REG, /* reg */ 386 __BITS(3,0), /* div */ 387 __BITS(25,24), /* sel */ 388 __BIT(31), /* enable */ 389 0), 390 391 SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc", 392 HDMI_SLOW_CLK_REG, 31), 393 394 SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents, 395 TCON1_CLK_REG, /* reg */ 396 __BITS(3,0), /* div */ 397 __BITS(25,24), /* sel */ 398 __BIT(31), /* enable */ 399 0), 400 401 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 402 BUS_CLK_GATING_REG0, 1), 403 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 404 BUS_CLK_GATING_REG0, 5), 405 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 406 BUS_CLK_GATING_REG0, 6), 407 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 408 BUS_CLK_GATING_REG0, 8), 409 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 410 BUS_CLK_GATING_REG0, 9), 411 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 412 BUS_CLK_GATING_REG0, 10), 413 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 414 BUS_CLK_GATING_REG0, 13), 415 SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 416 BUS_CLK_GATING_REG0, 14), 417 SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 418 BUS_CLK_GATING_REG0, 17), 419 SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 420 BUS_CLK_GATING_REG0, 18), 421 SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 422 BUS_CLK_GATING_REG0, 19), 423 SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 424 BUS_CLK_GATING_REG0, 20), 425 SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 426 BUS_CLK_GATING_REG0, 21), 427 SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 428 BUS_CLK_GATING_REG0, 23), 429 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 430 BUS_CLK_GATING_REG0, 24), 431 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 432 BUS_CLK_GATING_REG0, 25), 433 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 434 BUS_CLK_GATING_REG0, 28), 435 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 436 BUS_CLK_GATING_REG0, 29), 437 438 SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 439 BUS_CLK_GATING_REG1, 0), 440 SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 441 BUS_CLK_GATING_REG1, 3), 442 SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 443 BUS_CLK_GATING_REG1, 4), 444 SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 445 BUS_CLK_GATING_REG1, 5), 446 SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 447 BUS_CLK_GATING_REG1, 8), 448 SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 449 BUS_CLK_GATING_REG1, 10), 450 SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 451 BUS_CLK_GATING_REG1, 12), 452 SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 453 BUS_CLK_GATING_REG1, 20), 454 SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 455 BUS_CLK_GATING_REG1, 21), 456 SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 457 BUS_CLK_GATING_REG1, 22), 458 459 SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 460 BUS_CLK_GATING_REG2, 0), 461 SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 462 BUS_CLK_GATING_REG2, 1), 463 SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 464 BUS_CLK_GATING_REG2, 5), 465 SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 466 BUS_CLK_GATING_REG2, 8), 467 SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 468 BUS_CLK_GATING_REG2, 12), 469 SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 470 BUS_CLK_GATING_REG2, 13), 471 SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 472 BUS_CLK_GATING_REG2, 14), 473 474 SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 475 BUS_CLK_GATING_REG3, 0), 476 SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 477 BUS_CLK_GATING_REG3, 1), 478 SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 479 BUS_CLK_GATING_REG3, 2), 480 SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2", 481 BUS_CLK_GATING_REG3, 5), 482 SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 483 BUS_CLK_GATING_REG3, 16), 484 SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 485 BUS_CLK_GATING_REG3, 17), 486 SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 487 BUS_CLK_GATING_REG3, 18), 488 SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 489 BUS_CLK_GATING_REG3, 19), 490 SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 491 BUS_CLK_GATING_REG3, 20), 492 493 SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc", 494 USBPHY_CFG_REG, 8), 495 SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc", 496 USBPHY_CFG_REG, 9), 497 SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc", 498 USBPHY_CFG_REG, 10), 499 SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc", 500 USBPHY_CFG_REG, 11), 501 SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc", 502 USBPHY_CFG_REG, 16), 503 SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 504 USBPHY_CFG_REG, 17), 505 }; 506 507 static int 508 sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux) 509 { 510 struct fdt_attach_args * const faa = aux; 511 512 return of_match_compatible(faa->faa_phandle, compatible); 513 } 514 515 static void 516 sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux) 517 { 518 struct sunxi_ccu_softc * const sc = device_private(self); 519 struct fdt_attach_args * const faa = aux; 520 521 sc->sc_dev = self; 522 sc->sc_phandle = faa->faa_phandle; 523 sc->sc_bst = faa->faa_bst; 524 525 sc->sc_resets = sun50i_a64_ccu_resets; 526 sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets); 527 528 sc->sc_clks = sun50i_a64_ccu_clks; 529 sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks); 530 531 if (sunxi_ccu_attach(sc) != 0) 532 return; 533 534 aprint_naive("\n"); 535 aprint_normal(": A64 CCU\n"); 536 537 /* Set DE parent to PLL_DE */ 538 clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base); 539 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000); 540 541 sunxi_ccu_print(sc); 542 } 543
Indexes created Thu Oct 02 14:10:14 GMT 2025