sun50i_a64_ccu.c revision 1.12
1 /* $NetBSD: sun50i_a64_ccu.c,v 1.12 2019/06/27 14:51:33 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.12 2019/06/27 14:51:33 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_a64_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_VIDEO0_CTRL_REG 0x010 46 #define PLL_PERIPH0_CTRL_REG 0x028 47 #define PLL_PERIPH1_CTRL_REG 0x02c 48 #define PLL_VIDEO1_CTRL_REG 0x030 49 #define PLL_GPU_CTRL_REG 0x038 50 #define PLL_DE_CTRL_REG 0x048 51 #define AHB1_APB1_CFG_REG 0x054 52 #define APB2_CFG_REG 0x058 53 #define AHB2_CFG_REG 0x05c 54 #define BUS_CLK_GATING_REG0 0x060 55 #define BUS_CLK_GATING_REG1 0x064 56 #define BUS_CLK_GATING_REG2 0x068 57 #define BUS_CLK_GATING_REG3 0x06c 58 #define BUS_CLK_GATING_REG4 0x070 59 #define THS_CLK_REG 0x074 60 #define SDMMC0_CLK_REG 0x088 61 #define SDMMC1_CLK_REG 0x08c 62 #define SDMMC2_CLK_REG 0x090 63 #define USBPHY_CFG_REG 0x0cc 64 #define DRAM_CFG_REG 0x0f4 65 #define MBUS_RST_REG 0x0fc 66 #define DE_CLK_REG 0x104 67 #define TCON1_CLK_REG 0x11c 68 #define AC_DIG_CLK_REG 0x140 69 #define HDMI_CLK_REG 0x150 70 #define HDMI_SLOW_CLK_REG 0x154 71 #define GPU_CLK_REG 0x1a0 72 #define BUS_SOFT_RST_REG0 0x2c0 73 #define BUS_SOFT_RST_REG1 0x2c4 74 #define BUS_SOFT_RST_REG2 0x2c8 75 #define BUS_SOFT_RST_REG3 0x2d0 76 #define BUS_SOFT_RST_REG4 0x2d8 77 78 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *); 79 static void sun50i_a64_ccu_attach(device_t, device_t, void *); 80 81 static const char * const compatible[] = { 82 "allwinner,sun50i-a64-ccu", 83 NULL 84 }; 85 86 CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc), 87 sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL); 88 89 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = { 90 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0), 91 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1), 92 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2), 93 94 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31), 95 96 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31), 97 98 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 99 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 100 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 101 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 102 SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 103 SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 104 SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 105 SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 106 SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 107 SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 108 SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 109 SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 110 SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 111 SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 112 SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 113 SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 114 SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 115 SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 116 117 SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 118 SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 119 SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 120 SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 121 SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 122 SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 123 SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 124 SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 125 SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 126 SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 127 SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 128 SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 129 130 SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0), 131 132 SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 133 SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 134 SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 135 SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 136 SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 137 SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 138 139 SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 140 SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 141 SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 142 SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5), 143 SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 144 SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 145 SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 146 SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 147 }; 148 149 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 150 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 151 static const char *apb1_parents[] = { "ahb1" }; 152 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 153 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 154 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL }; 155 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" }; 156 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" }; 157 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL }; 158 static const char *gpu_parents[] = { "gpu" }; 159 160 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = { 161 { 60000000, 9, 0, 0, 2 }, 162 { 66000000, 10, 0, 0, 2 }, 163 { 72000000, 11, 0, 0, 2 }, 164 { 78000000, 12, 0, 0, 2 }, 165 { 84000000, 13, 0, 0, 2 }, 166 { 90000000, 14, 0, 0, 2 }, 167 { 96000000, 15, 0, 0, 2 }, 168 { 102000000, 16, 0, 0, 2 }, 169 { 108000000, 17, 0, 0, 2 }, 170 { 114000000, 18, 0, 0, 2 }, 171 { 120000000, 9, 0, 0, 1 }, 172 { 132000000, 10, 0, 0, 1 }, 173 { 144000000, 11, 0, 0, 1 }, 174 { 156000000, 12, 0, 0, 1 }, 175 { 168000000, 13, 0, 0, 1 }, 176 { 180000000, 14, 0, 0, 1 }, 177 { 192000000, 15, 0, 0, 1 }, 178 { 204000000, 16, 0, 0, 1 }, 179 { 216000000, 17, 0, 0, 1 }, 180 { 228000000, 18, 0, 0, 1 }, 181 { 240000000, 9, 0, 0, 0 }, 182 { 264000000, 10, 0, 0, 0 }, 183 { 288000000, 11, 0, 0, 0 }, 184 { 312000000, 12, 0, 0, 0 }, 185 { 336000000, 13, 0, 0, 0 }, 186 { 360000000, 14, 0, 0, 0 }, 187 { 384000000, 15, 0, 0, 0 }, 188 { 408000000, 16, 0, 0, 0 }, 189 { 432000000, 17, 0, 0, 0 }, 190 { 456000000, 18, 0, 0, 0 }, 191 { 480000000, 19, 0, 0, 0 }, 192 { 504000000, 20, 0, 0, 0 }, 193 { 528000000, 21, 0, 0, 0 }, 194 { 552000000, 22, 0, 0, 0 }, 195 { 576000000, 23, 0, 0, 0 }, 196 { 600000000, 24, 0, 0, 0 }, 197 { 624000000, 25, 0, 0, 0 }, 198 { 648000000, 26, 0, 0, 0 }, 199 { 672000000, 27, 0, 0, 0 }, 200 { 696000000, 28, 0, 0, 0 }, 201 { 720000000, 29, 0, 0, 0 }, 202 { 768000000, 15, 1, 0, 0 }, 203 { 792000000, 10, 2, 0, 0 }, 204 { 816000000, 16, 1, 0, 0 }, 205 { 864000000, 17, 1, 0, 0 }, 206 { 912000000, 18, 1, 0, 0 }, 207 { 936000000, 12, 2, 0, 0 }, 208 { 960000000, 19, 1, 0, 0 }, 209 { 1008000000, 20, 1, 0, 0 }, 210 { 1056000000, 21, 1, 0, 0 }, 211 { 1080000000, 14, 2, 0, 0 }, 212 { 1104000000, 22, 1, 0, 0 }, 213 { 1152000000, 23, 1, 0, 0 }, 214 { 1200000000, 24, 1, 0, 0 }, 215 { 1224000000, 16, 2, 0, 0 }, 216 { 1248000000, 25, 1, 0, 0 }, 217 { 1296000000, 26, 1, 0, 0 }, 218 { 1344000000, 27, 1, 0, 0 }, 219 { 1368000000, 18, 2, 0, 0 }, 220 { 1440000000, 19, 2, 0, 0 }, 221 { 1512000000, 20, 2, 0, 0 }, 222 { 1536000000, 15, 3, 0, 0 }, 223 { 1584000000, 21, 2, 0, 0 }, 224 { 1632000000, 16, 3, 0, 0 }, 225 { 1656000000, 22, 2, 0, 0 }, 226 { 1728000000, 23, 2, 0, 0 }, 227 { 1800000000, 24, 2, 0, 0 }, 228 { 1872000000, 25, 2, 0, 0 }, 229 { 0 } 230 }; 231 232 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_ac_dig_table[] = { 233 { 24576000, 0x55, 0, 0x14, 0x3 }, 234 { 0 } 235 }; 236 237 static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = { 238 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_CPUX, "pll_cpux", "hosc", 239 PLL_CPUX_CTRL_REG, /* reg */ 240 __BITS(12,8), /* n */ 241 __BITS(5,4), /* k */ 242 __BITS(1,0), /* m */ 243 __BITS(17,16), /* p */ 244 __BIT(31), /* enable */ 245 __BIT(28), /* lock */ 246 sun50i_a64_cpux_table, /* table */ 247 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 248 249 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 250 PLL_PERIPH0_CTRL_REG, /* reg */ 251 __BITS(12,8), /* n */ 252 __BITS(5,4), /* k */ 253 0, /* m */ 254 __BITS(17,16), /* p */ 255 __BIT(31), /* enable */ 256 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 257 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2), 258 259 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_AUDIO_BASE, "pll_audio_base", "hosc", 260 PLL_AUDIO_CTRL_REG, /* reg */ 261 __BITS(14,8), /* n */ 262 0, /* k */ 263 __BITS(4,0), /* m */ 264 __BITS(19,16), /* p */ 265 __BIT(31), /* enable */ 266 __BIT(28), /* lock */ 267 sun50i_a64_ac_dig_table, /* table */ 268 0), 269 270 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO, "pll_audio", "pll_audio_base", 1, 1), 271 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_2X, "pll_audio_2x", "pll_audio_base", 1, 2), 272 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_4X, "pll_audio_4x", "pll_audio_base", 1, 4), 273 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_8X, "pll_audio_8x", "pll_audio_base", 1, 8), 274 275 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO0, "pll_video0", "hosc", 276 PLL_VIDEO0_CTRL_REG, /* reg */ 277 __BITS(14,8), /* m */ 278 16, /* m_min */ 279 50, /* m_max */ 280 __BIT(24), /* div_en */ 281 __BIT(25), /* frac_sel */ 282 270000000, 297000000, /* frac values */ 283 __BITS(3,0), /* prediv */ 284 4, /* prediv_val */ 285 __BIT(31), /* enable */ 286 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 287 288 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_VIDEO0_2X, "pll_video0_2x", "pll_video0", 1, 2), 289 290 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO1, "pll_video1", "hosc", 291 PLL_VIDEO1_CTRL_REG, /* reg */ 292 __BITS(14,8), /* m */ 293 16, /* m_min */ 294 50, /* m_max */ 295 __BIT(24), /* div_en */ 296 __BIT(25), /* frac_sel */ 297 270000000, 297000000, /* frac values */ 298 __BITS(3,0), /* prediv */ 299 4, /* prediv_val */ 300 __BIT(31), /* enable */ 301 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 302 303 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_DE, "pll_de", "hosc", 304 PLL_DE_CTRL_REG, /* reg */ 305 __BITS(14,8), /* m */ 306 16, /* m_min */ 307 50, /* m_max */ 308 __BIT(24), /* div_en */ 309 __BIT(25), /* frac_sel */ 310 270000000, 297000000, /* frac values */ 311 __BITS(3,0), /* prediv */ 312 2, /* prediv_val */ 313 __BIT(31), /* enable */ 314 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 315 316 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_GPU, "pll_gpu", "hosc", 317 PLL_GPU_CTRL_REG, /* reg */ 318 __BITS(14,8), /* m */ 319 1, /* m_min */ 320 128, /* m_max */ 321 __BIT(24), /* div_en */ 322 __BIT(25), /* frac_sel */ 323 270000000, 297000000, /* frac values */ 324 __BITS(3,0), /* prediv */ 325 4, /* prediv_val */ 326 __BIT(31), /* enable */ 327 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 328 329 SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents, 330 AHB1_APB1_CFG_REG, /* reg */ 331 __BITS(7,6), /* prediv */ 332 __BIT(3), /* prediv_sel */ 333 __BITS(5,4), /* div */ 334 __BITS(13,12), /* sel */ 335 SUNXI_CCU_PREDIV_POWER_OF_TWO), 336 337 SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents, 338 AHB2_CFG_REG, /* reg */ 339 0, /* prediv */ 340 __BIT(1), /* prediv_sel */ 341 0, /* div */ 342 __BITS(1,0), /* sel */ 343 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 344 345 SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents, 346 AHB1_APB1_CFG_REG, /* reg */ 347 __BITS(9,8), /* div */ 348 0, /* sel */ 349 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 350 351 SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents, 352 APB2_CFG_REG, /* reg */ 353 __BITS(17,16), /* n */ 354 __BITS(4,0), /* m */ 355 __BITS(25,24), /* sel */ 356 0, /* enable */ 357 SUNXI_CCU_NM_POWER_OF_TWO), 358 359 SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mmc_parents, 360 SDMMC0_CLK_REG, /* reg */ 361 __BITS(17,16), /* n */ 362 __BITS(3,0), /* m */ 363 __BITS(25,24), /* sel */ 364 __BIT(31), /* enable */ 365 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 366 SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mmc_parents, 367 SDMMC1_CLK_REG, /* reg */ 368 __BITS(17,16), /* n */ 369 __BITS(3,0), /* m */ 370 __BITS(25,24), /* sel */ 371 __BIT(31), /* enable */ 372 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 373 SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mmc_parents, 374 SDMMC2_CLK_REG, /* reg */ 375 __BITS(17,16), /* n */ 376 __BITS(3,0), /* m */ 377 __BITS(25,24), /* sel */ 378 __BIT(31), /* enable */ 379 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 380 381 SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents, 382 THS_CLK_REG, /* reg */ 383 __BITS(1,0), /* div */ 384 __BITS(25,24), /* sel */ 385 __BIT(31), /* enable */ 386 SUNXI_CCU_DIV_TIMES_TWO), 387 388 SUNXI_CCU_DIV_GATE(A64_CLK_DE, "de", de_parents, 389 DE_CLK_REG, /* reg */ 390 __BITS(3,0), /* div */ 391 __BITS(26,24), /* sel */ 392 __BIT(31), /* enable */ 393 0), 394 395 SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 396 AC_DIG_CLK_REG, 31), 397 SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x", 398 AC_DIG_CLK_REG, 30), 399 400 SUNXI_CCU_DIV_GATE(A64_CLK_HDMI, "hdmi", hdmi_parents, 401 HDMI_CLK_REG, /* reg */ 402 __BITS(3,0), /* div */ 403 __BITS(25,24), /* sel */ 404 __BIT(31), /* enable */ 405 0), 406 407 SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc", 408 HDMI_SLOW_CLK_REG, 31), 409 410 SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents, 411 TCON1_CLK_REG, /* reg */ 412 __BITS(3,0), /* div */ 413 __BITS(25,24), /* sel */ 414 __BIT(31), /* enable */ 415 0), 416 417 SUNXI_CCU_DIV_GATE(A64_CLK_GPU, "gpu", gpu_parents, 418 GPU_CLK_REG, /* reg */ 419 __BITS(2,0), /* div */ 420 0, /* sel */ 421 __BIT(31), /* enable */ 422 0), 423 424 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 425 BUS_CLK_GATING_REG0, 1), 426 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 427 BUS_CLK_GATING_REG0, 5), 428 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 429 BUS_CLK_GATING_REG0, 6), 430 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 431 BUS_CLK_GATING_REG0, 8), 432 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 433 BUS_CLK_GATING_REG0, 9), 434 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 435 BUS_CLK_GATING_REG0, 10), 436 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 437 BUS_CLK_GATING_REG0, 13), 438 SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 439 BUS_CLK_GATING_REG0, 14), 440 SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 441 BUS_CLK_GATING_REG0, 17), 442 SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 443 BUS_CLK_GATING_REG0, 18), 444 SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 445 BUS_CLK_GATING_REG0, 19), 446 SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 447 BUS_CLK_GATING_REG0, 20), 448 SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 449 BUS_CLK_GATING_REG0, 21), 450 SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 451 BUS_CLK_GATING_REG0, 23), 452 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 453 BUS_CLK_GATING_REG0, 24), 454 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 455 BUS_CLK_GATING_REG0, 25), 456 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 457 BUS_CLK_GATING_REG0, 28), 458 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 459 BUS_CLK_GATING_REG0, 29), 460 461 SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 462 BUS_CLK_GATING_REG1, 0), 463 SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 464 BUS_CLK_GATING_REG1, 3), 465 SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 466 BUS_CLK_GATING_REG1, 4), 467 SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 468 BUS_CLK_GATING_REG1, 5), 469 SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 470 BUS_CLK_GATING_REG1, 8), 471 SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 472 BUS_CLK_GATING_REG1, 10), 473 SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 474 BUS_CLK_GATING_REG1, 12), 475 SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 476 BUS_CLK_GATING_REG1, 20), 477 SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 478 BUS_CLK_GATING_REG1, 21), 479 SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 480 BUS_CLK_GATING_REG1, 22), 481 482 SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 483 BUS_CLK_GATING_REG2, 0), 484 SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 485 BUS_CLK_GATING_REG2, 1), 486 SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 487 BUS_CLK_GATING_REG2, 5), 488 SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 489 BUS_CLK_GATING_REG2, 8), 490 SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 491 BUS_CLK_GATING_REG2, 12), 492 SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 493 BUS_CLK_GATING_REG2, 13), 494 SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 495 BUS_CLK_GATING_REG2, 14), 496 497 SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 498 BUS_CLK_GATING_REG3, 0), 499 SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 500 BUS_CLK_GATING_REG3, 1), 501 SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 502 BUS_CLK_GATING_REG3, 2), 503 SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2", 504 BUS_CLK_GATING_REG3, 5), 505 SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 506 BUS_CLK_GATING_REG3, 16), 507 SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 508 BUS_CLK_GATING_REG3, 17), 509 SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 510 BUS_CLK_GATING_REG3, 18), 511 SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 512 BUS_CLK_GATING_REG3, 19), 513 SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 514 BUS_CLK_GATING_REG3, 20), 515 516 SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc", 517 USBPHY_CFG_REG, 8), 518 SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc", 519 USBPHY_CFG_REG, 9), 520 SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc", 521 USBPHY_CFG_REG, 10), 522 SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc", 523 USBPHY_CFG_REG, 11), 524 SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc", 525 USBPHY_CFG_REG, 16), 526 SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 527 USBPHY_CFG_REG, 17), 528 }; 529 530 static int 531 sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux) 532 { 533 struct fdt_attach_args * const faa = aux; 534 535 return of_match_compatible(faa->faa_phandle, compatible); 536 } 537 538 static void 539 sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux) 540 { 541 struct sunxi_ccu_softc * const sc = device_private(self); 542 struct fdt_attach_args * const faa = aux; 543 544 sc->sc_dev = self; 545 sc->sc_phandle = faa->faa_phandle; 546 sc->sc_bst = faa->faa_bst; 547 548 sc->sc_resets = sun50i_a64_ccu_resets; 549 sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets); 550 551 sc->sc_clks = sun50i_a64_ccu_clks; 552 sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks); 553 554 if (sunxi_ccu_attach(sc) != 0) 555 return; 556 557 aprint_naive("\n"); 558 aprint_normal(": A64 CCU\n"); 559 560 /* Set DE parent to PLL_DE */ 561 clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base); 562 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000); 563 564 sunxi_ccu_print(sc); 565 } 566
Indexes created Thu Oct 02 14:10:14 GMT 2025