sun50i_a64_ccu.c revision 1.14
1 /* $NetBSD: sun50i_a64_ccu.c,v 1.14 2019/11/17 17:33:17 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.14 2019/11/17 17:33:17 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_a64_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_VIDEO0_CTRL_REG 0x010 46 #define PLL_PERIPH0_CTRL_REG 0x028 47 #define PLL_PERIPH1_CTRL_REG 0x02c 48 #define PLL_VIDEO1_CTRL_REG 0x030 49 #define PLL_GPU_CTRL_REG 0x038 50 #define PLL_DE_CTRL_REG 0x048 51 #define AHB1_APB1_CFG_REG 0x054 52 #define APB2_CFG_REG 0x058 53 #define AHB2_CFG_REG 0x05c 54 #define BUS_CLK_GATING_REG0 0x060 55 #define BUS_CLK_GATING_REG1 0x064 56 #define BUS_CLK_GATING_REG2 0x068 57 #define BUS_CLK_GATING_REG3 0x06c 58 #define BUS_CLK_GATING_REG4 0x070 59 #define THS_CLK_REG 0x074 60 #define SDMMC0_CLK_REG 0x088 61 #define SDMMC1_CLK_REG 0x08c 62 #define SDMMC2_CLK_REG 0x090 63 #define I2SPCM0_CLK_REG 0x0b0 64 #define I2SPCM1_CLK_REG 0x0b4 65 #define I2SPCM2_CLK_REG 0x0b8 66 #define USBPHY_CFG_REG 0x0cc 67 #define DRAM_CFG_REG 0x0f4 68 #define MBUS_RST_REG 0x0fc 69 #define DE_CLK_REG 0x104 70 #define TCON1_CLK_REG 0x11c 71 #define AC_DIG_CLK_REG 0x140 72 #define HDMI_CLK_REG 0x150 73 #define HDMI_SLOW_CLK_REG 0x154 74 #define GPU_CLK_REG 0x1a0 75 #define BUS_SOFT_RST_REG0 0x2c0 76 #define BUS_SOFT_RST_REG1 0x2c4 77 #define BUS_SOFT_RST_REG2 0x2c8 78 #define BUS_SOFT_RST_REG3 0x2d0 79 #define BUS_SOFT_RST_REG4 0x2d8 80 81 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *); 82 static void sun50i_a64_ccu_attach(device_t, device_t, void *); 83 84 static const char * const compatible[] = { 85 "allwinner,sun50i-a64-ccu", 86 NULL 87 }; 88 89 CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc), 90 sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL); 91 92 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = { 93 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0), 94 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1), 95 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2), 96 97 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31), 98 99 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31), 100 101 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 102 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 103 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 104 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 105 SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 106 SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 107 SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 108 SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 109 SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 110 SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 111 SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 112 SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 113 SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 114 SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 115 SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 116 SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 117 SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 118 SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 119 120 SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 121 SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 122 SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 123 SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 124 SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 125 SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 126 SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 127 SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 128 SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 129 SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 130 SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 131 SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 132 133 SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0), 134 135 SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 136 SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 137 SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 138 SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 139 SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 140 SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 141 142 SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 143 SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 144 SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 145 SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5), 146 SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 147 SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 148 SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 149 SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 150 }; 151 152 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 153 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 154 static const char *apb1_parents[] = { "ahb1" }; 155 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 156 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 157 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL }; 158 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" }; 159 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" }; 160 static const char *i2s_parents[] = { "pll_audio_8x", "pll_audio_4x", "pll_audio_2x", "pll_audio" }; 161 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL }; 162 static const char *gpu_parents[] = { "pll_gpu" }; 163 164 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = { 165 { 60000000, 9, 0, 0, 2 }, 166 { 66000000, 10, 0, 0, 2 }, 167 { 72000000, 11, 0, 0, 2 }, 168 { 78000000, 12, 0, 0, 2 }, 169 { 84000000, 13, 0, 0, 2 }, 170 { 90000000, 14, 0, 0, 2 }, 171 { 96000000, 15, 0, 0, 2 }, 172 { 102000000, 16, 0, 0, 2 }, 173 { 108000000, 17, 0, 0, 2 }, 174 { 114000000, 18, 0, 0, 2 }, 175 { 120000000, 9, 0, 0, 1 }, 176 { 132000000, 10, 0, 0, 1 }, 177 { 144000000, 11, 0, 0, 1 }, 178 { 156000000, 12, 0, 0, 1 }, 179 { 168000000, 13, 0, 0, 1 }, 180 { 180000000, 14, 0, 0, 1 }, 181 { 192000000, 15, 0, 0, 1 }, 182 { 204000000, 16, 0, 0, 1 }, 183 { 216000000, 17, 0, 0, 1 }, 184 { 228000000, 18, 0, 0, 1 }, 185 { 240000000, 9, 0, 0, 0 }, 186 { 264000000, 10, 0, 0, 0 }, 187 { 288000000, 11, 0, 0, 0 }, 188 { 312000000, 12, 0, 0, 0 }, 189 { 336000000, 13, 0, 0, 0 }, 190 { 360000000, 14, 0, 0, 0 }, 191 { 384000000, 15, 0, 0, 0 }, 192 { 408000000, 16, 0, 0, 0 }, 193 { 432000000, 17, 0, 0, 0 }, 194 { 456000000, 18, 0, 0, 0 }, 195 { 480000000, 19, 0, 0, 0 }, 196 { 504000000, 20, 0, 0, 0 }, 197 { 528000000, 21, 0, 0, 0 }, 198 { 552000000, 22, 0, 0, 0 }, 199 { 576000000, 23, 0, 0, 0 }, 200 { 600000000, 24, 0, 0, 0 }, 201 { 624000000, 25, 0, 0, 0 }, 202 { 648000000, 26, 0, 0, 0 }, 203 { 672000000, 27, 0, 0, 0 }, 204 { 696000000, 28, 0, 0, 0 }, 205 { 720000000, 29, 0, 0, 0 }, 206 { 768000000, 15, 1, 0, 0 }, 207 { 792000000, 10, 2, 0, 0 }, 208 { 816000000, 16, 1, 0, 0 }, 209 { 864000000, 17, 1, 0, 0 }, 210 { 912000000, 18, 1, 0, 0 }, 211 { 936000000, 12, 2, 0, 0 }, 212 { 960000000, 19, 1, 0, 0 }, 213 { 1008000000, 20, 1, 0, 0 }, 214 { 1056000000, 21, 1, 0, 0 }, 215 { 1080000000, 14, 2, 0, 0 }, 216 { 1104000000, 22, 1, 0, 0 }, 217 { 1152000000, 23, 1, 0, 0 }, 218 { 1200000000, 24, 1, 0, 0 }, 219 { 1224000000, 16, 2, 0, 0 }, 220 { 1248000000, 25, 1, 0, 0 }, 221 { 1296000000, 26, 1, 0, 0 }, 222 { 1344000000, 27, 1, 0, 0 }, 223 { 1368000000, 18, 2, 0, 0 }, 224 { 1440000000, 19, 2, 0, 0 }, 225 { 1512000000, 20, 2, 0, 0 }, 226 { 1536000000, 15, 3, 0, 0 }, 227 { 1584000000, 21, 2, 0, 0 }, 228 { 1632000000, 16, 3, 0, 0 }, 229 { 1656000000, 22, 2, 0, 0 }, 230 { 1728000000, 23, 2, 0, 0 }, 231 { 1800000000, 24, 2, 0, 0 }, 232 { 1872000000, 25, 2, 0, 0 }, 233 { 0 } 234 }; 235 236 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_ac_dig_table[] = { 237 { 24576000, 0x55, 0, 0x14, 0x3 }, 238 { 0 } 239 }; 240 241 static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = { 242 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_CPUX, "pll_cpux", "hosc", 243 PLL_CPUX_CTRL_REG, /* reg */ 244 __BITS(12,8), /* n */ 245 __BITS(5,4), /* k */ 246 __BITS(1,0), /* m */ 247 __BITS(17,16), /* p */ 248 __BIT(31), /* enable */ 249 __BIT(28), /* lock */ 250 sun50i_a64_cpux_table, /* table */ 251 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 252 253 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 254 PLL_PERIPH0_CTRL_REG, /* reg */ 255 __BITS(12,8), /* n */ 256 __BITS(5,4), /* k */ 257 0, /* m */ 258 __BITS(17,16), /* p */ 259 __BIT(31), /* enable */ 260 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 261 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2), 262 263 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_AUDIO_BASE, "pll_audio_base", "hosc", 264 PLL_AUDIO_CTRL_REG, /* reg */ 265 __BITS(14,8), /* n */ 266 0, /* k */ 267 __BITS(4,0), /* m */ 268 __BITS(19,16), /* p */ 269 __BIT(31), /* enable */ 270 __BIT(28), /* lock */ 271 sun50i_a64_ac_dig_table, /* table */ 272 0), 273 274 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO, "pll_audio", "pll_audio_base", 1, 1), 275 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_2X, "pll_audio_2x", "pll_audio_base", 1, 2), 276 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_4X, "pll_audio_4x", "pll_audio_base", 1, 4), 277 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_8X, "pll_audio_8x", "pll_audio_base", 1, 8), 278 279 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO0, "pll_video0", "hosc", 280 PLL_VIDEO0_CTRL_REG, /* reg */ 281 __BITS(14,8), /* m */ 282 16, /* m_min */ 283 50, /* m_max */ 284 __BIT(24), /* div_en */ 285 __BIT(25), /* frac_sel */ 286 270000000, 297000000, /* frac values */ 287 __BITS(3,0), /* prediv */ 288 4, /* prediv_val */ 289 __BIT(31), /* enable */ 290 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 291 292 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_VIDEO0_2X, "pll_video0_2x", "pll_video0", 1, 2), 293 294 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO1, "pll_video1", "hosc", 295 PLL_VIDEO1_CTRL_REG, /* reg */ 296 __BITS(14,8), /* m */ 297 16, /* m_min */ 298 50, /* m_max */ 299 __BIT(24), /* div_en */ 300 __BIT(25), /* frac_sel */ 301 270000000, 297000000, /* frac values */ 302 __BITS(3,0), /* prediv */ 303 4, /* prediv_val */ 304 __BIT(31), /* enable */ 305 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 306 307 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_DE, "pll_de", "hosc", 308 PLL_DE_CTRL_REG, /* reg */ 309 __BITS(14,8), /* m */ 310 16, /* m_min */ 311 50, /* m_max */ 312 __BIT(24), /* div_en */ 313 __BIT(25), /* frac_sel */ 314 270000000, 297000000, /* frac values */ 315 __BITS(3,0), /* prediv */ 316 2, /* prediv_val */ 317 __BIT(31), /* enable */ 318 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 319 320 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_GPU, "pll_gpu", "hosc", 321 PLL_GPU_CTRL_REG, /* reg */ 322 __BITS(14,8), /* m */ 323 1, /* m_min */ 324 128, /* m_max */ 325 __BIT(24), /* div_en */ 326 __BIT(25), /* frac_sel */ 327 270000000, 297000000, /* frac values */ 328 __BITS(3,0), /* prediv */ 329 4, /* prediv_val */ 330 __BIT(31), /* enable */ 331 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 332 333 SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents, 334 AHB1_APB1_CFG_REG, /* reg */ 335 __BITS(7,6), /* prediv */ 336 __BIT(3), /* prediv_sel */ 337 __BITS(5,4), /* div */ 338 __BITS(13,12), /* sel */ 339 SUNXI_CCU_PREDIV_POWER_OF_TWO), 340 341 SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents, 342 AHB2_CFG_REG, /* reg */ 343 0, /* prediv */ 344 __BIT(1), /* prediv_sel */ 345 0, /* div */ 346 __BITS(1,0), /* sel */ 347 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 348 349 SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents, 350 AHB1_APB1_CFG_REG, /* reg */ 351 __BITS(9,8), /* div */ 352 0, /* sel */ 353 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 354 355 SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents, 356 APB2_CFG_REG, /* reg */ 357 __BITS(17,16), /* n */ 358 __BITS(4,0), /* m */ 359 __BITS(25,24), /* sel */ 360 0, /* enable */ 361 SUNXI_CCU_NM_POWER_OF_TWO), 362 363 SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mmc_parents, 364 SDMMC0_CLK_REG, /* reg */ 365 __BITS(17,16), /* n */ 366 __BITS(3,0), /* m */ 367 __BITS(25,24), /* sel */ 368 __BIT(31), /* enable */ 369 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 370 SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mmc_parents, 371 SDMMC1_CLK_REG, /* reg */ 372 __BITS(17,16), /* n */ 373 __BITS(3,0), /* m */ 374 __BITS(25,24), /* sel */ 375 __BIT(31), /* enable */ 376 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 377 SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mmc_parents, 378 SDMMC2_CLK_REG, /* reg */ 379 __BITS(17,16), /* n */ 380 __BITS(3,0), /* m */ 381 __BITS(25,24), /* sel */ 382 __BIT(31), /* enable */ 383 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 384 385 SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents, 386 THS_CLK_REG, /* reg */ 387 __BITS(1,0), /* div */ 388 __BITS(25,24), /* sel */ 389 __BIT(31), /* enable */ 390 SUNXI_CCU_DIV_TIMES_TWO), 391 392 SUNXI_CCU_DIV_GATE(A64_CLK_DE, "de", de_parents, 393 DE_CLK_REG, /* reg */ 394 __BITS(3,0), /* div */ 395 __BITS(26,24), /* sel */ 396 __BIT(31), /* enable */ 397 0), 398 399 SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 400 AC_DIG_CLK_REG, 31), 401 SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x", 402 AC_DIG_CLK_REG, 30), 403 404 SUNXI_CCU_DIV_GATE(A64_CLK_HDMI, "hdmi", hdmi_parents, 405 HDMI_CLK_REG, /* reg */ 406 __BITS(3,0), /* div */ 407 __BITS(25,24), /* sel */ 408 __BIT(31), /* enable */ 409 0), 410 411 SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc", 412 HDMI_SLOW_CLK_REG, 31), 413 414 SUNXI_CCU_DIV_GATE(A64_CLK_I2S0, "i2s0", i2s_parents, 415 I2SPCM0_CLK_REG, /* reg */ 416 0, /* div */ 417 __BITS(17,16), /* sel */ 418 __BIT(31), /* enable */ 419 0), 420 SUNXI_CCU_DIV_GATE(A64_CLK_I2S1, "i2s1", i2s_parents, 421 I2SPCM1_CLK_REG, /* reg */ 422 0, /* div */ 423 __BITS(17,16), /* sel */ 424 __BIT(31), /* enable */ 425 0), 426 SUNXI_CCU_DIV_GATE(A64_CLK_I2S2, "i2s2", i2s_parents, 427 I2SPCM2_CLK_REG, /* reg */ 428 0, /* div */ 429 __BITS(17,16), /* sel */ 430 __BIT(31), /* enable */ 431 0), 432 433 434 SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents, 435 TCON1_CLK_REG, /* reg */ 436 __BITS(3,0), /* div */ 437 __BITS(25,24), /* sel */ 438 __BIT(31), /* enable */ 439 0), 440 441 SUNXI_CCU_DIV_GATE(A64_CLK_GPU, "gpu", gpu_parents, 442 GPU_CLK_REG, /* reg */ 443 __BITS(2,0), /* div */ 444 0, /* sel */ 445 __BIT(31), /* enable */ 446 0), 447 448 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 449 BUS_CLK_GATING_REG0, 1), 450 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 451 BUS_CLK_GATING_REG0, 5), 452 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 453 BUS_CLK_GATING_REG0, 6), 454 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 455 BUS_CLK_GATING_REG0, 8), 456 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 457 BUS_CLK_GATING_REG0, 9), 458 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 459 BUS_CLK_GATING_REG0, 10), 460 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 461 BUS_CLK_GATING_REG0, 13), 462 SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 463 BUS_CLK_GATING_REG0, 14), 464 SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 465 BUS_CLK_GATING_REG0, 17), 466 SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 467 BUS_CLK_GATING_REG0, 18), 468 SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 469 BUS_CLK_GATING_REG0, 19), 470 SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 471 BUS_CLK_GATING_REG0, 20), 472 SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 473 BUS_CLK_GATING_REG0, 21), 474 SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 475 BUS_CLK_GATING_REG0, 23), 476 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 477 BUS_CLK_GATING_REG0, 24), 478 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 479 BUS_CLK_GATING_REG0, 25), 480 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 481 BUS_CLK_GATING_REG0, 28), 482 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 483 BUS_CLK_GATING_REG0, 29), 484 485 SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 486 BUS_CLK_GATING_REG1, 0), 487 SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 488 BUS_CLK_GATING_REG1, 3), 489 SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 490 BUS_CLK_GATING_REG1, 4), 491 SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 492 BUS_CLK_GATING_REG1, 5), 493 SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 494 BUS_CLK_GATING_REG1, 8), 495 SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 496 BUS_CLK_GATING_REG1, 10), 497 SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 498 BUS_CLK_GATING_REG1, 12), 499 SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 500 BUS_CLK_GATING_REG1, 20), 501 SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 502 BUS_CLK_GATING_REG1, 21), 503 SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 504 BUS_CLK_GATING_REG1, 22), 505 506 SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 507 BUS_CLK_GATING_REG2, 0), 508 SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 509 BUS_CLK_GATING_REG2, 1), 510 SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 511 BUS_CLK_GATING_REG2, 5), 512 SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 513 BUS_CLK_GATING_REG2, 8), 514 SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 515 BUS_CLK_GATING_REG2, 12), 516 SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 517 BUS_CLK_GATING_REG2, 13), 518 SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 519 BUS_CLK_GATING_REG2, 14), 520 521 SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 522 BUS_CLK_GATING_REG3, 0), 523 SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 524 BUS_CLK_GATING_REG3, 1), 525 SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 526 BUS_CLK_GATING_REG3, 2), 527 SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2", 528 BUS_CLK_GATING_REG3, 5), 529 SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 530 BUS_CLK_GATING_REG3, 16), 531 SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 532 BUS_CLK_GATING_REG3, 17), 533 SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 534 BUS_CLK_GATING_REG3, 18), 535 SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 536 BUS_CLK_GATING_REG3, 19), 537 SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 538 BUS_CLK_GATING_REG3, 20), 539 540 SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc", 541 USBPHY_CFG_REG, 8), 542 SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc", 543 USBPHY_CFG_REG, 9), 544 SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc", 545 USBPHY_CFG_REG, 10), 546 SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc", 547 USBPHY_CFG_REG, 11), 548 SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc", 549 USBPHY_CFG_REG, 16), 550 SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 551 USBPHY_CFG_REG, 17), 552 }; 553 554 static int 555 sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux) 556 { 557 struct fdt_attach_args * const faa = aux; 558 559 return of_match_compatible(faa->faa_phandle, compatible); 560 } 561 562 static void 563 sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux) 564 { 565 struct sunxi_ccu_softc * const sc = device_private(self); 566 struct fdt_attach_args * const faa = aux; 567 568 sc->sc_dev = self; 569 sc->sc_phandle = faa->faa_phandle; 570 sc->sc_bst = faa->faa_bst; 571 572 sc->sc_resets = sun50i_a64_ccu_resets; 573 sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets); 574 575 sc->sc_clks = sun50i_a64_ccu_clks; 576 sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks); 577 578 if (sunxi_ccu_attach(sc) != 0) 579 return; 580 581 aprint_naive("\n"); 582 aprint_normal(": A64 CCU\n"); 583 584 /* Set DE parent to PLL_DE */ 585 clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base); 586 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000); 587 588 sunxi_ccu_print(sc); 589 } 590
Indexes created Thu Oct 02 14:10:14 GMT 2025