sun50i_a64_ccu.c revision 1.16
1 /* $NetBSD: sun50i_a64_ccu.c,v 1.16 2019/11/22 19:46:38 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.16 2019/11/22 19:46:38 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_a64_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_VIDEO0_CTRL_REG 0x010 46 #define PLL_PERIPH0_CTRL_REG 0x028 47 #define PLL_PERIPH1_CTRL_REG 0x02c 48 #define PLL_VIDEO1_CTRL_REG 0x030 49 #define PLL_GPU_CTRL_REG 0x038 50 #define PLL_DE_CTRL_REG 0x048 51 #define AHB1_APB1_CFG_REG 0x054 52 #define APB2_CFG_REG 0x058 53 #define AHB2_CFG_REG 0x05c 54 #define BUS_CLK_GATING_REG0 0x060 55 #define BUS_CLK_GATING_REG1 0x064 56 #define BUS_CLK_GATING_REG2 0x068 57 #define BUS_CLK_GATING_REG3 0x06c 58 #define BUS_CLK_GATING_REG4 0x070 59 #define THS_CLK_REG 0x074 60 #define SDMMC0_CLK_REG 0x088 61 #define SDMMC1_CLK_REG 0x08c 62 #define SDMMC2_CLK_REG 0x090 63 #define SPI0_CLK_REG 0x0a0 64 #define SPI1_CLK_REG 0x0a4 65 #define I2SPCM0_CLK_REG 0x0b0 66 #define I2SPCM1_CLK_REG 0x0b4 67 #define I2SPCM2_CLK_REG 0x0b8 68 #define USBPHY_CFG_REG 0x0cc 69 #define DRAM_CFG_REG 0x0f4 70 #define MBUS_RST_REG 0x0fc 71 #define DE_CLK_REG 0x104 72 #define TCON1_CLK_REG 0x11c 73 #define AC_DIG_CLK_REG 0x140 74 #define HDMI_CLK_REG 0x150 75 #define HDMI_SLOW_CLK_REG 0x154 76 #define GPU_CLK_REG 0x1a0 77 #define BUS_SOFT_RST_REG0 0x2c0 78 #define BUS_SOFT_RST_REG1 0x2c4 79 #define BUS_SOFT_RST_REG2 0x2c8 80 #define BUS_SOFT_RST_REG3 0x2d0 81 #define BUS_SOFT_RST_REG4 0x2d8 82 83 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *); 84 static void sun50i_a64_ccu_attach(device_t, device_t, void *); 85 86 static const char * const compatible[] = { 87 "allwinner,sun50i-a64-ccu", 88 NULL 89 }; 90 91 CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc), 92 sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL); 93 94 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = { 95 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0), 96 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1), 97 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2), 98 99 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31), 100 101 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31), 102 103 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 104 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 105 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 106 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 107 SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 108 SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 109 SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 110 SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 111 SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 112 SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 113 SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 114 SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 115 SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 116 SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 117 SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 118 SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 119 SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 120 SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 121 122 SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 123 SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 124 SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 125 SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 126 SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 127 SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 128 SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 129 SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 130 SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 131 SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 132 SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 133 SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 134 135 SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0), 136 137 SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 138 SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 139 SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 140 SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 141 SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 142 SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 143 144 SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 145 SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 146 SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 147 SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5), 148 SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 149 SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 150 SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 151 SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 152 }; 153 154 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 155 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 156 static const char *apb1_parents[] = { "ahb1" }; 157 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 158 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 159 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL }; 160 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" }; 161 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" }; 162 static const char *i2s_parents[] = { "pll_audio_8x", "pll_audio_4x", "pll_audio_2x", "pll_audio" }; 163 static const char *spi_parents[] = { "hosc", "pll_periph0", "pll_periph1", NULL }; 164 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL }; 165 static const char *gpu_parents[] = { "pll_gpu" }; 166 167 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = { 168 { 60000000, 9, 0, 0, 2 }, 169 { 66000000, 10, 0, 0, 2 }, 170 { 72000000, 11, 0, 0, 2 }, 171 { 78000000, 12, 0, 0, 2 }, 172 { 84000000, 13, 0, 0, 2 }, 173 { 90000000, 14, 0, 0, 2 }, 174 { 96000000, 15, 0, 0, 2 }, 175 { 102000000, 16, 0, 0, 2 }, 176 { 108000000, 17, 0, 0, 2 }, 177 { 114000000, 18, 0, 0, 2 }, 178 { 120000000, 9, 0, 0, 1 }, 179 { 132000000, 10, 0, 0, 1 }, 180 { 144000000, 11, 0, 0, 1 }, 181 { 156000000, 12, 0, 0, 1 }, 182 { 168000000, 13, 0, 0, 1 }, 183 { 180000000, 14, 0, 0, 1 }, 184 { 192000000, 15, 0, 0, 1 }, 185 { 204000000, 16, 0, 0, 1 }, 186 { 216000000, 17, 0, 0, 1 }, 187 { 228000000, 18, 0, 0, 1 }, 188 { 240000000, 9, 0, 0, 0 }, 189 { 264000000, 10, 0, 0, 0 }, 190 { 288000000, 11, 0, 0, 0 }, 191 { 312000000, 12, 0, 0, 0 }, 192 { 336000000, 13, 0, 0, 0 }, 193 { 360000000, 14, 0, 0, 0 }, 194 { 384000000, 15, 0, 0, 0 }, 195 { 408000000, 16, 0, 0, 0 }, 196 { 432000000, 17, 0, 0, 0 }, 197 { 456000000, 18, 0, 0, 0 }, 198 { 480000000, 19, 0, 0, 0 }, 199 { 504000000, 20, 0, 0, 0 }, 200 { 528000000, 21, 0, 0, 0 }, 201 { 552000000, 22, 0, 0, 0 }, 202 { 576000000, 23, 0, 0, 0 }, 203 { 600000000, 24, 0, 0, 0 }, 204 { 624000000, 25, 0, 0, 0 }, 205 { 648000000, 26, 0, 0, 0 }, 206 { 672000000, 27, 0, 0, 0 }, 207 { 696000000, 28, 0, 0, 0 }, 208 { 720000000, 29, 0, 0, 0 }, 209 { 768000000, 15, 1, 0, 0 }, 210 { 792000000, 10, 2, 0, 0 }, 211 { 816000000, 16, 1, 0, 0 }, 212 { 864000000, 17, 1, 0, 0 }, 213 { 912000000, 18, 1, 0, 0 }, 214 { 936000000, 12, 2, 0, 0 }, 215 { 960000000, 19, 1, 0, 0 }, 216 { 1008000000, 20, 1, 0, 0 }, 217 { 1056000000, 21, 1, 0, 0 }, 218 { 1080000000, 14, 2, 0, 0 }, 219 { 1104000000, 22, 1, 0, 0 }, 220 { 1152000000, 23, 1, 0, 0 }, 221 { 1200000000, 24, 1, 0, 0 }, 222 { 1224000000, 16, 2, 0, 0 }, 223 { 1248000000, 25, 1, 0, 0 }, 224 { 1296000000, 26, 1, 0, 0 }, 225 { 1344000000, 27, 1, 0, 0 }, 226 { 1368000000, 18, 2, 0, 0 }, 227 { 1440000000, 19, 2, 0, 0 }, 228 { 1512000000, 20, 2, 0, 0 }, 229 { 1536000000, 15, 3, 0, 0 }, 230 { 1584000000, 21, 2, 0, 0 }, 231 { 1632000000, 16, 3, 0, 0 }, 232 { 1656000000, 22, 2, 0, 0 }, 233 { 1728000000, 23, 2, 0, 0 }, 234 { 1800000000, 24, 2, 0, 0 }, 235 { 1872000000, 25, 2, 0, 0 }, 236 { 0 } 237 }; 238 239 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_ac_dig_table[] = { 240 { 24576000, 0x55, 0, 0x14, 0x3 }, 241 { 0 } 242 }; 243 244 static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = { 245 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_CPUX, "pll_cpux", "hosc", 246 PLL_CPUX_CTRL_REG, /* reg */ 247 __BITS(12,8), /* n */ 248 __BITS(5,4), /* k */ 249 __BITS(1,0), /* m */ 250 __BITS(17,16), /* p */ 251 __BIT(31), /* enable */ 252 __BIT(28), /* lock */ 253 sun50i_a64_cpux_table, /* table */ 254 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 255 256 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 257 PLL_PERIPH0_CTRL_REG, /* reg */ 258 __BITS(12,8), /* n */ 259 __BITS(5,4), /* k */ 260 0, /* m */ 261 __BITS(17,16), /* p */ 262 __BIT(31), /* enable */ 263 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 264 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2), 265 266 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH1, "pll_periph1", "hosc", 267 PLL_PERIPH1_CTRL_REG, /* reg */ 268 __BITS(12,8), /* n */ 269 __BITS(5,4), /* k */ 270 0, /* m */ 271 __BITS(17,16), /* p */ 272 __BIT(31), /* enable */ 273 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 274 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH1_2X, "pll_periph1_2x", "pll_periph1", 1, 2), 275 276 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_AUDIO_BASE, "pll_audio_base", "hosc", 277 PLL_AUDIO_CTRL_REG, /* reg */ 278 __BITS(14,8), /* n */ 279 0, /* k */ 280 __BITS(4,0), /* m */ 281 __BITS(19,16), /* p */ 282 __BIT(31), /* enable */ 283 __BIT(28), /* lock */ 284 sun50i_a64_ac_dig_table, /* table */ 285 0), 286 287 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO, "pll_audio", "pll_audio_base", 1, 1), 288 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_2X, "pll_audio_2x", "pll_audio_base", 1, 2), 289 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_4X, "pll_audio_4x", "pll_audio_base", 1, 4), 290 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_8X, "pll_audio_8x", "pll_audio_base", 1, 8), 291 292 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO0, "pll_video0", "hosc", 293 PLL_VIDEO0_CTRL_REG, /* reg */ 294 __BITS(14,8), /* m */ 295 16, /* m_min */ 296 50, /* m_max */ 297 __BIT(24), /* div_en */ 298 __BIT(25), /* frac_sel */ 299 270000000, 297000000, /* frac values */ 300 __BITS(3,0), /* prediv */ 301 4, /* prediv_val */ 302 __BIT(31), /* enable */ 303 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 304 305 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_VIDEO0_2X, "pll_video0_2x", "pll_video0", 1, 2), 306 307 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO1, "pll_video1", "hosc", 308 PLL_VIDEO1_CTRL_REG, /* reg */ 309 __BITS(14,8), /* m */ 310 16, /* m_min */ 311 50, /* m_max */ 312 __BIT(24), /* div_en */ 313 __BIT(25), /* frac_sel */ 314 270000000, 297000000, /* frac values */ 315 __BITS(3,0), /* prediv */ 316 4, /* prediv_val */ 317 __BIT(31), /* enable */ 318 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 319 320 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_DE, "pll_de", "hosc", 321 PLL_DE_CTRL_REG, /* reg */ 322 __BITS(14,8), /* m */ 323 16, /* m_min */ 324 50, /* m_max */ 325 __BIT(24), /* div_en */ 326 __BIT(25), /* frac_sel */ 327 270000000, 297000000, /* frac values */ 328 __BITS(3,0), /* prediv */ 329 2, /* prediv_val */ 330 __BIT(31), /* enable */ 331 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 332 333 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_GPU, "pll_gpu", "hosc", 334 PLL_GPU_CTRL_REG, /* reg */ 335 __BITS(14,8), /* m */ 336 1, /* m_min */ 337 128, /* m_max */ 338 __BIT(24), /* div_en */ 339 __BIT(25), /* frac_sel */ 340 270000000, 297000000, /* frac values */ 341 __BITS(3,0), /* prediv */ 342 4, /* prediv_val */ 343 __BIT(31), /* enable */ 344 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 345 346 SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents, 347 AHB1_APB1_CFG_REG, /* reg */ 348 __BITS(7,6), /* prediv */ 349 __BIT(3), /* prediv_sel */ 350 __BITS(5,4), /* div */ 351 __BITS(13,12), /* sel */ 352 SUNXI_CCU_PREDIV_POWER_OF_TWO), 353 354 SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents, 355 AHB2_CFG_REG, /* reg */ 356 0, /* prediv */ 357 __BIT(1), /* prediv_sel */ 358 0, /* div */ 359 __BITS(1,0), /* sel */ 360 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 361 362 SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents, 363 AHB1_APB1_CFG_REG, /* reg */ 364 __BITS(9,8), /* div */ 365 0, /* sel */ 366 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 367 368 SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents, 369 APB2_CFG_REG, /* reg */ 370 __BITS(17,16), /* n */ 371 __BITS(4,0), /* m */ 372 __BITS(25,24), /* sel */ 373 0, /* enable */ 374 SUNXI_CCU_NM_POWER_OF_TWO), 375 376 SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mmc_parents, 377 SDMMC0_CLK_REG, /* reg */ 378 __BITS(17,16), /* n */ 379 __BITS(3,0), /* m */ 380 __BITS(25,24), /* sel */ 381 __BIT(31), /* enable */ 382 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 383 SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mmc_parents, 384 SDMMC1_CLK_REG, /* reg */ 385 __BITS(17,16), /* n */ 386 __BITS(3,0), /* m */ 387 __BITS(25,24), /* sel */ 388 __BIT(31), /* enable */ 389 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 390 SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mmc_parents, 391 SDMMC2_CLK_REG, /* reg */ 392 __BITS(17,16), /* n */ 393 __BITS(3,0), /* m */ 394 __BITS(25,24), /* sel */ 395 __BIT(31), /* enable */ 396 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 397 398 SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents, 399 THS_CLK_REG, /* reg */ 400 __BITS(1,0), /* div */ 401 __BITS(25,24), /* sel */ 402 __BIT(31), /* enable */ 403 SUNXI_CCU_DIV_TIMES_TWO), 404 405 SUNXI_CCU_DIV_GATE(A64_CLK_DE, "de", de_parents, 406 DE_CLK_REG, /* reg */ 407 __BITS(3,0), /* div */ 408 __BITS(26,24), /* sel */ 409 __BIT(31), /* enable */ 410 0), 411 412 SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 413 AC_DIG_CLK_REG, 31), 414 SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x", 415 AC_DIG_CLK_REG, 30), 416 417 SUNXI_CCU_DIV_GATE(A64_CLK_HDMI, "hdmi", hdmi_parents, 418 HDMI_CLK_REG, /* reg */ 419 __BITS(3,0), /* div */ 420 __BITS(25,24), /* sel */ 421 __BIT(31), /* enable */ 422 0), 423 424 SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc", 425 HDMI_SLOW_CLK_REG, 31), 426 427 SUNXI_CCU_DIV_GATE(A64_CLK_I2S0, "i2s0", i2s_parents, 428 I2SPCM0_CLK_REG, /* reg */ 429 0, /* div */ 430 __BITS(17,16), /* sel */ 431 __BIT(31), /* enable */ 432 0), 433 SUNXI_CCU_DIV_GATE(A64_CLK_I2S1, "i2s1", i2s_parents, 434 I2SPCM1_CLK_REG, /* reg */ 435 0, /* div */ 436 __BITS(17,16), /* sel */ 437 __BIT(31), /* enable */ 438 0), 439 SUNXI_CCU_DIV_GATE(A64_CLK_I2S2, "i2s2", i2s_parents, 440 I2SPCM2_CLK_REG, /* reg */ 441 0, /* div */ 442 __BITS(17,16), /* sel */ 443 __BIT(31), /* enable */ 444 0), 445 446 SUNXI_CCU_NM(A64_CLK_SPI0, "spi0", spi_parents, 447 SPI0_CLK_REG, /* reg */ 448 __BITS(17,16), /* n */ 449 __BITS(3,0), /* m */ 450 __BITS(25,24), /* sel */ 451 __BIT(31), /* enable */ 452 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 453 454 SUNXI_CCU_NM(A64_CLK_SPI1, "spi1", spi_parents, 455 SPI1_CLK_REG, /* reg */ 456 __BITS(17,16), /* n */ 457 __BITS(3,0), /* m */ 458 __BITS(25,24), /* sel */ 459 __BIT(31), /* enable */ 460 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 461 462 SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents, 463 TCON1_CLK_REG, /* reg */ 464 __BITS(3,0), /* div */ 465 __BITS(25,24), /* sel */ 466 __BIT(31), /* enable */ 467 0), 468 469 SUNXI_CCU_DIV_GATE(A64_CLK_GPU, "gpu", gpu_parents, 470 GPU_CLK_REG, /* reg */ 471 __BITS(2,0), /* div */ 472 0, /* sel */ 473 __BIT(31), /* enable */ 474 0), 475 476 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 477 BUS_CLK_GATING_REG0, 1), 478 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 479 BUS_CLK_GATING_REG0, 5), 480 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 481 BUS_CLK_GATING_REG0, 6), 482 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 483 BUS_CLK_GATING_REG0, 8), 484 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 485 BUS_CLK_GATING_REG0, 9), 486 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 487 BUS_CLK_GATING_REG0, 10), 488 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 489 BUS_CLK_GATING_REG0, 13), 490 SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 491 BUS_CLK_GATING_REG0, 14), 492 SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 493 BUS_CLK_GATING_REG0, 17), 494 SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 495 BUS_CLK_GATING_REG0, 18), 496 SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 497 BUS_CLK_GATING_REG0, 19), 498 SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 499 BUS_CLK_GATING_REG0, 20), 500 SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 501 BUS_CLK_GATING_REG0, 21), 502 SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 503 BUS_CLK_GATING_REG0, 23), 504 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 505 BUS_CLK_GATING_REG0, 24), 506 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 507 BUS_CLK_GATING_REG0, 25), 508 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 509 BUS_CLK_GATING_REG0, 28), 510 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 511 BUS_CLK_GATING_REG0, 29), 512 513 SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 514 BUS_CLK_GATING_REG1, 0), 515 SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 516 BUS_CLK_GATING_REG1, 3), 517 SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 518 BUS_CLK_GATING_REG1, 4), 519 SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 520 BUS_CLK_GATING_REG1, 5), 521 SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 522 BUS_CLK_GATING_REG1, 8), 523 SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 524 BUS_CLK_GATING_REG1, 11), 525 SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 526 BUS_CLK_GATING_REG1, 12), 527 SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 528 BUS_CLK_GATING_REG1, 20), 529 SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 530 BUS_CLK_GATING_REG1, 21), 531 SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 532 BUS_CLK_GATING_REG1, 22), 533 534 SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 535 BUS_CLK_GATING_REG2, 0), 536 SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 537 BUS_CLK_GATING_REG2, 1), 538 SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 539 BUS_CLK_GATING_REG2, 5), 540 SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 541 BUS_CLK_GATING_REG2, 8), 542 SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 543 BUS_CLK_GATING_REG2, 12), 544 SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 545 BUS_CLK_GATING_REG2, 13), 546 SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 547 BUS_CLK_GATING_REG2, 14), 548 549 SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 550 BUS_CLK_GATING_REG3, 0), 551 SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 552 BUS_CLK_GATING_REG3, 1), 553 SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 554 BUS_CLK_GATING_REG3, 2), 555 SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2", 556 BUS_CLK_GATING_REG3, 5), 557 SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 558 BUS_CLK_GATING_REG3, 16), 559 SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 560 BUS_CLK_GATING_REG3, 17), 561 SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 562 BUS_CLK_GATING_REG3, 18), 563 SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 564 BUS_CLK_GATING_REG3, 19), 565 SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 566 BUS_CLK_GATING_REG3, 20), 567 568 SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc", 569 USBPHY_CFG_REG, 8), 570 SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc", 571 USBPHY_CFG_REG, 9), 572 SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc", 573 USBPHY_CFG_REG, 10), 574 SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc", 575 USBPHY_CFG_REG, 11), 576 SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc", 577 USBPHY_CFG_REG, 16), 578 SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 579 USBPHY_CFG_REG, 17), 580 }; 581 582 static int 583 sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux) 584 { 585 struct fdt_attach_args * const faa = aux; 586 587 return of_match_compatible(faa->faa_phandle, compatible); 588 } 589 590 static void 591 sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux) 592 { 593 struct sunxi_ccu_softc * const sc = device_private(self); 594 struct fdt_attach_args * const faa = aux; 595 596 sc->sc_dev = self; 597 sc->sc_phandle = faa->faa_phandle; 598 sc->sc_bst = faa->faa_bst; 599 600 sc->sc_resets = sun50i_a64_ccu_resets; 601 sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets); 602 603 sc->sc_clks = sun50i_a64_ccu_clks; 604 sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks); 605 606 if (sunxi_ccu_attach(sc) != 0) 607 return; 608 609 aprint_naive("\n"); 610 aprint_normal(": A64 CCU\n"); 611 612 /* Set DE parent to PLL_DE */ 613 clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base); 614 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000); 615 616 sunxi_ccu_print(sc); 617 } 618
Indexes created Thu Oct 02 14:10:14 GMT 2025