sun50i_a64_ccu.c revision 1.19
1 /* $NetBSD: sun50i_a64_ccu.c,v 1.19 2019/11/23 22:46:53 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.19 2019/11/23 22:46:53 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_a64_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_VIDEO0_CTRL_REG 0x010 46 #define PLL_PERIPH0_CTRL_REG 0x028 47 #define PLL_PERIPH1_CTRL_REG 0x02c 48 #define PLL_VIDEO1_CTRL_REG 0x030 49 #define PLL_GPU_CTRL_REG 0x038 50 #define PLL_DE_CTRL_REG 0x048 51 #define AHB1_APB1_CFG_REG 0x054 52 #define APB2_CFG_REG 0x058 53 #define AHB2_CFG_REG 0x05c 54 #define BUS_CLK_GATING_REG0 0x060 55 #define BUS_CLK_GATING_REG1 0x064 56 #define BUS_CLK_GATING_REG2 0x068 57 #define BUS_CLK_GATING_REG3 0x06c 58 #define BUS_CLK_GATING_REG4 0x070 59 #define THS_CLK_REG 0x074 60 #define SDMMC0_CLK_REG 0x088 61 #define SDMMC1_CLK_REG 0x08c 62 #define SDMMC2_CLK_REG 0x090 63 #define SPI0_CLK_REG 0x0a0 64 #define SPI1_CLK_REG 0x0a4 65 #define I2SPCM0_CLK_REG 0x0b0 66 #define I2SPCM1_CLK_REG 0x0b4 67 #define I2SPCM2_CLK_REG 0x0b8 68 #define USBPHY_CFG_REG 0x0cc 69 #define DRAM_CFG_REG 0x0f4 70 #define MBUS_RST_REG 0x0fc 71 #define DE_CLK_REG 0x104 72 #define TCON0_CLK_REG 0x118 73 #define TCON1_CLK_REG 0x11c 74 #define AC_DIG_CLK_REG 0x140 75 #define HDMI_CLK_REG 0x150 76 #define HDMI_SLOW_CLK_REG 0x154 77 #define GPU_CLK_REG 0x1a0 78 #define BUS_SOFT_RST_REG0 0x2c0 79 #define BUS_SOFT_RST_REG1 0x2c4 80 #define BUS_SOFT_RST_REG2 0x2c8 81 #define BUS_SOFT_RST_REG3 0x2d0 82 #define BUS_SOFT_RST_REG4 0x2d8 83 84 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *); 85 static void sun50i_a64_ccu_attach(device_t, device_t, void *); 86 87 static const char * const compatible[] = { 88 "allwinner,sun50i-a64-ccu", 89 NULL 90 }; 91 92 CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc), 93 sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL); 94 95 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = { 96 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0), 97 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1), 98 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2), 99 100 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31), 101 102 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31), 103 104 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 105 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 106 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 107 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 108 SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 109 SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 110 SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 111 SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 112 SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 113 SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 114 SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 115 SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 116 SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 117 SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 118 SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 119 SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 120 SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 121 SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 122 123 SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 124 SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 125 SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 126 SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 127 SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 128 SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 129 SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 130 SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 131 SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 132 SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 133 SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 134 SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 135 136 SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0), 137 138 SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 139 SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 140 SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 141 SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 142 SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 143 SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 144 145 SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 146 SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 147 SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 148 SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5), 149 SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 150 SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 151 SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 152 SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 153 }; 154 155 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 156 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 157 static const char *apb1_parents[] = { "ahb1" }; 158 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 159 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 160 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL }; 161 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" }; 162 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" }; 163 static const char *i2s_parents[] = { "pll_audio_8x", "pll_audio_4x", "pll_audio_2x", "pll_audio" }; 164 static const char *spi_parents[] = { "hosc", "pll_periph0", "pll_periph1", NULL }; 165 static const char *tcon0_parents[] = { "pll_mipi", NULL, "pll_video0_2x", NULL }; 166 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL }; 167 static const char *gpu_parents[] = { "pll_gpu" }; 168 169 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = { 170 { 60000000, 9, 0, 0, 2 }, 171 { 66000000, 10, 0, 0, 2 }, 172 { 72000000, 11, 0, 0, 2 }, 173 { 78000000, 12, 0, 0, 2 }, 174 { 84000000, 13, 0, 0, 2 }, 175 { 90000000, 14, 0, 0, 2 }, 176 { 96000000, 15, 0, 0, 2 }, 177 { 102000000, 16, 0, 0, 2 }, 178 { 108000000, 17, 0, 0, 2 }, 179 { 114000000, 18, 0, 0, 2 }, 180 { 120000000, 9, 0, 0, 1 }, 181 { 132000000, 10, 0, 0, 1 }, 182 { 144000000, 11, 0, 0, 1 }, 183 { 156000000, 12, 0, 0, 1 }, 184 { 168000000, 13, 0, 0, 1 }, 185 { 180000000, 14, 0, 0, 1 }, 186 { 192000000, 15, 0, 0, 1 }, 187 { 204000000, 16, 0, 0, 1 }, 188 { 216000000, 17, 0, 0, 1 }, 189 { 228000000, 18, 0, 0, 1 }, 190 { 240000000, 9, 0, 0, 0 }, 191 { 264000000, 10, 0, 0, 0 }, 192 { 288000000, 11, 0, 0, 0 }, 193 { 312000000, 12, 0, 0, 0 }, 194 { 336000000, 13, 0, 0, 0 }, 195 { 360000000, 14, 0, 0, 0 }, 196 { 384000000, 15, 0, 0, 0 }, 197 { 408000000, 16, 0, 0, 0 }, 198 { 432000000, 17, 0, 0, 0 }, 199 { 456000000, 18, 0, 0, 0 }, 200 { 480000000, 19, 0, 0, 0 }, 201 { 504000000, 20, 0, 0, 0 }, 202 { 528000000, 21, 0, 0, 0 }, 203 { 552000000, 22, 0, 0, 0 }, 204 { 576000000, 23, 0, 0, 0 }, 205 { 600000000, 24, 0, 0, 0 }, 206 { 624000000, 25, 0, 0, 0 }, 207 { 648000000, 26, 0, 0, 0 }, 208 { 672000000, 27, 0, 0, 0 }, 209 { 696000000, 28, 0, 0, 0 }, 210 { 720000000, 29, 0, 0, 0 }, 211 { 768000000, 15, 1, 0, 0 }, 212 { 792000000, 10, 2, 0, 0 }, 213 { 816000000, 16, 1, 0, 0 }, 214 { 864000000, 17, 1, 0, 0 }, 215 { 912000000, 18, 1, 0, 0 }, 216 { 936000000, 12, 2, 0, 0 }, 217 { 960000000, 19, 1, 0, 0 }, 218 { 1008000000, 20, 1, 0, 0 }, 219 { 1056000000, 21, 1, 0, 0 }, 220 { 1080000000, 14, 2, 0, 0 }, 221 { 1104000000, 22, 1, 0, 0 }, 222 { 1152000000, 23, 1, 0, 0 }, 223 { 1200000000, 24, 1, 0, 0 }, 224 { 1224000000, 16, 2, 0, 0 }, 225 { 1248000000, 25, 1, 0, 0 }, 226 { 1296000000, 26, 1, 0, 0 }, 227 { 1344000000, 27, 1, 0, 0 }, 228 { 1368000000, 18, 2, 0, 0 }, 229 { 1440000000, 19, 2, 0, 0 }, 230 { 1512000000, 20, 2, 0, 0 }, 231 { 1536000000, 15, 3, 0, 0 }, 232 { 1584000000, 21, 2, 0, 0 }, 233 { 1632000000, 16, 3, 0, 0 }, 234 { 1656000000, 22, 2, 0, 0 }, 235 { 1728000000, 23, 2, 0, 0 }, 236 { 1800000000, 24, 2, 0, 0 }, 237 { 1872000000, 25, 2, 0, 0 }, 238 { 0 } 239 }; 240 241 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_ac_dig_table[] = { 242 { 24576000, 0x55, 0, 0x14, 0x3 }, 243 { 0 } 244 }; 245 246 static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = { 247 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_CPUX, "pll_cpux", "hosc", 248 PLL_CPUX_CTRL_REG, /* reg */ 249 __BITS(12,8), /* n */ 250 __BITS(5,4), /* k */ 251 __BITS(1,0), /* m */ 252 __BITS(17,16), /* p */ 253 __BIT(31), /* enable */ 254 __BIT(28), /* lock */ 255 sun50i_a64_cpux_table, /* table */ 256 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 257 258 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 259 PLL_PERIPH0_CTRL_REG, /* reg */ 260 __BITS(12,8), /* n */ 261 __BITS(5,4), /* k */ 262 0, /* m */ 263 __BITS(17,16), /* p */ 264 __BIT(31), /* enable */ 265 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 266 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2), 267 268 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH1, "pll_periph1", "hosc", 269 PLL_PERIPH1_CTRL_REG, /* reg */ 270 __BITS(12,8), /* n */ 271 __BITS(5,4), /* k */ 272 0, /* m */ 273 __BITS(17,16), /* p */ 274 __BIT(31), /* enable */ 275 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 276 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH1_2X, "pll_periph1_2x", "pll_periph1", 1, 2), 277 278 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_AUDIO_BASE, "pll_audio_base", "hosc", 279 PLL_AUDIO_CTRL_REG, /* reg */ 280 __BITS(14,8), /* n */ 281 0, /* k */ 282 __BITS(4,0), /* m */ 283 __BITS(19,16), /* p */ 284 __BIT(31), /* enable */ 285 __BIT(28), /* lock */ 286 sun50i_a64_ac_dig_table, /* table */ 287 0), 288 289 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO, "pll_audio", "pll_audio_base", 1, 1), 290 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_2X, "pll_audio_2x", "pll_audio_base", 1, 2), 291 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_4X, "pll_audio_4x", "pll_audio_base", 1, 4), 292 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_8X, "pll_audio_8x", "pll_audio_base", 1, 8), 293 294 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO0, "pll_video0", "hosc", 295 PLL_VIDEO0_CTRL_REG, /* reg */ 296 __BITS(14,8), /* m */ 297 16, /* m_min */ 298 50, /* m_max */ 299 __BIT(24), /* div_en */ 300 __BIT(25), /* frac_sel */ 301 270000000, 297000000, /* frac values */ 302 __BITS(3,0), /* prediv */ 303 4, /* prediv_val */ 304 __BIT(31), /* enable */ 305 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 306 307 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_VIDEO0_2X, "pll_video0_2x", "pll_video0", 1, 2), 308 309 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO1, "pll_video1", "hosc", 310 PLL_VIDEO1_CTRL_REG, /* reg */ 311 __BITS(14,8), /* m */ 312 16, /* m_min */ 313 50, /* m_max */ 314 __BIT(24), /* div_en */ 315 __BIT(25), /* frac_sel */ 316 270000000, 297000000, /* frac values */ 317 __BITS(3,0), /* prediv */ 318 4, /* prediv_val */ 319 __BIT(31), /* enable */ 320 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 321 322 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_DE, "pll_de", "hosc", 323 PLL_DE_CTRL_REG, /* reg */ 324 __BITS(14,8), /* m */ 325 16, /* m_min */ 326 50, /* m_max */ 327 __BIT(24), /* div_en */ 328 __BIT(25), /* frac_sel */ 329 270000000, 297000000, /* frac values */ 330 __BITS(3,0), /* prediv */ 331 2, /* prediv_val */ 332 __BIT(31), /* enable */ 333 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 334 335 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_GPU, "pll_gpu", "hosc", 336 PLL_GPU_CTRL_REG, /* reg */ 337 __BITS(14,8), /* m */ 338 1, /* m_min */ 339 128, /* m_max */ 340 __BIT(24), /* div_en */ 341 __BIT(25), /* frac_sel */ 342 270000000, 297000000, /* frac values */ 343 __BITS(3,0), /* prediv */ 344 4, /* prediv_val */ 345 __BIT(31), /* enable */ 346 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 347 348 SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents, 349 AHB1_APB1_CFG_REG, /* reg */ 350 __BITS(7,6), /* prediv */ 351 __BIT(3), /* prediv_sel */ 352 __BITS(5,4), /* div */ 353 __BITS(13,12), /* sel */ 354 SUNXI_CCU_PREDIV_POWER_OF_TWO), 355 356 SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents, 357 AHB2_CFG_REG, /* reg */ 358 0, /* prediv */ 359 __BIT(1), /* prediv_sel */ 360 0, /* div */ 361 __BITS(1,0), /* sel */ 362 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 363 364 SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents, 365 AHB1_APB1_CFG_REG, /* reg */ 366 __BITS(9,8), /* div */ 367 0, /* sel */ 368 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 369 370 SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents, 371 APB2_CFG_REG, /* reg */ 372 __BITS(17,16), /* n */ 373 __BITS(4,0), /* m */ 374 __BITS(25,24), /* sel */ 375 0, /* enable */ 376 SUNXI_CCU_NM_POWER_OF_TWO), 377 378 SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mmc_parents, 379 SDMMC0_CLK_REG, /* reg */ 380 __BITS(17,16), /* n */ 381 __BITS(3,0), /* m */ 382 __BITS(25,24), /* sel */ 383 __BIT(31), /* enable */ 384 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 385 SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mmc_parents, 386 SDMMC1_CLK_REG, /* reg */ 387 __BITS(17,16), /* n */ 388 __BITS(3,0), /* m */ 389 __BITS(25,24), /* sel */ 390 __BIT(31), /* enable */ 391 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 392 SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mmc_parents, 393 SDMMC2_CLK_REG, /* reg */ 394 __BITS(17,16), /* n */ 395 __BITS(3,0), /* m */ 396 __BITS(25,24), /* sel */ 397 __BIT(31), /* enable */ 398 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 399 400 SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents, 401 THS_CLK_REG, /* reg */ 402 __BITS(1,0), /* div */ 403 __BITS(25,24), /* sel */ 404 __BIT(31), /* enable */ 405 SUNXI_CCU_DIV_TIMES_TWO), 406 407 SUNXI_CCU_DIV_GATE(A64_CLK_DE, "de", de_parents, 408 DE_CLK_REG, /* reg */ 409 __BITS(3,0), /* div */ 410 __BITS(26,24), /* sel */ 411 __BIT(31), /* enable */ 412 0), 413 414 SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 415 AC_DIG_CLK_REG, 31), 416 SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x", 417 AC_DIG_CLK_REG, 30), 418 419 SUNXI_CCU_DIV_GATE(A64_CLK_HDMI, "hdmi", hdmi_parents, 420 HDMI_CLK_REG, /* reg */ 421 __BITS(3,0), /* div */ 422 __BITS(25,24), /* sel */ 423 __BIT(31), /* enable */ 424 0), 425 426 SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc", 427 HDMI_SLOW_CLK_REG, 31), 428 429 SUNXI_CCU_DIV_GATE(A64_CLK_I2S0, "i2s0", i2s_parents, 430 I2SPCM0_CLK_REG, /* reg */ 431 0, /* div */ 432 __BITS(17,16), /* sel */ 433 __BIT(31), /* enable */ 434 0), 435 SUNXI_CCU_DIV_GATE(A64_CLK_I2S1, "i2s1", i2s_parents, 436 I2SPCM1_CLK_REG, /* reg */ 437 0, /* div */ 438 __BITS(17,16), /* sel */ 439 __BIT(31), /* enable */ 440 0), 441 SUNXI_CCU_DIV_GATE(A64_CLK_I2S2, "i2s2", i2s_parents, 442 I2SPCM2_CLK_REG, /* reg */ 443 0, /* div */ 444 __BITS(17,16), /* sel */ 445 __BIT(31), /* enable */ 446 0), 447 448 SUNXI_CCU_NM(A64_CLK_SPI0, "spi0", spi_parents, 449 SPI0_CLK_REG, /* reg */ 450 __BITS(17,16), /* n */ 451 __BITS(3,0), /* m */ 452 __BITS(25,24), /* sel */ 453 __BIT(31), /* enable */ 454 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 455 456 SUNXI_CCU_NM(A64_CLK_SPI1, "spi1", spi_parents, 457 SPI1_CLK_REG, /* reg */ 458 __BITS(17,16), /* n */ 459 __BITS(3,0), /* m */ 460 __BITS(25,24), /* sel */ 461 __BIT(31), /* enable */ 462 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 463 464 SUNXI_CCU_DIV_GATE(A64_CLK_TCON0, "tcon0", tcon0_parents, 465 TCON0_CLK_REG, /* reg */ 466 0, /* div */ 467 __BITS(26,24), /* sel */ 468 __BIT(31), /* enable */ 469 0), 470 471 SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents, 472 TCON1_CLK_REG, /* reg */ 473 __BITS(3,0), /* div */ 474 __BITS(25,24), /* sel */ 475 __BIT(31), /* enable */ 476 0), 477 478 SUNXI_CCU_DIV_GATE(A64_CLK_GPU, "gpu", gpu_parents, 479 GPU_CLK_REG, /* reg */ 480 __BITS(2,0), /* div */ 481 0, /* sel */ 482 __BIT(31), /* enable */ 483 0), 484 485 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 486 BUS_CLK_GATING_REG0, 1), 487 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 488 BUS_CLK_GATING_REG0, 5), 489 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 490 BUS_CLK_GATING_REG0, 6), 491 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 492 BUS_CLK_GATING_REG0, 8), 493 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 494 BUS_CLK_GATING_REG0, 9), 495 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 496 BUS_CLK_GATING_REG0, 10), 497 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 498 BUS_CLK_GATING_REG0, 13), 499 SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 500 BUS_CLK_GATING_REG0, 14), 501 SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 502 BUS_CLK_GATING_REG0, 17), 503 SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 504 BUS_CLK_GATING_REG0, 18), 505 SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 506 BUS_CLK_GATING_REG0, 19), 507 SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 508 BUS_CLK_GATING_REG0, 20), 509 SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 510 BUS_CLK_GATING_REG0, 21), 511 SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 512 BUS_CLK_GATING_REG0, 23), 513 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 514 BUS_CLK_GATING_REG0, 24), 515 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 516 BUS_CLK_GATING_REG0, 25), 517 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 518 BUS_CLK_GATING_REG0, 28), 519 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 520 BUS_CLK_GATING_REG0, 29), 521 522 SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 523 BUS_CLK_GATING_REG1, 0), 524 SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 525 BUS_CLK_GATING_REG1, 3), 526 SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 527 BUS_CLK_GATING_REG1, 4), 528 SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 529 BUS_CLK_GATING_REG1, 5), 530 SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 531 BUS_CLK_GATING_REG1, 8), 532 SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 533 BUS_CLK_GATING_REG1, 11), 534 SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 535 BUS_CLK_GATING_REG1, 12), 536 SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 537 BUS_CLK_GATING_REG1, 20), 538 SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 539 BUS_CLK_GATING_REG1, 21), 540 SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 541 BUS_CLK_GATING_REG1, 22), 542 543 SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 544 BUS_CLK_GATING_REG2, 0), 545 SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 546 BUS_CLK_GATING_REG2, 1), 547 SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 548 BUS_CLK_GATING_REG2, 5), 549 SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 550 BUS_CLK_GATING_REG2, 8), 551 SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 552 BUS_CLK_GATING_REG2, 12), 553 SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 554 BUS_CLK_GATING_REG2, 13), 555 SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 556 BUS_CLK_GATING_REG2, 14), 557 558 SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 559 BUS_CLK_GATING_REG3, 0), 560 SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 561 BUS_CLK_GATING_REG3, 1), 562 SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 563 BUS_CLK_GATING_REG3, 2), 564 SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2", 565 BUS_CLK_GATING_REG3, 5), 566 SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 567 BUS_CLK_GATING_REG3, 16), 568 SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 569 BUS_CLK_GATING_REG3, 17), 570 SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 571 BUS_CLK_GATING_REG3, 18), 572 SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 573 BUS_CLK_GATING_REG3, 19), 574 SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 575 BUS_CLK_GATING_REG3, 20), 576 577 SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc", 578 USBPHY_CFG_REG, 8), 579 SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc", 580 USBPHY_CFG_REG, 9), 581 SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc", 582 USBPHY_CFG_REG, 10), 583 SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc", 584 USBPHY_CFG_REG, 11), 585 SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc", 586 USBPHY_CFG_REG, 16), 587 SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 588 USBPHY_CFG_REG, 17), 589 }; 590 591 static int 592 sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux) 593 { 594 struct fdt_attach_args * const faa = aux; 595 596 return of_match_compatible(faa->faa_phandle, compatible); 597 } 598 599 static void 600 sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux) 601 { 602 struct sunxi_ccu_softc * const sc = device_private(self); 603 struct fdt_attach_args * const faa = aux; 604 605 sc->sc_dev = self; 606 sc->sc_phandle = faa->faa_phandle; 607 sc->sc_bst = faa->faa_bst; 608 609 sc->sc_resets = sun50i_a64_ccu_resets; 610 sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets); 611 612 sc->sc_clks = sun50i_a64_ccu_clks; 613 sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks); 614 615 if (sunxi_ccu_attach(sc) != 0) 616 return; 617 618 aprint_naive("\n"); 619 aprint_normal(": A64 CCU\n"); 620 621 /* Set DE parent to PLL_DE */ 622 clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base); 623 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000); 624 625 /* Set video PLLs to 297 MHz */ 626 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO0].base, 297000000); 627 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO1].base, 297000000); 628 629 /* Set TCON1 parent to PLL_VIDEO1(1X) */ 630 clk_set_parent(&sc->sc_clks[A64_CLK_TCON1].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base); 631 632 /* Set HDMI parent to PLL_VIDEO1(1X) */ 633 clk_set_parent(&sc->sc_clks[A64_CLK_HDMI].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base); 634 635 sunxi_ccu_print(sc); 636 } 637
Indexes created Thu Oct 23 22:10:10 GMT 2025