sun50i_a64_ccu.c revision 1.23
1 /* $NetBSD: sun50i_a64_ccu.c,v 1.23 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.23 2021/01/27 03:10:20 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_a64_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_VIDEO0_CTRL_REG 0x010 46 #define PLL_PERIPH0_CTRL_REG 0x028 47 #define PLL_PERIPH1_CTRL_REG 0x02c 48 #define PLL_VIDEO1_CTRL_REG 0x030 49 #define PLL_GPU_CTRL_REG 0x038 50 #define PLL_DE_CTRL_REG 0x048 51 #define AHB1_APB1_CFG_REG 0x054 52 #define APB2_CFG_REG 0x058 53 #define AHB2_CFG_REG 0x05c 54 #define BUS_CLK_GATING_REG0 0x060 55 #define BUS_CLK_GATING_REG1 0x064 56 #define BUS_CLK_GATING_REG2 0x068 57 #define BUS_CLK_GATING_REG3 0x06c 58 #define BUS_CLK_GATING_REG4 0x070 59 #define THS_CLK_REG 0x074 60 #define SDMMC0_CLK_REG 0x088 61 #define SDMMC1_CLK_REG 0x08c 62 #define SDMMC2_CLK_REG 0x090 63 #define CE_CLK_REG 0x09c 64 #define SPI0_CLK_REG 0x0a0 65 #define SPI1_CLK_REG 0x0a4 66 #define I2SPCM0_CLK_REG 0x0b0 67 #define I2SPCM1_CLK_REG 0x0b4 68 #define I2SPCM2_CLK_REG 0x0b8 69 #define USBPHY_CFG_REG 0x0cc 70 #define DRAM_CFG_REG 0x0f4 71 #define MBUS_RST_REG 0x0fc 72 #define DE_CLK_REG 0x104 73 #define TCON0_CLK_REG 0x118 74 #define TCON1_CLK_REG 0x11c 75 #define AC_DIG_CLK_REG 0x140 76 #define HDMI_CLK_REG 0x150 77 #define HDMI_SLOW_CLK_REG 0x154 78 #define GPU_CLK_REG 0x1a0 79 #define BUS_SOFT_RST_REG0 0x2c0 80 #define BUS_SOFT_RST_REG1 0x2c4 81 #define BUS_SOFT_RST_REG2 0x2c8 82 #define BUS_SOFT_RST_REG3 0x2d0 83 #define BUS_SOFT_RST_REG4 0x2d8 84 85 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *); 86 static void sun50i_a64_ccu_attach(device_t, device_t, void *); 87 88 static const struct device_compatible_entry compat_data[] = { 89 { .compat = "allwinner,sun50i-a64-ccu" }, 90 DEVICE_COMPAT_EOL 91 }; 92 93 CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc), 94 sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL); 95 96 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = { 97 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0), 98 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1), 99 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2), 100 101 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31), 102 103 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31), 104 105 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 106 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 107 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 108 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 109 SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 110 SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 111 SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 112 SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 113 SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 114 SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 115 SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 116 SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 117 SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 118 SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 119 SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 120 SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 121 SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 122 SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 123 124 SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 125 SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 126 SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 127 SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 128 SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 129 SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 130 SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 131 SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 132 SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 133 SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 134 SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 135 SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 136 137 SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0), 138 139 SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 140 SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 141 SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 142 SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 143 SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 144 SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 145 146 SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 147 SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 148 SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 149 SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5), 150 SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 151 SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 152 SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 153 SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 154 }; 155 156 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 157 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 158 static const char *apb1_parents[] = { "ahb1" }; 159 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 160 static const char *ce_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 161 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 162 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL }; 163 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" }; 164 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" }; 165 static const char *i2s_parents[] = { "pll_audio_8x", "pll_audio_4x", "pll_audio_2x", "pll_audio" }; 166 static const char *spi_parents[] = { "hosc", "pll_periph0", "pll_periph1", NULL }; 167 static const char *tcon0_parents[] = { "pll_mipi", NULL, "pll_video0_2x", NULL }; 168 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL }; 169 static const char *gpu_parents[] = { "pll_gpu" }; 170 171 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = { 172 { 60000000, 9, 0, 0, 2 }, 173 { 66000000, 10, 0, 0, 2 }, 174 { 72000000, 11, 0, 0, 2 }, 175 { 78000000, 12, 0, 0, 2 }, 176 { 84000000, 13, 0, 0, 2 }, 177 { 90000000, 14, 0, 0, 2 }, 178 { 96000000, 15, 0, 0, 2 }, 179 { 102000000, 16, 0, 0, 2 }, 180 { 108000000, 17, 0, 0, 2 }, 181 { 114000000, 18, 0, 0, 2 }, 182 { 120000000, 9, 0, 0, 1 }, 183 { 132000000, 10, 0, 0, 1 }, 184 { 144000000, 11, 0, 0, 1 }, 185 { 156000000, 12, 0, 0, 1 }, 186 { 168000000, 13, 0, 0, 1 }, 187 { 180000000, 14, 0, 0, 1 }, 188 { 192000000, 15, 0, 0, 1 }, 189 { 204000000, 16, 0, 0, 1 }, 190 { 216000000, 17, 0, 0, 1 }, 191 { 228000000, 18, 0, 0, 1 }, 192 { 240000000, 9, 0, 0, 0 }, 193 { 264000000, 10, 0, 0, 0 }, 194 { 288000000, 11, 0, 0, 0 }, 195 { 312000000, 12, 0, 0, 0 }, 196 { 336000000, 13, 0, 0, 0 }, 197 { 360000000, 14, 0, 0, 0 }, 198 { 384000000, 15, 0, 0, 0 }, 199 { 408000000, 16, 0, 0, 0 }, 200 { 432000000, 17, 0, 0, 0 }, 201 { 456000000, 18, 0, 0, 0 }, 202 { 480000000, 19, 0, 0, 0 }, 203 { 504000000, 20, 0, 0, 0 }, 204 { 528000000, 21, 0, 0, 0 }, 205 { 552000000, 22, 0, 0, 0 }, 206 { 576000000, 23, 0, 0, 0 }, 207 { 600000000, 24, 0, 0, 0 }, 208 { 624000000, 25, 0, 0, 0 }, 209 { 648000000, 26, 0, 0, 0 }, 210 { 672000000, 27, 0, 0, 0 }, 211 { 696000000, 28, 0, 0, 0 }, 212 { 720000000, 29, 0, 0, 0 }, 213 { 768000000, 15, 1, 0, 0 }, 214 { 792000000, 10, 2, 0, 0 }, 215 { 816000000, 16, 1, 0, 0 }, 216 { 864000000, 17, 1, 0, 0 }, 217 { 912000000, 18, 1, 0, 0 }, 218 { 936000000, 12, 2, 0, 0 }, 219 { 960000000, 19, 1, 0, 0 }, 220 { 1008000000, 20, 1, 0, 0 }, 221 { 1056000000, 21, 1, 0, 0 }, 222 { 1080000000, 14, 2, 0, 0 }, 223 { 1104000000, 22, 1, 0, 0 }, 224 { 1152000000, 23, 1, 0, 0 }, 225 { 1200000000, 24, 1, 0, 0 }, 226 { 1224000000, 16, 2, 0, 0 }, 227 { 1248000000, 25, 1, 0, 0 }, 228 { 1296000000, 26, 1, 0, 0 }, 229 { 1344000000, 27, 1, 0, 0 }, 230 { 1368000000, 18, 2, 0, 0 }, 231 { 1440000000, 19, 2, 0, 0 }, 232 { 1512000000, 20, 2, 0, 0 }, 233 { 1536000000, 15, 3, 0, 0 }, 234 { 1584000000, 21, 2, 0, 0 }, 235 { 1632000000, 16, 3, 0, 0 }, 236 { 1656000000, 22, 2, 0, 0 }, 237 { 1728000000, 23, 2, 0, 0 }, 238 { 1800000000, 24, 2, 0, 0 }, 239 { 1872000000, 25, 2, 0, 0 }, 240 { 0 } 241 }; 242 243 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_ac_dig_table[] = { 244 { 24576000, 0x55, 0, 0x14, 0x3 }, 245 { 0 } 246 }; 247 248 static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = { 249 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_CPUX, "pll_cpux", "hosc", 250 PLL_CPUX_CTRL_REG, /* reg */ 251 __BITS(12,8), /* n */ 252 __BITS(5,4), /* k */ 253 __BITS(1,0), /* m */ 254 __BITS(17,16), /* p */ 255 __BIT(31), /* enable */ 256 __BIT(28), /* lock */ 257 sun50i_a64_cpux_table, /* table */ 258 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 259 260 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 261 PLL_PERIPH0_CTRL_REG, /* reg */ 262 __BITS(12,8), /* n */ 263 __BITS(5,4), /* k */ 264 0, /* m */ 265 __BITS(17,16), /* p */ 266 __BIT(31), /* enable */ 267 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 268 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2), 269 270 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH1, "pll_periph1", "hosc", 271 PLL_PERIPH1_CTRL_REG, /* reg */ 272 __BITS(12,8), /* n */ 273 __BITS(5,4), /* k */ 274 0, /* m */ 275 __BITS(17,16), /* p */ 276 __BIT(31), /* enable */ 277 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 278 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH1_2X, "pll_periph1_2x", "pll_periph1", 1, 2), 279 280 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_AUDIO_BASE, "pll_audio_base", "hosc", 281 PLL_AUDIO_CTRL_REG, /* reg */ 282 __BITS(14,8), /* n */ 283 0, /* k */ 284 __BITS(4,0), /* m */ 285 __BITS(19,16), /* p */ 286 __BIT(31), /* enable */ 287 __BIT(28), /* lock */ 288 sun50i_a64_ac_dig_table, /* table */ 289 0), 290 291 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO, "pll_audio", "pll_audio_base", 1, 1), 292 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_2X, "pll_audio_2x", "pll_audio_base", 1, 2), 293 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_4X, "pll_audio_4x", "pll_audio_base", 1, 4), 294 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_8X, "pll_audio_8x", "pll_audio_base", 1, 8), 295 296 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO0, "pll_video0", "hosc", 297 PLL_VIDEO0_CTRL_REG, /* reg */ 298 __BITS(14,8), /* m */ 299 16, /* m_min */ 300 50, /* m_max */ 301 __BIT(24), /* div_en */ 302 __BIT(25), /* frac_sel */ 303 270000000, 297000000, /* frac values */ 304 __BITS(3,0), /* prediv */ 305 4, /* prediv_val */ 306 __BIT(31), /* enable */ 307 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 308 309 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_VIDEO0_2X, "pll_video0_2x", "pll_video0", 1, 2), 310 311 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO1, "pll_video1", "hosc", 312 PLL_VIDEO1_CTRL_REG, /* reg */ 313 __BITS(14,8), /* m */ 314 16, /* m_min */ 315 50, /* m_max */ 316 __BIT(24), /* div_en */ 317 __BIT(25), /* frac_sel */ 318 270000000, 297000000, /* frac values */ 319 __BITS(3,0), /* prediv */ 320 4, /* prediv_val */ 321 __BIT(31), /* enable */ 322 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 323 324 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_DE, "pll_de", "hosc", 325 PLL_DE_CTRL_REG, /* reg */ 326 __BITS(14,8), /* m */ 327 16, /* m_min */ 328 50, /* m_max */ 329 __BIT(24), /* div_en */ 330 __BIT(25), /* frac_sel */ 331 270000000, 297000000, /* frac values */ 332 __BITS(3,0), /* prediv */ 333 2, /* prediv_val */ 334 __BIT(31), /* enable */ 335 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 336 337 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_GPU, "pll_gpu", "hosc", 338 PLL_GPU_CTRL_REG, /* reg */ 339 __BITS(14,8), /* m */ 340 1, /* m_min */ 341 128, /* m_max */ 342 __BIT(24), /* div_en */ 343 __BIT(25), /* frac_sel */ 344 270000000, 297000000, /* frac values */ 345 __BITS(3,0), /* prediv */ 346 4, /* prediv_val */ 347 __BIT(31), /* enable */ 348 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 349 350 SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents, 351 AHB1_APB1_CFG_REG, /* reg */ 352 __BITS(7,6), /* prediv */ 353 __BIT(3), /* prediv_sel */ 354 __BITS(5,4), /* div */ 355 __BITS(13,12), /* sel */ 356 SUNXI_CCU_PREDIV_POWER_OF_TWO), 357 358 SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents, 359 AHB2_CFG_REG, /* reg */ 360 0, /* prediv */ 361 __BIT(1), /* prediv_sel */ 362 0, /* div */ 363 __BITS(1,0), /* sel */ 364 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 365 366 SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents, 367 AHB1_APB1_CFG_REG, /* reg */ 368 __BITS(9,8), /* div */ 369 0, /* sel */ 370 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 371 372 SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents, 373 APB2_CFG_REG, /* reg */ 374 __BITS(17,16), /* n */ 375 __BITS(4,0), /* m */ 376 __BITS(25,24), /* sel */ 377 0, /* enable */ 378 SUNXI_CCU_NM_POWER_OF_TWO), 379 380 SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mmc_parents, 381 SDMMC0_CLK_REG, /* reg */ 382 __BITS(17,16), /* n */ 383 __BITS(3,0), /* m */ 384 __BITS(25,24), /* sel */ 385 __BIT(31), /* enable */ 386 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 387 SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mmc_parents, 388 SDMMC1_CLK_REG, /* reg */ 389 __BITS(17,16), /* n */ 390 __BITS(3,0), /* m */ 391 __BITS(25,24), /* sel */ 392 __BIT(31), /* enable */ 393 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 394 SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mmc_parents, 395 SDMMC2_CLK_REG, /* reg */ 396 __BITS(17,16), /* n */ 397 __BITS(3,0), /* m */ 398 __BITS(25,24), /* sel */ 399 __BIT(31), /* enable */ 400 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 401 402 SUNXI_CCU_NM(A64_CLK_CE, "ce", ce_parents, 403 CE_CLK_REG, /* reg */ 404 __BITS(17,16), /* n */ 405 __BITS(3,0), /* m */ 406 __BITS(25,24), /* sel */ 407 __BIT(31), /* enable */ 408 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 409 410 SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents, 411 THS_CLK_REG, /* reg */ 412 __BITS(1,0), /* div */ 413 __BITS(25,24), /* sel */ 414 __BIT(31), /* enable */ 415 SUNXI_CCU_DIV_TIMES_TWO), 416 417 SUNXI_CCU_DIV_GATE(A64_CLK_DE, "de", de_parents, 418 DE_CLK_REG, /* reg */ 419 __BITS(3,0), /* div */ 420 __BITS(26,24), /* sel */ 421 __BIT(31), /* enable */ 422 0), 423 424 SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 425 AC_DIG_CLK_REG, 31), 426 SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x", 427 AC_DIG_CLK_REG, 30), 428 429 SUNXI_CCU_DIV_GATE(A64_CLK_HDMI, "hdmi", hdmi_parents, 430 HDMI_CLK_REG, /* reg */ 431 __BITS(3,0), /* div */ 432 __BITS(25,24), /* sel */ 433 __BIT(31), /* enable */ 434 0), 435 436 SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc", 437 HDMI_SLOW_CLK_REG, 31), 438 439 SUNXI_CCU_DIV_GATE(A64_CLK_I2S0, "i2s0", i2s_parents, 440 I2SPCM0_CLK_REG, /* reg */ 441 0, /* div */ 442 __BITS(17,16), /* sel */ 443 __BIT(31), /* enable */ 444 0), 445 SUNXI_CCU_DIV_GATE(A64_CLK_I2S1, "i2s1", i2s_parents, 446 I2SPCM1_CLK_REG, /* reg */ 447 0, /* div */ 448 __BITS(17,16), /* sel */ 449 __BIT(31), /* enable */ 450 0), 451 SUNXI_CCU_DIV_GATE(A64_CLK_I2S2, "i2s2", i2s_parents, 452 I2SPCM2_CLK_REG, /* reg */ 453 0, /* div */ 454 __BITS(17,16), /* sel */ 455 __BIT(31), /* enable */ 456 0), 457 458 SUNXI_CCU_NM(A64_CLK_SPI0, "spi0", spi_parents, 459 SPI0_CLK_REG, /* reg */ 460 __BITS(17,16), /* n */ 461 __BITS(3,0), /* m */ 462 __BITS(25,24), /* sel */ 463 __BIT(31), /* enable */ 464 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 465 466 SUNXI_CCU_NM(A64_CLK_SPI1, "spi1", spi_parents, 467 SPI1_CLK_REG, /* reg */ 468 __BITS(17,16), /* n */ 469 __BITS(3,0), /* m */ 470 __BITS(25,24), /* sel */ 471 __BIT(31), /* enable */ 472 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 473 474 SUNXI_CCU_DIV_GATE(A64_CLK_TCON0, "tcon0", tcon0_parents, 475 TCON0_CLK_REG, /* reg */ 476 0, /* div */ 477 __BITS(26,24), /* sel */ 478 __BIT(31), /* enable */ 479 0), 480 481 SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents, 482 TCON1_CLK_REG, /* reg */ 483 __BITS(3,0), /* div */ 484 __BITS(25,24), /* sel */ 485 __BIT(31), /* enable */ 486 0), 487 488 SUNXI_CCU_DIV_GATE(A64_CLK_GPU, "gpu", gpu_parents, 489 GPU_CLK_REG, /* reg */ 490 __BITS(2,0), /* div */ 491 0, /* sel */ 492 __BIT(31), /* enable */ 493 0), 494 495 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 496 BUS_CLK_GATING_REG0, 1), 497 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 498 BUS_CLK_GATING_REG0, 5), 499 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 500 BUS_CLK_GATING_REG0, 6), 501 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 502 BUS_CLK_GATING_REG0, 8), 503 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 504 BUS_CLK_GATING_REG0, 9), 505 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 506 BUS_CLK_GATING_REG0, 10), 507 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 508 BUS_CLK_GATING_REG0, 13), 509 SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 510 BUS_CLK_GATING_REG0, 14), 511 SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 512 BUS_CLK_GATING_REG0, 17), 513 SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 514 BUS_CLK_GATING_REG0, 18), 515 SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 516 BUS_CLK_GATING_REG0, 19), 517 SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 518 BUS_CLK_GATING_REG0, 20), 519 SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 520 BUS_CLK_GATING_REG0, 21), 521 SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 522 BUS_CLK_GATING_REG0, 23), 523 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 524 BUS_CLK_GATING_REG0, 24), 525 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 526 BUS_CLK_GATING_REG0, 25), 527 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 528 BUS_CLK_GATING_REG0, 28), 529 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 530 BUS_CLK_GATING_REG0, 29), 531 532 SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 533 BUS_CLK_GATING_REG1, 0), 534 SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 535 BUS_CLK_GATING_REG1, 3), 536 SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 537 BUS_CLK_GATING_REG1, 4), 538 SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 539 BUS_CLK_GATING_REG1, 5), 540 SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 541 BUS_CLK_GATING_REG1, 8), 542 SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 543 BUS_CLK_GATING_REG1, 11), 544 SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 545 BUS_CLK_GATING_REG1, 12), 546 SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 547 BUS_CLK_GATING_REG1, 20), 548 SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 549 BUS_CLK_GATING_REG1, 21), 550 SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 551 BUS_CLK_GATING_REG1, 22), 552 553 SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 554 BUS_CLK_GATING_REG2, 0), 555 SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 556 BUS_CLK_GATING_REG2, 1), 557 SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 558 BUS_CLK_GATING_REG2, 5), 559 SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 560 BUS_CLK_GATING_REG2, 8), 561 SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 562 BUS_CLK_GATING_REG2, 12), 563 SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 564 BUS_CLK_GATING_REG2, 13), 565 SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 566 BUS_CLK_GATING_REG2, 14), 567 568 SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 569 BUS_CLK_GATING_REG3, 0), 570 SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 571 BUS_CLK_GATING_REG3, 1), 572 SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 573 BUS_CLK_GATING_REG3, 2), 574 SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2", 575 BUS_CLK_GATING_REG3, 5), 576 SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 577 BUS_CLK_GATING_REG3, 16), 578 SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 579 BUS_CLK_GATING_REG3, 17), 580 SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 581 BUS_CLK_GATING_REG3, 18), 582 SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 583 BUS_CLK_GATING_REG3, 19), 584 SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 585 BUS_CLK_GATING_REG3, 20), 586 587 SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc", 588 USBPHY_CFG_REG, 8), 589 SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc", 590 USBPHY_CFG_REG, 9), 591 SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc", 592 USBPHY_CFG_REG, 10), 593 SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc", 594 USBPHY_CFG_REG, 11), 595 SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc", 596 USBPHY_CFG_REG, 16), 597 SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 598 USBPHY_CFG_REG, 17), 599 }; 600 601 static int 602 sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux) 603 { 604 struct fdt_attach_args * const faa = aux; 605 606 return of_compatible_match(faa->faa_phandle, compat_data); 607 } 608 609 static void 610 sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux) 611 { 612 struct sunxi_ccu_softc * const sc = device_private(self); 613 struct fdt_attach_args * const faa = aux; 614 prop_dictionary_t prop = device_properties(self); 615 bool nomodeset; 616 617 sc->sc_dev = self; 618 sc->sc_phandle = faa->faa_phandle; 619 sc->sc_bst = faa->faa_bst; 620 621 sc->sc_resets = sun50i_a64_ccu_resets; 622 sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets); 623 624 sc->sc_clks = sun50i_a64_ccu_clks; 625 sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks); 626 627 if (sunxi_ccu_attach(sc) != 0) 628 return; 629 630 aprint_naive("\n"); 631 aprint_normal(": A64 CCU\n"); 632 633 nomodeset = false; 634 prop_dictionary_get_bool(prop, "nomodeset", &nomodeset); 635 if (!nomodeset) { 636 /* Set DE parent to PLL_DE */ 637 clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base); 638 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000); 639 640 /* Set video PLLs to 297 MHz */ 641 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO0].base, 297000000); 642 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO1].base, 297000000); 643 644 /* Set TCON1 parent to PLL_VIDEO1(1X) */ 645 clk_set_parent(&sc->sc_clks[A64_CLK_TCON1].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base); 646 647 /* Set HDMI parent to PLL_VIDEO1(1X) */ 648 clk_set_parent(&sc->sc_clks[A64_CLK_HDMI].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base); 649 } 650 651 sunxi_ccu_print(sc); 652 } 653
Indexes created Thu Oct 02 14:10:14 GMT 2025