sun50i_a64_ccu.c revision 1.4
1 /* $NetBSD: sun50i_a64_ccu.c,v 1.4 2018/05/05 13:28:23 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.4 2018/05/05 13:28:23 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_a64_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_PERIPH0_CTRL_REG 0x028 46 #define PLL_PERIPH1_CTRL_REG 0x02c 47 #define AHB1_APB1_CFG_REG 0x054 48 #define APB2_CFG_REG 0x058 49 #define AHB2_CFG_REG 0x05c 50 #define BUS_CLK_GATING_REG0 0x060 51 #define BUS_CLK_GATING_REG1 0x064 52 #define BUS_CLK_GATING_REG2 0x068 53 #define BUS_CLK_GATING_REG3 0x06c 54 #define BUS_CLK_GATING_REG4 0x070 55 #define THS_CLK_REG 0x074 56 #define SDMMC0_CLK_REG 0x088 57 #define SDMMC1_CLK_REG 0x08c 58 #define SDMMC2_CLK_REG 0x090 59 #define USBPHY_CFG_REG 0x0cc 60 #define DRAM_CFG_REG 0x0f4 61 #define MBUS_RST_REG 0x0fc 62 #define AC_DIG_CLK_REG 0x140 63 #define BUS_SOFT_RST_REG0 0x2c0 64 #define BUS_SOFT_RST_REG1 0x2c4 65 #define BUS_SOFT_RST_REG2 0x2c8 66 #define BUS_SOFT_RST_REG3 0x2d0 67 #define BUS_SOFT_RST_REG4 0x2d8 68 69 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *); 70 static void sun50i_a64_ccu_attach(device_t, device_t, void *); 71 72 static const char * const compatible[] = { 73 "allwinner,sun50i-a64-ccu", 74 NULL 75 }; 76 77 CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc), 78 sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL); 79 80 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = { 81 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0), 82 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1), 83 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2), 84 85 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31), 86 87 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31), 88 89 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 90 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 91 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 92 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 93 SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 94 SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 95 SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 96 SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 97 SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 98 SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 99 SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 100 SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 101 SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 102 SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 103 SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 104 SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 105 SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 106 SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 107 108 SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 109 SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 110 SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 111 SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 112 SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 113 SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 114 SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 115 SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 116 SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 117 SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 118 SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 119 SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 120 121 SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0), 122 123 SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 124 SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 125 SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 126 SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 127 SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 128 SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 129 130 SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 131 SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 132 SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 133 SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5), 134 SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 135 SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 136 SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 137 SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 138 }; 139 140 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 141 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 142 static const char *apb1_parents[] = { "ahb1" }; 143 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 144 static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" }; 145 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL }; 146 147 static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = { 148 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 149 PLL_PERIPH0_CTRL_REG, /* reg */ 150 __BITS(12,8), /* n */ 151 __BITS(5,4), /* k */ 152 0, /* m */ 153 __BITS(17,16), /* p */ 154 __BIT(31), /* enable */ 155 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 156 157 SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents, 158 AHB1_APB1_CFG_REG, /* reg */ 159 __BITS(7,6), /* prediv */ 160 __BIT(3), /* prediv_sel */ 161 __BITS(5,4), /* div */ 162 __BITS(13,12), /* sel */ 163 SUNXI_CCU_PREDIV_POWER_OF_TWO), 164 165 SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents, 166 AHB2_CFG_REG, /* reg */ 167 0, /* prediv */ 168 __BIT(1), /* prediv_sel */ 169 0, /* div */ 170 __BITS(1,0), /* sel */ 171 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 172 173 SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents, 174 AHB1_APB1_CFG_REG, /* reg */ 175 __BITS(9,8), /* div */ 176 0, /* sel */ 177 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 178 179 SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents, 180 APB2_CFG_REG, /* reg */ 181 __BITS(17,16), /* n */ 182 __BITS(4,0), /* m */ 183 __BITS(25,24), /* sel */ 184 0, /* enable */ 185 SUNXI_CCU_NM_POWER_OF_TWO), 186 187 SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mod_parents, 188 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 189 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 190 SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mod_parents, 191 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 192 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 193 SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mod_parents, 194 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 195 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 196 197 SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents, 198 THS_CLK_REG, /* reg */ 199 __BITS(1,0), /* div */ 200 __BITS(25,24), /* sel */ 201 __BIT(31), /* enable */ 202 SUNXI_CCU_DIV_TIMES_TWO), 203 204 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 205 BUS_CLK_GATING_REG0, 1), 206 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 207 BUS_CLK_GATING_REG0, 5), 208 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 209 BUS_CLK_GATING_REG0, 6), 210 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 211 BUS_CLK_GATING_REG0, 8), 212 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 213 BUS_CLK_GATING_REG0, 9), 214 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 215 BUS_CLK_GATING_REG0, 10), 216 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 217 BUS_CLK_GATING_REG0, 13), 218 SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 219 BUS_CLK_GATING_REG0, 14), 220 SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 221 BUS_CLK_GATING_REG0, 17), 222 SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 223 BUS_CLK_GATING_REG0, 18), 224 SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 225 BUS_CLK_GATING_REG0, 19), 226 SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 227 BUS_CLK_GATING_REG0, 20), 228 SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 229 BUS_CLK_GATING_REG0, 21), 230 SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 231 BUS_CLK_GATING_REG0, 23), 232 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 233 BUS_CLK_GATING_REG0, 24), 234 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 235 BUS_CLK_GATING_REG0, 25), 236 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 237 BUS_CLK_GATING_REG0, 28), 238 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 239 BUS_CLK_GATING_REG0, 29), 240 241 SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 242 BUS_CLK_GATING_REG1, 0), 243 SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 244 BUS_CLK_GATING_REG1, 3), 245 SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 246 BUS_CLK_GATING_REG1, 4), 247 SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 248 BUS_CLK_GATING_REG1, 5), 249 SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 250 BUS_CLK_GATING_REG1, 8), 251 SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 252 BUS_CLK_GATING_REG1, 10), 253 SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 254 BUS_CLK_GATING_REG1, 12), 255 SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 256 BUS_CLK_GATING_REG1, 20), 257 SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 258 BUS_CLK_GATING_REG1, 21), 259 SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 260 BUS_CLK_GATING_REG1, 22), 261 262 SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 263 BUS_CLK_GATING_REG2, 8), 264 265 SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 266 BUS_CLK_GATING_REG3, 0), 267 SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 268 BUS_CLK_GATING_REG3, 1), 269 SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 270 BUS_CLK_GATING_REG3, 5), 271 SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 272 BUS_CLK_GATING_REG3, 12), 273 SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 274 BUS_CLK_GATING_REG3, 13), 275 SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 276 BUS_CLK_GATING_REG3, 14), 277 278 SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 279 BUS_CLK_GATING_REG4, 0), 280 SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 281 BUS_CLK_GATING_REG4, 1), 282 SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 283 BUS_CLK_GATING_REG4, 2), 284 SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2", 285 BUS_CLK_GATING_REG4, 5), 286 SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 287 BUS_CLK_GATING_REG4, 16), 288 SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 289 BUS_CLK_GATING_REG4, 17), 290 SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 291 BUS_CLK_GATING_REG4, 18), 292 SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 293 BUS_CLK_GATING_REG4, 19), 294 SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 295 BUS_CLK_GATING_REG4, 20), 296 297 SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc", 298 USBPHY_CFG_REG, 8), 299 SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc", 300 USBPHY_CFG_REG, 9), 301 SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc", 302 USBPHY_CFG_REG, 10), 303 SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc", 304 USBPHY_CFG_REG, 11), 305 SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc", 306 USBPHY_CFG_REG, 16), 307 SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 308 USBPHY_CFG_REG, 17), 309 }; 310 311 static int 312 sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux) 313 { 314 struct fdt_attach_args * const faa = aux; 315 316 return of_match_compatible(faa->faa_phandle, compatible); 317 } 318 319 static void 320 sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux) 321 { 322 struct sunxi_ccu_softc * const sc = device_private(self); 323 struct fdt_attach_args * const faa = aux; 324 325 sc->sc_dev = self; 326 sc->sc_phandle = faa->faa_phandle; 327 sc->sc_bst = faa->faa_bst; 328 329 sc->sc_resets = sun50i_a64_ccu_resets; 330 sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets); 331 332 sc->sc_clks = sun50i_a64_ccu_clks; 333 sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks); 334 335 if (sunxi_ccu_attach(sc) != 0) 336 return; 337 338 aprint_naive("\n"); 339 aprint_normal(": A64 CCU\n"); 340 341 sunxi_ccu_print(sc); 342 } 343
Indexes created Thu Oct 02 14:10:14 GMT 2025