sun50i_a64_ccu.c revision 1.9
1 /* $NetBSD: sun50i_a64_ccu.c,v 1.9 2018/05/18 02:03:00 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.9 2018/05/18 02:03:00 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_a64_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_PERIPH0_CTRL_REG 0x028 46 #define PLL_PERIPH1_CTRL_REG 0x02c 47 #define AHB1_APB1_CFG_REG 0x054 48 #define APB2_CFG_REG 0x058 49 #define AHB2_CFG_REG 0x05c 50 #define BUS_CLK_GATING_REG0 0x060 51 #define BUS_CLK_GATING_REG1 0x064 52 #define BUS_CLK_GATING_REG2 0x068 53 #define BUS_CLK_GATING_REG3 0x06c 54 #define BUS_CLK_GATING_REG4 0x070 55 #define THS_CLK_REG 0x074 56 #define SDMMC0_CLK_REG 0x088 57 #define SDMMC1_CLK_REG 0x08c 58 #define SDMMC2_CLK_REG 0x090 59 #define USBPHY_CFG_REG 0x0cc 60 #define DRAM_CFG_REG 0x0f4 61 #define MBUS_RST_REG 0x0fc 62 #define AC_DIG_CLK_REG 0x140 63 #define BUS_SOFT_RST_REG0 0x2c0 64 #define BUS_SOFT_RST_REG1 0x2c4 65 #define BUS_SOFT_RST_REG2 0x2c8 66 #define BUS_SOFT_RST_REG3 0x2d0 67 #define BUS_SOFT_RST_REG4 0x2d8 68 69 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *); 70 static void sun50i_a64_ccu_attach(device_t, device_t, void *); 71 72 static const char * const compatible[] = { 73 "allwinner,sun50i-a64-ccu", 74 NULL 75 }; 76 77 CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc), 78 sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL); 79 80 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = { 81 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0), 82 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1), 83 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2), 84 85 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31), 86 87 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31), 88 89 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 90 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 91 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 92 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 93 SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 94 SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 95 SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 96 SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 97 SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 98 SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 99 SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 100 SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 101 SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 102 SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 103 SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 104 SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 105 SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 106 SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 107 108 SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 109 SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 110 SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 111 SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 112 SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 113 SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 114 SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 115 SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 116 SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 117 SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 118 SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 119 SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 120 121 SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0), 122 123 SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 124 SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 125 SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 126 SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 127 SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 128 SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 129 130 SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 131 SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 132 SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 133 SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5), 134 SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 135 SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 136 SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 137 SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 138 }; 139 140 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 141 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 142 static const char *apb1_parents[] = { "ahb1" }; 143 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 144 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 145 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL }; 146 147 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = { 148 { 60000000, 9, 0, 0, 2 }, 149 { 66000000, 10, 0, 0, 2 }, 150 { 72000000, 11, 0, 0, 2 }, 151 { 78000000, 12, 0, 0, 2 }, 152 { 84000000, 13, 0, 0, 2 }, 153 { 90000000, 14, 0, 0, 2 }, 154 { 96000000, 15, 0, 0, 2 }, 155 { 102000000, 16, 0, 0, 2 }, 156 { 108000000, 17, 0, 0, 2 }, 157 { 114000000, 18, 0, 0, 2 }, 158 { 120000000, 9, 0, 0, 1 }, 159 { 132000000, 10, 0, 0, 1 }, 160 { 144000000, 11, 0, 0, 1 }, 161 { 156000000, 12, 0, 0, 1 }, 162 { 168000000, 13, 0, 0, 1 }, 163 { 180000000, 14, 0, 0, 1 }, 164 { 192000000, 15, 0, 0, 1 }, 165 { 204000000, 16, 0, 0, 1 }, 166 { 216000000, 17, 0, 0, 1 }, 167 { 228000000, 18, 0, 0, 1 }, 168 { 240000000, 9, 0, 0, 0 }, 169 { 264000000, 10, 0, 0, 0 }, 170 { 288000000, 11, 0, 0, 0 }, 171 { 312000000, 12, 0, 0, 0 }, 172 { 336000000, 13, 0, 0, 0 }, 173 { 360000000, 14, 0, 0, 0 }, 174 { 384000000, 15, 0, 0, 0 }, 175 { 408000000, 16, 0, 0, 0 }, 176 { 432000000, 17, 0, 0, 0 }, 177 { 456000000, 18, 0, 0, 0 }, 178 { 480000000, 19, 0, 0, 0 }, 179 { 504000000, 20, 0, 0, 0 }, 180 { 528000000, 21, 0, 0, 0 }, 181 { 552000000, 22, 0, 0, 0 }, 182 { 576000000, 23, 0, 0, 0 }, 183 { 600000000, 24, 0, 0, 0 }, 184 { 624000000, 25, 0, 0, 0 }, 185 { 648000000, 26, 0, 0, 0 }, 186 { 672000000, 27, 0, 0, 0 }, 187 { 696000000, 28, 0, 0, 0 }, 188 { 720000000, 29, 0, 0, 0 }, 189 { 768000000, 15, 1, 0, 0 }, 190 { 792000000, 10, 2, 0, 0 }, 191 { 816000000, 16, 1, 0, 0 }, 192 { 864000000, 17, 1, 0, 0 }, 193 { 912000000, 18, 1, 0, 0 }, 194 { 936000000, 12, 2, 0, 0 }, 195 { 960000000, 19, 1, 0, 0 }, 196 { 1008000000, 20, 1, 0, 0 }, 197 { 1056000000, 21, 1, 0, 0 }, 198 { 1080000000, 14, 2, 0, 0 }, 199 { 1104000000, 22, 1, 0, 0 }, 200 { 1152000000, 23, 1, 0, 0 }, 201 { 1200000000, 24, 1, 0, 0 }, 202 { 1224000000, 16, 2, 0, 0 }, 203 { 1248000000, 25, 1, 0, 0 }, 204 { 1296000000, 26, 1, 0, 0 }, 205 { 1344000000, 27, 1, 0, 0 }, 206 { 1368000000, 18, 2, 0, 0 }, 207 { 1440000000, 19, 2, 0, 0 }, 208 { 1512000000, 20, 2, 0, 0 }, 209 { 1536000000, 15, 3, 0, 0 }, 210 { 1584000000, 21, 2, 0, 0 }, 211 { 1632000000, 16, 3, 0, 0 }, 212 { 1656000000, 22, 2, 0, 0 }, 213 { 1728000000, 23, 2, 0, 0 }, 214 { 1800000000, 24, 2, 0, 0 }, 215 { 1872000000, 25, 2, 0, 0 }, 216 { 0 } 217 }; 218 219 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_ac_dig_table[] = { 220 { 24576000, 0x55, 0, 0x14, 0x3 }, 221 { 0 } 222 }; 223 224 static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = { 225 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_CPUX, "pll_cpux", "hosc", 226 PLL_CPUX_CTRL_REG, /* reg */ 227 __BITS(12,8), /* n */ 228 __BITS(5,4), /* k */ 229 __BITS(1,0), /* m */ 230 __BITS(17,16), /* p */ 231 __BIT(31), /* enable */ 232 __BIT(28), /* lock */ 233 sun50i_a64_cpux_table, /* table */ 234 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 235 236 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 237 PLL_PERIPH0_CTRL_REG, /* reg */ 238 __BITS(12,8), /* n */ 239 __BITS(5,4), /* k */ 240 0, /* m */ 241 __BITS(17,16), /* p */ 242 __BIT(31), /* enable */ 243 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 244 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2), 245 246 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_AUDIO_BASE, "pll_audio_base", "hosc", 247 PLL_AUDIO_CTRL_REG, /* reg */ 248 __BITS(14,8), /* n */ 249 0, /* k */ 250 __BITS(4,0), /* m */ 251 __BITS(19,16), /* p */ 252 __BIT(31), /* enable */ 253 __BIT(28), /* lock */ 254 sun50i_a64_ac_dig_table, /* table */ 255 0), 256 257 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO, "pll_audio", "pll_audio_base", 1, 1), 258 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_2X, "pll_audio_2x", "pll_audio_base", 1, 2), 259 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_4X, "pll_audio_4x", "pll_audio_base", 1, 4), 260 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_8X, "pll_audio_8x", "pll_audio_base", 1, 8), 261 262 SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents, 263 AHB1_APB1_CFG_REG, /* reg */ 264 __BITS(7,6), /* prediv */ 265 __BIT(3), /* prediv_sel */ 266 __BITS(5,4), /* div */ 267 __BITS(13,12), /* sel */ 268 SUNXI_CCU_PREDIV_POWER_OF_TWO), 269 270 SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents, 271 AHB2_CFG_REG, /* reg */ 272 0, /* prediv */ 273 __BIT(1), /* prediv_sel */ 274 0, /* div */ 275 __BITS(1,0), /* sel */ 276 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 277 278 SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents, 279 AHB1_APB1_CFG_REG, /* reg */ 280 __BITS(9,8), /* div */ 281 0, /* sel */ 282 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 283 284 SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents, 285 APB2_CFG_REG, /* reg */ 286 __BITS(17,16), /* n */ 287 __BITS(4,0), /* m */ 288 __BITS(25,24), /* sel */ 289 0, /* enable */ 290 SUNXI_CCU_NM_POWER_OF_TWO), 291 292 SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mmc_parents, 293 SDMMC0_CLK_REG, /* reg */ 294 __BITS(17,16), /* n */ 295 __BITS(3,0), /* m */ 296 __BITS(25,24), /* sel */ 297 __BIT(31), /* enable */ 298 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 299 SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mmc_parents, 300 SDMMC1_CLK_REG, /* reg */ 301 __BITS(17,16), /* n */ 302 __BITS(3,0), /* m */ 303 __BITS(25,24), /* sel */ 304 __BIT(31), /* enable */ 305 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 306 SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mmc_parents, 307 SDMMC2_CLK_REG, /* reg */ 308 __BITS(17,16), /* n */ 309 __BITS(3,0), /* m */ 310 __BITS(25,24), /* sel */ 311 __BIT(31), /* enable */ 312 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 313 314 SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents, 315 THS_CLK_REG, /* reg */ 316 __BITS(1,0), /* div */ 317 __BITS(25,24), /* sel */ 318 __BIT(31), /* enable */ 319 SUNXI_CCU_DIV_TIMES_TWO), 320 321 SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 322 AC_DIG_CLK_REG, 31), 323 SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x", 324 AC_DIG_CLK_REG, 30), 325 326 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 327 BUS_CLK_GATING_REG0, 1), 328 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 329 BUS_CLK_GATING_REG0, 5), 330 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 331 BUS_CLK_GATING_REG0, 6), 332 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 333 BUS_CLK_GATING_REG0, 8), 334 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 335 BUS_CLK_GATING_REG0, 9), 336 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 337 BUS_CLK_GATING_REG0, 10), 338 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 339 BUS_CLK_GATING_REG0, 13), 340 SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 341 BUS_CLK_GATING_REG0, 14), 342 SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 343 BUS_CLK_GATING_REG0, 17), 344 SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 345 BUS_CLK_GATING_REG0, 18), 346 SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 347 BUS_CLK_GATING_REG0, 19), 348 SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 349 BUS_CLK_GATING_REG0, 20), 350 SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 351 BUS_CLK_GATING_REG0, 21), 352 SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 353 BUS_CLK_GATING_REG0, 23), 354 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 355 BUS_CLK_GATING_REG0, 24), 356 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 357 BUS_CLK_GATING_REG0, 25), 358 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 359 BUS_CLK_GATING_REG0, 28), 360 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 361 BUS_CLK_GATING_REG0, 29), 362 363 SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 364 BUS_CLK_GATING_REG1, 0), 365 SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 366 BUS_CLK_GATING_REG1, 3), 367 SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 368 BUS_CLK_GATING_REG1, 4), 369 SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 370 BUS_CLK_GATING_REG1, 5), 371 SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 372 BUS_CLK_GATING_REG1, 8), 373 SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 374 BUS_CLK_GATING_REG1, 10), 375 SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 376 BUS_CLK_GATING_REG1, 12), 377 SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 378 BUS_CLK_GATING_REG1, 20), 379 SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 380 BUS_CLK_GATING_REG1, 21), 381 SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 382 BUS_CLK_GATING_REG1, 22), 383 384 SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 385 BUS_CLK_GATING_REG2, 0), 386 SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 387 BUS_CLK_GATING_REG2, 1), 388 SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 389 BUS_CLK_GATING_REG2, 5), 390 SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 391 BUS_CLK_GATING_REG2, 8), 392 SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 393 BUS_CLK_GATING_REG2, 12), 394 SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 395 BUS_CLK_GATING_REG2, 13), 396 SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 397 BUS_CLK_GATING_REG2, 14), 398 399 SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 400 BUS_CLK_GATING_REG3, 0), 401 SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 402 BUS_CLK_GATING_REG3, 1), 403 SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 404 BUS_CLK_GATING_REG3, 2), 405 SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2", 406 BUS_CLK_GATING_REG3, 5), 407 SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 408 BUS_CLK_GATING_REG3, 16), 409 SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 410 BUS_CLK_GATING_REG3, 17), 411 SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 412 BUS_CLK_GATING_REG3, 18), 413 SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 414 BUS_CLK_GATING_REG3, 19), 415 SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 416 BUS_CLK_GATING_REG3, 20), 417 418 SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc", 419 USBPHY_CFG_REG, 8), 420 SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc", 421 USBPHY_CFG_REG, 9), 422 SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc", 423 USBPHY_CFG_REG, 10), 424 SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc", 425 USBPHY_CFG_REG, 11), 426 SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc", 427 USBPHY_CFG_REG, 16), 428 SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 429 USBPHY_CFG_REG, 17), 430 }; 431 432 static int 433 sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux) 434 { 435 struct fdt_attach_args * const faa = aux; 436 437 return of_match_compatible(faa->faa_phandle, compatible); 438 } 439 440 static void 441 sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux) 442 { 443 struct sunxi_ccu_softc * const sc = device_private(self); 444 struct fdt_attach_args * const faa = aux; 445 446 sc->sc_dev = self; 447 sc->sc_phandle = faa->faa_phandle; 448 sc->sc_bst = faa->faa_bst; 449 450 sc->sc_resets = sun50i_a64_ccu_resets; 451 sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets); 452 453 sc->sc_clks = sun50i_a64_ccu_clks; 454 sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks); 455 456 if (sunxi_ccu_attach(sc) != 0) 457 return; 458 459 aprint_naive("\n"); 460 aprint_normal(": A64 CCU\n"); 461 462 sunxi_ccu_print(sc); 463 } 464
Indexes created Thu Oct 02 14:10:14 GMT 2025