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      1  1.7   thorpej /* $NetBSD: sun8i_a83t_ccu.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $ */
      2  1.1  jmcneill 
      3  1.1  jmcneill /*-
      4  1.1  jmcneill  * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  1.1  jmcneill  * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org>
      6  1.1  jmcneill  * All rights reserved.
      7  1.1  jmcneill  *
      8  1.1  jmcneill  * Redistribution and use in source and binary forms, with or without
      9  1.1  jmcneill  * modification, are permitted provided that the following conditions
     10  1.1  jmcneill  * are met:
     11  1.1  jmcneill  * 1. Redistributions of source code must retain the above copyright
     12  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer.
     13  1.1  jmcneill  * 2. Redistributions in binary form must reproduce the above copyright
     14  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer in the
     15  1.1  jmcneill  *    documentation and/or other materials provided with the distribution.
     16  1.1  jmcneill  *
     17  1.1  jmcneill  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  1.1  jmcneill  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  1.1  jmcneill  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  1.1  jmcneill  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  1.1  jmcneill  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     22  1.1  jmcneill  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     23  1.1  jmcneill  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     24  1.1  jmcneill  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     25  1.1  jmcneill  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     26  1.1  jmcneill  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     27  1.1  jmcneill  * SUCH DAMAGE.
     28  1.1  jmcneill  */
     29  1.1  jmcneill 
     30  1.1  jmcneill #include <sys/cdefs.h>
     31  1.1  jmcneill 
     32  1.7   thorpej __KERNEL_RCSID(1, "$NetBSD: sun8i_a83t_ccu.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $");
     33  1.1  jmcneill 
     34  1.1  jmcneill #include <sys/param.h>
     35  1.1  jmcneill #include <sys/bus.h>
     36  1.1  jmcneill #include <sys/device.h>
     37  1.1  jmcneill #include <sys/systm.h>
     38  1.1  jmcneill 
     39  1.1  jmcneill #include <dev/fdt/fdtvar.h>
     40  1.1  jmcneill 
     41  1.1  jmcneill #include <arm/sunxi/sunxi_ccu.h>
     42  1.1  jmcneill #include <arm/sunxi/sun8i_a83t_ccu.h>
     43  1.1  jmcneill 
     44  1.6  jmcneill #define	PLL_C0CPUX_CTRL_REG	0x000
     45  1.6  jmcneill #define	PLL_C1CPUX_CTRL_REG	0x004
     46  1.6  jmcneill #define	 PLL_CxCPUX_CTRL_PLL_FACTOR_N	__BITS(15,8)
     47  1.2  jmcneill #define	PLL_PERIPH_CTRL_REG	0x028
     48  1.6  jmcneill #define	CPUX_AXI_CFG_REG	0x050
     49  1.6  jmcneill #define	 Cx_CPUX_CLK_SRC_SEL(cluster)	__BIT(12 + (cluster) * 16)
     50  1.1  jmcneill #define	AHB1_APB1_CFG_REG	0x054
     51  1.1  jmcneill #define	APB2_CFG_REG		0x058
     52  1.1  jmcneill #define	BUS_CLK_GATING_REG0	0x060
     53  1.5  jmcneill #define	BUS_CLK_GATING_REG1	0x064
     54  1.1  jmcneill #define	BUS_CLK_GATING_REG2	0x068
     55  1.1  jmcneill #define	BUS_CLK_GATING_REG3	0x06c
     56  1.1  jmcneill #define	SDMMC0_CLK_REG		0x088
     57  1.1  jmcneill #define	SDMMC1_CLK_REG		0x08c
     58  1.1  jmcneill #define	SDMMC2_CLK_REG		0x090
     59  1.4  jmcneill #define	 SDMMC2_CLK_MODE_SELECT	__BIT(30)
     60  1.1  jmcneill #define	USBPHY_CFG_REG		0x0cc
     61  1.1  jmcneill #define	MBUS_RST_REG		0x0fc
     62  1.6  jmcneill #define	PLL_STABLE_STATUS_REG	0x20c
     63  1.1  jmcneill #define	BUS_SOFT_RST_REG0	0x2c0
     64  1.1  jmcneill #define	BUS_SOFT_RST_REG1	0x2c4
     65  1.1  jmcneill #define	BUS_SOFT_RST_REG2	0x2c8
     66  1.1  jmcneill #define	BUS_SOFT_RST_REG3	0x2d0
     67  1.1  jmcneill #define	BUS_SOFT_RST_REG4	0x2d8
     68  1.1  jmcneill 
     69  1.1  jmcneill static int sun8i_a83t_ccu_match(device_t, cfdata_t, void *);
     70  1.1  jmcneill static void sun8i_a83t_ccu_attach(device_t, device_t, void *);
     71  1.1  jmcneill 
     72  1.7   thorpej static const struct device_compatible_entry compat_data[] = {
     73  1.7   thorpej 	{ .compat = "allwinner,sun8i-a83t-ccu" },
     74  1.7   thorpej 	DEVICE_COMPAT_EOL
     75  1.1  jmcneill };
     76  1.1  jmcneill 
     77  1.1  jmcneill CFATTACH_DECL_NEW(sunxi_a83t_ccu, sizeof(struct sunxi_ccu_softc),
     78  1.1  jmcneill 	sun8i_a83t_ccu_match, sun8i_a83t_ccu_attach, NULL, NULL);
     79  1.1  jmcneill 
     80  1.1  jmcneill static struct sunxi_ccu_reset sun8i_a83t_ccu_resets[] = {
     81  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_USB_PHY0, USBPHY_CFG_REG, 0),
     82  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_USB_PHY1, USBPHY_CFG_REG, 1),
     83  1.2  jmcneill 
     84  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_MBUS, MBUS_RST_REG, 31),
     85  1.2  jmcneill 
     86  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
     87  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
     88  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
     89  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
     90  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13),
     91  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
     92  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17),
     93  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19),
     94  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
     95  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
     96  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23),
     97  1.3  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 26),
     98  1.3  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 27),
     99  1.3  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 29),
    100  1.1  jmcneill 
    101  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_VE, BUS_SOFT_RST_REG1, 0),
    102  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3),
    103  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4),
    104  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8),
    105  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10),
    106  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11),
    107  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_DE, BUS_SOFT_RST_REG1, 12),
    108  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20),
    109  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
    110  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
    111  1.2  jmcneill 
    112  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1),
    113  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12),
    114  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13),
    115  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14),
    116  1.2  jmcneill 
    117  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
    118  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
    119  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
    120  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
    121  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
    122  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
    123  1.2  jmcneill 	SUNXI_CCU_RESET(A83T_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
    124  1.1  jmcneill };
    125  1.1  jmcneill 
    126  1.1  jmcneill static const char *ahb1_parents[] = { "losc", "hosc", "pll_periph" };
    127  1.1  jmcneill static const char *ahb2_parents[] = { "ahb1", "pll_periph" };
    128  1.1  jmcneill static const char *apb1_parents[] = { "ahb1" };
    129  1.1  jmcneill static const char *apb2_parents[] = { "losc", "hosc", "pll_periph" };
    130  1.1  jmcneill static const char *mod_parents[] = { "hosc", "pll_periph" };
    131  1.1  jmcneill 
    132  1.6  jmcneill static kmutex_t cpux_axi_cfg_lock;
    133  1.6  jmcneill 
    134  1.6  jmcneill static int
    135  1.6  jmcneill sun8i_a83t_ccu_cpux_set_rate(struct sunxi_ccu_softc *sc,
    136  1.6  jmcneill     struct sunxi_ccu_clk *clk, u_int rate)
    137  1.6  jmcneill {
    138  1.6  jmcneill 	const int cluster = clk->u.nkmp.reg == PLL_C0CPUX_CTRL_REG ? 0 : 1;
    139  1.6  jmcneill 	struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp;
    140  1.6  jmcneill 	uint32_t val;
    141  1.6  jmcneill 	u_int n;
    142  1.6  jmcneill 
    143  1.6  jmcneill 	n = rate / 24000000;
    144  1.6  jmcneill 	if (n < 0x11 || n > 0xff)
    145  1.6  jmcneill 		return EINVAL;
    146  1.6  jmcneill 
    147  1.6  jmcneill 	/* Switch cluster to OSC24M clock */
    148  1.6  jmcneill 	mutex_enter(&cpux_axi_cfg_lock);
    149  1.6  jmcneill 	val = CCU_READ(sc, CPUX_AXI_CFG_REG);
    150  1.6  jmcneill 	val &= ~Cx_CPUX_CLK_SRC_SEL(cluster);
    151  1.6  jmcneill 	CCU_WRITE(sc, CPUX_AXI_CFG_REG, val);
    152  1.6  jmcneill 	mutex_exit(&cpux_axi_cfg_lock);
    153  1.6  jmcneill 
    154  1.6  jmcneill 	/* Set new PLL rate */
    155  1.6  jmcneill 	val = CCU_READ(sc, nkmp->reg);
    156  1.6  jmcneill 	val &= ~PLL_CxCPUX_CTRL_PLL_FACTOR_N;
    157  1.6  jmcneill 	val |= __SHIFTIN(n, PLL_CxCPUX_CTRL_PLL_FACTOR_N);
    158  1.6  jmcneill 	CCU_WRITE(sc, nkmp->reg, val);
    159  1.6  jmcneill 
    160  1.6  jmcneill 	/* Wait for PLL lock */
    161  1.6  jmcneill 	while ((CCU_READ(sc, PLL_STABLE_STATUS_REG) & nkmp->lock) == 0)
    162  1.6  jmcneill 		;
    163  1.6  jmcneill 
    164  1.6  jmcneill 	/* Switch cluster back to CPUX PLL */
    165  1.6  jmcneill 	mutex_enter(&cpux_axi_cfg_lock);
    166  1.6  jmcneill 	val = CCU_READ(sc, CPUX_AXI_CFG_REG);
    167  1.6  jmcneill 	val |= Cx_CPUX_CLK_SRC_SEL(cluster);
    168  1.6  jmcneill 	CCU_WRITE(sc, CPUX_AXI_CFG_REG, val);
    169  1.6  jmcneill 	mutex_exit(&cpux_axi_cfg_lock);
    170  1.6  jmcneill 
    171  1.6  jmcneill 	return 0;
    172  1.6  jmcneill }
    173  1.6  jmcneill 
    174  1.1  jmcneill static struct sunxi_ccu_clk sun8i_a83t_ccu_clks[] = {
    175  1.6  jmcneill 	[A83T_CLK_C0CPUX] = {
    176  1.6  jmcneill 		.type = SUNXI_CCU_NKMP,
    177  1.6  jmcneill 		.base.name = "pll_c0cpux",
    178  1.6  jmcneill 		.u.nkmp.reg = PLL_C0CPUX_CTRL_REG,
    179  1.6  jmcneill 		.u.nkmp.parent = "hosc",
    180  1.6  jmcneill 		.u.nkmp.n = __BITS(15,8),
    181  1.6  jmcneill 		.u.nkmp.k = 0,
    182  1.6  jmcneill 		.u.nkmp.m = __BITS(1,0),
    183  1.6  jmcneill 		.u.nkmp.p = __BIT(16),
    184  1.6  jmcneill 		.u.nkmp.enable = __BIT(31),
    185  1.6  jmcneill 		.u.nkmp.flags = SUNXI_CCU_NKMP_SCALE_CLOCK |
    186  1.6  jmcneill 				SUNXI_CCU_NKMP_FACTOR_N_EXACT |
    187  1.6  jmcneill 				SUNXI_CCU_NKMP_FACTOR_P_X4,
    188  1.6  jmcneill 		.u.nkmp.lock = __BIT(0),	/* PLL_STABLE_STATUS_REG */
    189  1.6  jmcneill 		.u.nkmp.table = NULL,
    190  1.6  jmcneill 		.enable = sunxi_ccu_nkmp_enable,
    191  1.6  jmcneill 		.get_rate = sunxi_ccu_nkmp_get_rate,
    192  1.6  jmcneill 		.set_rate = sun8i_a83t_ccu_cpux_set_rate,
    193  1.6  jmcneill 		.get_parent = sunxi_ccu_nkmp_get_parent,
    194  1.6  jmcneill 	},
    195  1.6  jmcneill 
    196  1.6  jmcneill 	[A83T_CLK_C1CPUX] = {
    197  1.6  jmcneill 		.type = SUNXI_CCU_NKMP,
    198  1.6  jmcneill 		.base.name = "pll_c1cpux",
    199  1.6  jmcneill 		.u.nkmp.reg = PLL_C1CPUX_CTRL_REG,
    200  1.6  jmcneill 		.u.nkmp.parent = "hosc",
    201  1.6  jmcneill 		.u.nkmp.n = __BITS(15,8),
    202  1.6  jmcneill 		.u.nkmp.k = 0,
    203  1.6  jmcneill 		.u.nkmp.m = __BITS(1,0),
    204  1.6  jmcneill 		.u.nkmp.p = __BIT(16),
    205  1.6  jmcneill 		.u.nkmp.enable = __BIT(31),
    206  1.6  jmcneill 		.u.nkmp.flags = SUNXI_CCU_NKMP_SCALE_CLOCK |
    207  1.6  jmcneill 				SUNXI_CCU_NKMP_FACTOR_N_EXACT |
    208  1.6  jmcneill 				SUNXI_CCU_NKMP_FACTOR_P_X4,
    209  1.6  jmcneill 		.u.nkmp.lock = __BIT(1),	/* PLL_STABLE_STATUS_REG */
    210  1.6  jmcneill 		.u.nkmp.table = NULL,
    211  1.6  jmcneill 		.enable = sunxi_ccu_nkmp_enable,
    212  1.6  jmcneill 		.get_rate = sunxi_ccu_nkmp_get_rate,
    213  1.6  jmcneill 		.set_rate = sun8i_a83t_ccu_cpux_set_rate,
    214  1.6  jmcneill 		.get_parent = sunxi_ccu_nkmp_get_parent,
    215  1.6  jmcneill 	},
    216  1.6  jmcneill 
    217  1.2  jmcneill 	SUNXI_CCU_NKMP(A83T_CLK_PLL_PERIPH, "pll_periph", "hosc",
    218  1.2  jmcneill 	    PLL_PERIPH_CTRL_REG,	/* reg */
    219  1.1  jmcneill 	    __BITS(15,8),		/* n */
    220  1.1  jmcneill 	    0,		 		/* k */
    221  1.1  jmcneill 	    __BIT(18),			/* m */
    222  1.1  jmcneill 	    __BIT(16),			/* p */
    223  1.1  jmcneill 	    __BIT(31),			/* enable */
    224  1.1  jmcneill 	    SUNXI_CCU_NKMP_FACTOR_N_EXACT),
    225  1.1  jmcneill 
    226  1.2  jmcneill 	SUNXI_CCU_PREDIV(A83T_CLK_AHB1, "ahb1", ahb1_parents,
    227  1.1  jmcneill 	    AHB1_APB1_CFG_REG,	/* reg */
    228  1.1  jmcneill 	    __BITS(7,6),	/* prediv */
    229  1.1  jmcneill 	    __BIT(3),		/* prediv_sel */
    230  1.1  jmcneill 	    __BITS(5,4),	/* div */
    231  1.1  jmcneill 	    __BITS(13,12),	/* sel */
    232  1.1  jmcneill 	    SUNXI_CCU_PREDIV_POWER_OF_TWO),
    233  1.1  jmcneill 
    234  1.2  jmcneill 	SUNXI_CCU_PREDIV(A83T_CLK_AHB2, "ahb2", ahb2_parents,
    235  1.1  jmcneill 	    APB2_CFG_REG,	/* reg */
    236  1.1  jmcneill 	    0,			/* prediv */
    237  1.1  jmcneill 	    __BIT(1),		/* prediv_sel */
    238  1.1  jmcneill 	    0,			/* div */
    239  1.1  jmcneill 	    __BITS(1,0),	/* sel */
    240  1.1  jmcneill 	    SUNXI_CCU_PREDIV_DIVIDE_BY_TWO),
    241  1.1  jmcneill 
    242  1.2  jmcneill 	SUNXI_CCU_DIV(A83T_CLK_APB1, "apb1", apb1_parents,
    243  1.1  jmcneill 	    AHB1_APB1_CFG_REG,	/* reg */
    244  1.1  jmcneill 	    __BITS(9,8),	/* div */
    245  1.1  jmcneill 	    0,			/* sel */
    246  1.1  jmcneill 	    SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE),
    247  1.1  jmcneill 
    248  1.2  jmcneill 	SUNXI_CCU_NM(A83T_CLK_APB2, "apb2", apb2_parents,
    249  1.1  jmcneill 	    APB2_CFG_REG,	/* reg */
    250  1.1  jmcneill 	    __BITS(17,16),	/* n */
    251  1.1  jmcneill 	    __BITS(4,0),	/* m */
    252  1.1  jmcneill 	    __BITS(25,24),	/* sel */
    253  1.1  jmcneill 	    0,			/* enable */
    254  1.1  jmcneill 	    SUNXI_CCU_NM_POWER_OF_TWO),
    255  1.1  jmcneill 
    256  1.2  jmcneill 	SUNXI_CCU_NM(A83T_CLK_MMC0, "mmc0", mod_parents,
    257  1.1  jmcneill 	    SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
    258  1.1  jmcneill 	    SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
    259  1.2  jmcneill 	SUNXI_CCU_NM(A83T_CLK_MMC1, "mmc1", mod_parents,
    260  1.1  jmcneill 	    SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
    261  1.1  jmcneill 	    SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
    262  1.2  jmcneill 	SUNXI_CCU_NM(A83T_CLK_MMC2, "mmc2", mod_parents,
    263  1.1  jmcneill 	    SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
    264  1.4  jmcneill 	    SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO),
    265  1.1  jmcneill 
    266  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1",
    267  1.5  jmcneill 	    BUS_CLK_GATING_REG0, 1),
    268  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_SS, "bus-ss", "ahb1",
    269  1.5  jmcneill 	    BUS_CLK_GATING_REG0, 5),
    270  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_DMA, "bus-dma", "ahb1",
    271  1.5  jmcneill 	    BUS_CLK_GATING_REG0, 6),
    272  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
    273  1.1  jmcneill 	    BUS_CLK_GATING_REG0, 8),
    274  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
    275  1.1  jmcneill 	    BUS_CLK_GATING_REG0, 9),
    276  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
    277  1.1  jmcneill 	    BUS_CLK_GATING_REG0, 10),
    278  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_NAND, "bus-nand", "ahb1",
    279  1.5  jmcneill 	    BUS_CLK_GATING_REG0, 13),
    280  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_DRAM, "bus-dram", "ahb1",
    281  1.5  jmcneill 	    BUS_CLK_GATING_REG0, 14),
    282  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_EMAC, "bus-emac", "ahb2",
    283  1.1  jmcneill 	    BUS_CLK_GATING_REG0, 17),
    284  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1",
    285  1.5  jmcneill 	    BUS_CLK_GATING_REG0, 19),
    286  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_SPI0, "bus-spi0", "ahb1",
    287  1.5  jmcneill 	    BUS_CLK_GATING_REG0, 20),
    288  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_SPI1, "bus-spi1", "ahb1",
    289  1.5  jmcneill 	    BUS_CLK_GATING_REG0, 21),
    290  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_OTG, "bus-otg", "ahb1",
    291  1.3  jmcneill 	    BUS_CLK_GATING_REG0, 24),
    292  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI0, "bus-ehci0", "ahb1",
    293  1.3  jmcneill 	    BUS_CLK_GATING_REG0, 26),
    294  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI1, "bus-ehci1", "ahb2",
    295  1.3  jmcneill 	    BUS_CLK_GATING_REG0, 27),
    296  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_OHCI0, "bus-ohci0", "ahb1",
    297  1.3  jmcneill 	    BUS_CLK_GATING_REG0, 29),
    298  1.1  jmcneill 
    299  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_VE, "bus-ve", "ahb2",
    300  1.5  jmcneill 	    BUS_CLK_GATING_REG1, 0),
    301  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_TCON0, "bus-tcon0", "ahb2",
    302  1.5  jmcneill 	    BUS_CLK_GATING_REG1, 4),
    303  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_TCON1, "bus-tcon1", "ahb2",
    304  1.5  jmcneill 	    BUS_CLK_GATING_REG1, 5),
    305  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_CSI, "bus-csi", "ahb2",
    306  1.5  jmcneill 	    BUS_CLK_GATING_REG1, 8),
    307  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_HDMI, "bus-hdmi", "ahb2",
    308  1.5  jmcneill 	    BUS_CLK_GATING_REG1, 11),
    309  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_DE, "bus-de", "ahb2",
    310  1.5  jmcneill 	    BUS_CLK_GATING_REG1, 12),
    311  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_GPU, "bus-gpu", "ahb2",
    312  1.5  jmcneill 	    BUS_CLK_GATING_REG1, 20),
    313  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_MSGBOX, "bus-msgbox", "ahb2",
    314  1.5  jmcneill 	    BUS_CLK_GATING_REG1, 21),
    315  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb2",
    316  1.5  jmcneill 	    BUS_CLK_GATING_REG1, 22),
    317  1.5  jmcneill 
    318  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_SPDIF, "bus-spdif", "apb1",
    319  1.5  jmcneill 	    BUS_CLK_GATING_REG2, 1),
    320  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_PIO, "bus-pio", "apb1",
    321  1.1  jmcneill 	    BUS_CLK_GATING_REG2, 5),
    322  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_I2S0, "bus-i2s0", "apb1",
    323  1.5  jmcneill 	    BUS_CLK_GATING_REG2, 12),
    324  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_I2S1, "bus-i2s1", "apb1",
    325  1.5  jmcneill 	    BUS_CLK_GATING_REG2, 13),
    326  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_I2S2, "bus-i2s2", "apb1",
    327  1.5  jmcneill 	    BUS_CLK_GATING_REG2, 14),
    328  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_TDM, "bus-tdm", "apb1",
    329  1.5  jmcneill 	    BUS_CLK_GATING_REG2, 15),
    330  1.1  jmcneill 
    331  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_I2C0, "bus-i2c0", "apb2",
    332  1.1  jmcneill 	    BUS_CLK_GATING_REG3, 0),
    333  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_I2C1, "bus-i2c1", "apb2",
    334  1.1  jmcneill 	    BUS_CLK_GATING_REG3, 1),
    335  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_I2C2, "bus-i2c2", "apb2",
    336  1.1  jmcneill 	    BUS_CLK_GATING_REG3, 2),
    337  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_UART0, "bus-uart0", "apb2",
    338  1.1  jmcneill 	    BUS_CLK_GATING_REG3, 16),
    339  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_UART1, "bus-uart1", "apb2",
    340  1.1  jmcneill 	    BUS_CLK_GATING_REG3, 17),
    341  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_UART2, "bus-uart2", "apb2",
    342  1.1  jmcneill 	    BUS_CLK_GATING_REG3, 18),
    343  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_UART3, "bus-uart3", "apb2",
    344  1.1  jmcneill 	    BUS_CLK_GATING_REG3, 19),
    345  1.5  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_BUS_UART4, "bus-uart4", "apb2",
    346  1.5  jmcneill 	    BUS_CLK_GATING_REG3, 20),
    347  1.1  jmcneill 
    348  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_USB_PHY0, "usb-phy0", "hosc",
    349  1.1  jmcneill 	    USBPHY_CFG_REG, 8),
    350  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_USB_PHY1, "usb-phy1", "hosc",
    351  1.1  jmcneill 	    USBPHY_CFG_REG, 9),
    352  1.2  jmcneill 	SUNXI_CCU_GATE(A83T_CLK_USB_OHCI0, "usb-ohci0", "hosc",
    353  1.1  jmcneill 	    USBPHY_CFG_REG, 16),
    354  1.1  jmcneill };
    355  1.1  jmcneill 
    356  1.4  jmcneill static void
    357  1.4  jmcneill sun8i_a83t_ccu_init(struct sunxi_ccu_softc *sc)
    358  1.4  jmcneill {
    359  1.4  jmcneill 	uint32_t val;
    360  1.4  jmcneill 
    361  1.4  jmcneill 	/* SDMMC2 has a mode select switch. Always use "New Mode". */
    362  1.4  jmcneill 	val = CCU_READ(sc, SDMMC2_CLK_REG);
    363  1.4  jmcneill 	val |= SDMMC2_CLK_MODE_SELECT;
    364  1.4  jmcneill 	CCU_WRITE(sc, SDMMC2_CLK_REG, val);
    365  1.4  jmcneill }
    366  1.4  jmcneill 
    367  1.1  jmcneill static int
    368  1.1  jmcneill sun8i_a83t_ccu_match(device_t parent, cfdata_t cf, void *aux)
    369  1.1  jmcneill {
    370  1.1  jmcneill 	struct fdt_attach_args * const faa = aux;
    371  1.1  jmcneill 
    372  1.7   thorpej 	return of_compatible_match(faa->faa_phandle, compat_data);
    373  1.1  jmcneill }
    374  1.1  jmcneill 
    375  1.1  jmcneill static void
    376  1.1  jmcneill sun8i_a83t_ccu_attach(device_t parent, device_t self, void *aux)
    377  1.1  jmcneill {
    378  1.1  jmcneill 	struct sunxi_ccu_softc * const sc = device_private(self);
    379  1.1  jmcneill 	struct fdt_attach_args * const faa = aux;
    380  1.1  jmcneill 
    381  1.1  jmcneill 	sc->sc_dev = self;
    382  1.1  jmcneill 	sc->sc_phandle = faa->faa_phandle;
    383  1.1  jmcneill 	sc->sc_bst = faa->faa_bst;
    384  1.1  jmcneill 
    385  1.1  jmcneill 	sc->sc_resets = sun8i_a83t_ccu_resets;
    386  1.1  jmcneill 	sc->sc_nresets = __arraycount(sun8i_a83t_ccu_resets);
    387  1.1  jmcneill 
    388  1.1  jmcneill 	sc->sc_clks = sun8i_a83t_ccu_clks;
    389  1.1  jmcneill 	sc->sc_nclks = __arraycount(sun8i_a83t_ccu_clks);
    390  1.1  jmcneill 
    391  1.6  jmcneill 	mutex_init(&cpux_axi_cfg_lock, MUTEX_DEFAULT, IPL_HIGH);
    392  1.6  jmcneill 
    393  1.1  jmcneill 	if (sunxi_ccu_attach(sc) != 0)
    394  1.1  jmcneill 		return;
    395  1.1  jmcneill 
    396  1.1  jmcneill 	aprint_naive("\n");
    397  1.1  jmcneill 	aprint_normal(": A83T CCU\n");
    398  1.1  jmcneill 
    399  1.4  jmcneill 	sun8i_a83t_ccu_init(sc);
    400  1.4  jmcneill 
    401  1.1  jmcneill 	sunxi_ccu_print(sc);
    402  1.1  jmcneill }
    403