1 /* $NetBSD: sun8i_a83t_ccu.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun8i_a83t_ccu.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun8i_a83t_ccu.h> 43 44 #define PLL_C0CPUX_CTRL_REG 0x000 45 #define PLL_C1CPUX_CTRL_REG 0x004 46 #define PLL_CxCPUX_CTRL_PLL_FACTOR_N __BITS(15,8) 47 #define PLL_PERIPH_CTRL_REG 0x028 48 #define CPUX_AXI_CFG_REG 0x050 49 #define Cx_CPUX_CLK_SRC_SEL(cluster) __BIT(12 + (cluster) * 16) 50 #define AHB1_APB1_CFG_REG 0x054 51 #define APB2_CFG_REG 0x058 52 #define BUS_CLK_GATING_REG0 0x060 53 #define BUS_CLK_GATING_REG1 0x064 54 #define BUS_CLK_GATING_REG2 0x068 55 #define BUS_CLK_GATING_REG3 0x06c 56 #define SDMMC0_CLK_REG 0x088 57 #define SDMMC1_CLK_REG 0x08c 58 #define SDMMC2_CLK_REG 0x090 59 #define SDMMC2_CLK_MODE_SELECT __BIT(30) 60 #define USBPHY_CFG_REG 0x0cc 61 #define MBUS_RST_REG 0x0fc 62 #define PLL_STABLE_STATUS_REG 0x20c 63 #define BUS_SOFT_RST_REG0 0x2c0 64 #define BUS_SOFT_RST_REG1 0x2c4 65 #define BUS_SOFT_RST_REG2 0x2c8 66 #define BUS_SOFT_RST_REG3 0x2d0 67 #define BUS_SOFT_RST_REG4 0x2d8 68 69 static int sun8i_a83t_ccu_match(device_t, cfdata_t, void *); 70 static void sun8i_a83t_ccu_attach(device_t, device_t, void *); 71 72 static const struct device_compatible_entry compat_data[] = { 73 { .compat = "allwinner,sun8i-a83t-ccu" }, 74 DEVICE_COMPAT_EOL 75 }; 76 77 CFATTACH_DECL_NEW(sunxi_a83t_ccu, sizeof(struct sunxi_ccu_softc), 78 sun8i_a83t_ccu_match, sun8i_a83t_ccu_attach, NULL, NULL); 79 80 static struct sunxi_ccu_reset sun8i_a83t_ccu_resets[] = { 81 SUNXI_CCU_RESET(A83T_RST_USB_PHY0, USBPHY_CFG_REG, 0), 82 SUNXI_CCU_RESET(A83T_RST_USB_PHY1, USBPHY_CFG_REG, 1), 83 84 SUNXI_CCU_RESET(A83T_RST_MBUS, MBUS_RST_REG, 31), 85 86 SUNXI_CCU_RESET(A83T_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 87 SUNXI_CCU_RESET(A83T_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 88 SUNXI_CCU_RESET(A83T_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 89 SUNXI_CCU_RESET(A83T_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 90 SUNXI_CCU_RESET(A83T_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 91 SUNXI_CCU_RESET(A83T_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 92 SUNXI_CCU_RESET(A83T_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 93 SUNXI_CCU_RESET(A83T_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 94 SUNXI_CCU_RESET(A83T_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 95 SUNXI_CCU_RESET(A83T_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 96 SUNXI_CCU_RESET(A83T_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 97 SUNXI_CCU_RESET(A83T_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 26), 98 SUNXI_CCU_RESET(A83T_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 27), 99 SUNXI_CCU_RESET(A83T_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 29), 100 101 SUNXI_CCU_RESET(A83T_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 102 SUNXI_CCU_RESET(A83T_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 103 SUNXI_CCU_RESET(A83T_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 104 SUNXI_CCU_RESET(A83T_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 105 SUNXI_CCU_RESET(A83T_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 106 SUNXI_CCU_RESET(A83T_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 107 SUNXI_CCU_RESET(A83T_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 108 SUNXI_CCU_RESET(A83T_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 109 SUNXI_CCU_RESET(A83T_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 110 SUNXI_CCU_RESET(A83T_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 111 112 SUNXI_CCU_RESET(A83T_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 113 SUNXI_CCU_RESET(A83T_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 114 SUNXI_CCU_RESET(A83T_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 115 SUNXI_CCU_RESET(A83T_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 116 117 SUNXI_CCU_RESET(A83T_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 118 SUNXI_CCU_RESET(A83T_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 119 SUNXI_CCU_RESET(A83T_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 120 SUNXI_CCU_RESET(A83T_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 121 SUNXI_CCU_RESET(A83T_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 122 SUNXI_CCU_RESET(A83T_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 123 SUNXI_CCU_RESET(A83T_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 124 }; 125 126 static const char *ahb1_parents[] = { "losc", "hosc", "pll_periph" }; 127 static const char *ahb2_parents[] = { "ahb1", "pll_periph" }; 128 static const char *apb1_parents[] = { "ahb1" }; 129 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph" }; 130 static const char *mod_parents[] = { "hosc", "pll_periph" }; 131 132 static kmutex_t cpux_axi_cfg_lock; 133 134 static int 135 sun8i_a83t_ccu_cpux_set_rate(struct sunxi_ccu_softc *sc, 136 struct sunxi_ccu_clk *clk, u_int rate) 137 { 138 const int cluster = clk->u.nkmp.reg == PLL_C0CPUX_CTRL_REG ? 0 : 1; 139 struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp; 140 uint32_t val; 141 u_int n; 142 143 n = rate / 24000000; 144 if (n < 0x11 || n > 0xff) 145 return EINVAL; 146 147 /* Switch cluster to OSC24M clock */ 148 mutex_enter(&cpux_axi_cfg_lock); 149 val = CCU_READ(sc, CPUX_AXI_CFG_REG); 150 val &= ~Cx_CPUX_CLK_SRC_SEL(cluster); 151 CCU_WRITE(sc, CPUX_AXI_CFG_REG, val); 152 mutex_exit(&cpux_axi_cfg_lock); 153 154 /* Set new PLL rate */ 155 val = CCU_READ(sc, nkmp->reg); 156 val &= ~PLL_CxCPUX_CTRL_PLL_FACTOR_N; 157 val |= __SHIFTIN(n, PLL_CxCPUX_CTRL_PLL_FACTOR_N); 158 CCU_WRITE(sc, nkmp->reg, val); 159 160 /* Wait for PLL lock */ 161 while ((CCU_READ(sc, PLL_STABLE_STATUS_REG) & nkmp->lock) == 0) 162 ; 163 164 /* Switch cluster back to CPUX PLL */ 165 mutex_enter(&cpux_axi_cfg_lock); 166 val = CCU_READ(sc, CPUX_AXI_CFG_REG); 167 val |= Cx_CPUX_CLK_SRC_SEL(cluster); 168 CCU_WRITE(sc, CPUX_AXI_CFG_REG, val); 169 mutex_exit(&cpux_axi_cfg_lock); 170 171 return 0; 172 } 173 174 static struct sunxi_ccu_clk sun8i_a83t_ccu_clks[] = { 175 [A83T_CLK_C0CPUX] = { 176 .type = SUNXI_CCU_NKMP, 177 .base.name = "pll_c0cpux", 178 .u.nkmp.reg = PLL_C0CPUX_CTRL_REG, 179 .u.nkmp.parent = "hosc", 180 .u.nkmp.n = __BITS(15,8), 181 .u.nkmp.k = 0, 182 .u.nkmp.m = __BITS(1,0), 183 .u.nkmp.p = __BIT(16), 184 .u.nkmp.enable = __BIT(31), 185 .u.nkmp.flags = SUNXI_CCU_NKMP_SCALE_CLOCK | 186 SUNXI_CCU_NKMP_FACTOR_N_EXACT | 187 SUNXI_CCU_NKMP_FACTOR_P_X4, 188 .u.nkmp.lock = __BIT(0), /* PLL_STABLE_STATUS_REG */ 189 .u.nkmp.table = NULL, 190 .enable = sunxi_ccu_nkmp_enable, 191 .get_rate = sunxi_ccu_nkmp_get_rate, 192 .set_rate = sun8i_a83t_ccu_cpux_set_rate, 193 .get_parent = sunxi_ccu_nkmp_get_parent, 194 }, 195 196 [A83T_CLK_C1CPUX] = { 197 .type = SUNXI_CCU_NKMP, 198 .base.name = "pll_c1cpux", 199 .u.nkmp.reg = PLL_C1CPUX_CTRL_REG, 200 .u.nkmp.parent = "hosc", 201 .u.nkmp.n = __BITS(15,8), 202 .u.nkmp.k = 0, 203 .u.nkmp.m = __BITS(1,0), 204 .u.nkmp.p = __BIT(16), 205 .u.nkmp.enable = __BIT(31), 206 .u.nkmp.flags = SUNXI_CCU_NKMP_SCALE_CLOCK | 207 SUNXI_CCU_NKMP_FACTOR_N_EXACT | 208 SUNXI_CCU_NKMP_FACTOR_P_X4, 209 .u.nkmp.lock = __BIT(1), /* PLL_STABLE_STATUS_REG */ 210 .u.nkmp.table = NULL, 211 .enable = sunxi_ccu_nkmp_enable, 212 .get_rate = sunxi_ccu_nkmp_get_rate, 213 .set_rate = sun8i_a83t_ccu_cpux_set_rate, 214 .get_parent = sunxi_ccu_nkmp_get_parent, 215 }, 216 217 SUNXI_CCU_NKMP(A83T_CLK_PLL_PERIPH, "pll_periph", "hosc", 218 PLL_PERIPH_CTRL_REG, /* reg */ 219 __BITS(15,8), /* n */ 220 0, /* k */ 221 __BIT(18), /* m */ 222 __BIT(16), /* p */ 223 __BIT(31), /* enable */ 224 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 225 226 SUNXI_CCU_PREDIV(A83T_CLK_AHB1, "ahb1", ahb1_parents, 227 AHB1_APB1_CFG_REG, /* reg */ 228 __BITS(7,6), /* prediv */ 229 __BIT(3), /* prediv_sel */ 230 __BITS(5,4), /* div */ 231 __BITS(13,12), /* sel */ 232 SUNXI_CCU_PREDIV_POWER_OF_TWO), 233 234 SUNXI_CCU_PREDIV(A83T_CLK_AHB2, "ahb2", ahb2_parents, 235 APB2_CFG_REG, /* reg */ 236 0, /* prediv */ 237 __BIT(1), /* prediv_sel */ 238 0, /* div */ 239 __BITS(1,0), /* sel */ 240 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 241 242 SUNXI_CCU_DIV(A83T_CLK_APB1, "apb1", apb1_parents, 243 AHB1_APB1_CFG_REG, /* reg */ 244 __BITS(9,8), /* div */ 245 0, /* sel */ 246 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 247 248 SUNXI_CCU_NM(A83T_CLK_APB2, "apb2", apb2_parents, 249 APB2_CFG_REG, /* reg */ 250 __BITS(17,16), /* n */ 251 __BITS(4,0), /* m */ 252 __BITS(25,24), /* sel */ 253 0, /* enable */ 254 SUNXI_CCU_NM_POWER_OF_TWO), 255 256 SUNXI_CCU_NM(A83T_CLK_MMC0, "mmc0", mod_parents, 257 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 258 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 259 SUNXI_CCU_NM(A83T_CLK_MMC1, "mmc1", mod_parents, 260 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 261 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 262 SUNXI_CCU_NM(A83T_CLK_MMC2, "mmc2", mod_parents, 263 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 264 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 265 266 SUNXI_CCU_GATE(A83T_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 267 BUS_CLK_GATING_REG0, 1), 268 SUNXI_CCU_GATE(A83T_CLK_BUS_SS, "bus-ss", "ahb1", 269 BUS_CLK_GATING_REG0, 5), 270 SUNXI_CCU_GATE(A83T_CLK_BUS_DMA, "bus-dma", "ahb1", 271 BUS_CLK_GATING_REG0, 6), 272 SUNXI_CCU_GATE(A83T_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 273 BUS_CLK_GATING_REG0, 8), 274 SUNXI_CCU_GATE(A83T_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 275 BUS_CLK_GATING_REG0, 9), 276 SUNXI_CCU_GATE(A83T_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 277 BUS_CLK_GATING_REG0, 10), 278 SUNXI_CCU_GATE(A83T_CLK_BUS_NAND, "bus-nand", "ahb1", 279 BUS_CLK_GATING_REG0, 13), 280 SUNXI_CCU_GATE(A83T_CLK_BUS_DRAM, "bus-dram", "ahb1", 281 BUS_CLK_GATING_REG0, 14), 282 SUNXI_CCU_GATE(A83T_CLK_BUS_EMAC, "bus-emac", "ahb2", 283 BUS_CLK_GATING_REG0, 17), 284 SUNXI_CCU_GATE(A83T_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 285 BUS_CLK_GATING_REG0, 19), 286 SUNXI_CCU_GATE(A83T_CLK_BUS_SPI0, "bus-spi0", "ahb1", 287 BUS_CLK_GATING_REG0, 20), 288 SUNXI_CCU_GATE(A83T_CLK_BUS_SPI1, "bus-spi1", "ahb1", 289 BUS_CLK_GATING_REG0, 21), 290 SUNXI_CCU_GATE(A83T_CLK_BUS_OTG, "bus-otg", "ahb1", 291 BUS_CLK_GATING_REG0, 24), 292 SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 293 BUS_CLK_GATING_REG0, 26), 294 SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 295 BUS_CLK_GATING_REG0, 27), 296 SUNXI_CCU_GATE(A83T_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 297 BUS_CLK_GATING_REG0, 29), 298 299 SUNXI_CCU_GATE(A83T_CLK_BUS_VE, "bus-ve", "ahb2", 300 BUS_CLK_GATING_REG1, 0), 301 SUNXI_CCU_GATE(A83T_CLK_BUS_TCON0, "bus-tcon0", "ahb2", 302 BUS_CLK_GATING_REG1, 4), 303 SUNXI_CCU_GATE(A83T_CLK_BUS_TCON1, "bus-tcon1", "ahb2", 304 BUS_CLK_GATING_REG1, 5), 305 SUNXI_CCU_GATE(A83T_CLK_BUS_CSI, "bus-csi", "ahb2", 306 BUS_CLK_GATING_REG1, 8), 307 SUNXI_CCU_GATE(A83T_CLK_BUS_HDMI, "bus-hdmi", "ahb2", 308 BUS_CLK_GATING_REG1, 11), 309 SUNXI_CCU_GATE(A83T_CLK_BUS_DE, "bus-de", "ahb2", 310 BUS_CLK_GATING_REG1, 12), 311 SUNXI_CCU_GATE(A83T_CLK_BUS_GPU, "bus-gpu", "ahb2", 312 BUS_CLK_GATING_REG1, 20), 313 SUNXI_CCU_GATE(A83T_CLK_BUS_MSGBOX, "bus-msgbox", "ahb2", 314 BUS_CLK_GATING_REG1, 21), 315 SUNXI_CCU_GATE(A83T_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb2", 316 BUS_CLK_GATING_REG1, 22), 317 318 SUNXI_CCU_GATE(A83T_CLK_BUS_SPDIF, "bus-spdif", "apb1", 319 BUS_CLK_GATING_REG2, 1), 320 SUNXI_CCU_GATE(A83T_CLK_BUS_PIO, "bus-pio", "apb1", 321 BUS_CLK_GATING_REG2, 5), 322 SUNXI_CCU_GATE(A83T_CLK_BUS_I2S0, "bus-i2s0", "apb1", 323 BUS_CLK_GATING_REG2, 12), 324 SUNXI_CCU_GATE(A83T_CLK_BUS_I2S1, "bus-i2s1", "apb1", 325 BUS_CLK_GATING_REG2, 13), 326 SUNXI_CCU_GATE(A83T_CLK_BUS_I2S2, "bus-i2s2", "apb1", 327 BUS_CLK_GATING_REG2, 14), 328 SUNXI_CCU_GATE(A83T_CLK_BUS_TDM, "bus-tdm", "apb1", 329 BUS_CLK_GATING_REG2, 15), 330 331 SUNXI_CCU_GATE(A83T_CLK_BUS_I2C0, "bus-i2c0", "apb2", 332 BUS_CLK_GATING_REG3, 0), 333 SUNXI_CCU_GATE(A83T_CLK_BUS_I2C1, "bus-i2c1", "apb2", 334 BUS_CLK_GATING_REG3, 1), 335 SUNXI_CCU_GATE(A83T_CLK_BUS_I2C2, "bus-i2c2", "apb2", 336 BUS_CLK_GATING_REG3, 2), 337 SUNXI_CCU_GATE(A83T_CLK_BUS_UART0, "bus-uart0", "apb2", 338 BUS_CLK_GATING_REG3, 16), 339 SUNXI_CCU_GATE(A83T_CLK_BUS_UART1, "bus-uart1", "apb2", 340 BUS_CLK_GATING_REG3, 17), 341 SUNXI_CCU_GATE(A83T_CLK_BUS_UART2, "bus-uart2", "apb2", 342 BUS_CLK_GATING_REG3, 18), 343 SUNXI_CCU_GATE(A83T_CLK_BUS_UART3, "bus-uart3", "apb2", 344 BUS_CLK_GATING_REG3, 19), 345 SUNXI_CCU_GATE(A83T_CLK_BUS_UART4, "bus-uart4", "apb2", 346 BUS_CLK_GATING_REG3, 20), 347 348 SUNXI_CCU_GATE(A83T_CLK_USB_PHY0, "usb-phy0", "hosc", 349 USBPHY_CFG_REG, 8), 350 SUNXI_CCU_GATE(A83T_CLK_USB_PHY1, "usb-phy1", "hosc", 351 USBPHY_CFG_REG, 9), 352 SUNXI_CCU_GATE(A83T_CLK_USB_OHCI0, "usb-ohci0", "hosc", 353 USBPHY_CFG_REG, 16), 354 }; 355 356 static void 357 sun8i_a83t_ccu_init(struct sunxi_ccu_softc *sc) 358 { 359 uint32_t val; 360 361 /* SDMMC2 has a mode select switch. Always use "New Mode". */ 362 val = CCU_READ(sc, SDMMC2_CLK_REG); 363 val |= SDMMC2_CLK_MODE_SELECT; 364 CCU_WRITE(sc, SDMMC2_CLK_REG, val); 365 } 366 367 static int 368 sun8i_a83t_ccu_match(device_t parent, cfdata_t cf, void *aux) 369 { 370 struct fdt_attach_args * const faa = aux; 371 372 return of_compatible_match(faa->faa_phandle, compat_data); 373 } 374 375 static void 376 sun8i_a83t_ccu_attach(device_t parent, device_t self, void *aux) 377 { 378 struct sunxi_ccu_softc * const sc = device_private(self); 379 struct fdt_attach_args * const faa = aux; 380 381 sc->sc_dev = self; 382 sc->sc_phandle = faa->faa_phandle; 383 sc->sc_bst = faa->faa_bst; 384 385 sc->sc_resets = sun8i_a83t_ccu_resets; 386 sc->sc_nresets = __arraycount(sun8i_a83t_ccu_resets); 387 388 sc->sc_clks = sun8i_a83t_ccu_clks; 389 sc->sc_nclks = __arraycount(sun8i_a83t_ccu_clks); 390 391 mutex_init(&cpux_axi_cfg_lock, MUTEX_DEFAULT, IPL_HIGH); 392 393 if (sunxi_ccu_attach(sc) != 0) 394 return; 395 396 aprint_naive("\n"); 397 aprint_normal(": A83T CCU\n"); 398 399 sun8i_a83t_ccu_init(sc); 400 401 sunxi_ccu_print(sc); 402 } 403
Indexes created Sun Sep 21 20:09:37 GMT 2025