sun8i_a83t_ccu.c revision 1.4
1 /* $NetBSD: sun8i_a83t_ccu.c,v 1.4 2017/10/28 13:13:45 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun8i_a83t_ccu.c,v 1.4 2017/10/28 13:13:45 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun8i_a83t_ccu.h> 43 44 #define PLL_PERIPH_CTRL_REG 0x028 45 #define AHB1_APB1_CFG_REG 0x054 46 #define APB2_CFG_REG 0x058 47 #define BUS_CLK_GATING_REG0 0x060 48 #define BUS_CLK_GATING_REG2 0x068 49 #define BUS_CLK_GATING_REG3 0x06c 50 #define SDMMC0_CLK_REG 0x088 51 #define SDMMC1_CLK_REG 0x08c 52 #define SDMMC2_CLK_REG 0x090 53 #define SDMMC2_CLK_MODE_SELECT __BIT(30) 54 #define USBPHY_CFG_REG 0x0cc 55 #define MBUS_RST_REG 0x0fc 56 #define BUS_SOFT_RST_REG0 0x2c0 57 #define BUS_SOFT_RST_REG1 0x2c4 58 #define BUS_SOFT_RST_REG2 0x2c8 59 #define BUS_SOFT_RST_REG3 0x2d0 60 #define BUS_SOFT_RST_REG4 0x2d8 61 62 static int sun8i_a83t_ccu_match(device_t, cfdata_t, void *); 63 static void sun8i_a83t_ccu_attach(device_t, device_t, void *); 64 65 static const char * const compatible[] = { 66 "allwinner,sun8i-a83t-ccu", 67 NULL 68 }; 69 70 CFATTACH_DECL_NEW(sunxi_a83t_ccu, sizeof(struct sunxi_ccu_softc), 71 sun8i_a83t_ccu_match, sun8i_a83t_ccu_attach, NULL, NULL); 72 73 static struct sunxi_ccu_reset sun8i_a83t_ccu_resets[] = { 74 SUNXI_CCU_RESET(A83T_RST_USB_PHY0, USBPHY_CFG_REG, 0), 75 SUNXI_CCU_RESET(A83T_RST_USB_PHY1, USBPHY_CFG_REG, 1), 76 77 SUNXI_CCU_RESET(A83T_RST_MBUS, MBUS_RST_REG, 31), 78 79 SUNXI_CCU_RESET(A83T_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 80 SUNXI_CCU_RESET(A83T_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 81 SUNXI_CCU_RESET(A83T_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 82 SUNXI_CCU_RESET(A83T_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 83 SUNXI_CCU_RESET(A83T_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 84 SUNXI_CCU_RESET(A83T_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 85 SUNXI_CCU_RESET(A83T_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 86 SUNXI_CCU_RESET(A83T_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 87 SUNXI_CCU_RESET(A83T_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 88 SUNXI_CCU_RESET(A83T_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 89 SUNXI_CCU_RESET(A83T_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 90 SUNXI_CCU_RESET(A83T_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 26), 91 SUNXI_CCU_RESET(A83T_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 27), 92 SUNXI_CCU_RESET(A83T_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 29), 93 94 SUNXI_CCU_RESET(A83T_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 95 SUNXI_CCU_RESET(A83T_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 96 SUNXI_CCU_RESET(A83T_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 97 SUNXI_CCU_RESET(A83T_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 98 SUNXI_CCU_RESET(A83T_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 99 SUNXI_CCU_RESET(A83T_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 100 SUNXI_CCU_RESET(A83T_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 101 SUNXI_CCU_RESET(A83T_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 102 SUNXI_CCU_RESET(A83T_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 103 SUNXI_CCU_RESET(A83T_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 104 105 SUNXI_CCU_RESET(A83T_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 106 SUNXI_CCU_RESET(A83T_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 107 SUNXI_CCU_RESET(A83T_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 108 SUNXI_CCU_RESET(A83T_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 109 110 SUNXI_CCU_RESET(A83T_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 111 SUNXI_CCU_RESET(A83T_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 112 SUNXI_CCU_RESET(A83T_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 113 SUNXI_CCU_RESET(A83T_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 114 SUNXI_CCU_RESET(A83T_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 115 SUNXI_CCU_RESET(A83T_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 116 SUNXI_CCU_RESET(A83T_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 117 }; 118 119 static const char *ahb1_parents[] = { "losc", "hosc", "pll_periph" }; 120 static const char *ahb2_parents[] = { "ahb1", "pll_periph" }; 121 static const char *apb1_parents[] = { "ahb1" }; 122 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph" }; 123 static const char *mod_parents[] = { "hosc", "pll_periph" }; 124 125 static struct sunxi_ccu_clk sun8i_a83t_ccu_clks[] = { 126 SUNXI_CCU_NKMP(A83T_CLK_PLL_PERIPH, "pll_periph", "hosc", 127 PLL_PERIPH_CTRL_REG, /* reg */ 128 __BITS(15,8), /* n */ 129 0, /* k */ 130 __BIT(18), /* m */ 131 __BIT(16), /* p */ 132 __BIT(31), /* enable */ 133 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 134 135 SUNXI_CCU_PREDIV(A83T_CLK_AHB1, "ahb1", ahb1_parents, 136 AHB1_APB1_CFG_REG, /* reg */ 137 __BITS(7,6), /* prediv */ 138 __BIT(3), /* prediv_sel */ 139 __BITS(5,4), /* div */ 140 __BITS(13,12), /* sel */ 141 SUNXI_CCU_PREDIV_POWER_OF_TWO), 142 143 SUNXI_CCU_PREDIV(A83T_CLK_AHB2, "ahb2", ahb2_parents, 144 APB2_CFG_REG, /* reg */ 145 0, /* prediv */ 146 __BIT(1), /* prediv_sel */ 147 0, /* div */ 148 __BITS(1,0), /* sel */ 149 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 150 151 SUNXI_CCU_DIV(A83T_CLK_APB1, "apb1", apb1_parents, 152 AHB1_APB1_CFG_REG, /* reg */ 153 __BITS(9,8), /* div */ 154 0, /* sel */ 155 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 156 157 SUNXI_CCU_NM(A83T_CLK_APB2, "apb2", apb2_parents, 158 APB2_CFG_REG, /* reg */ 159 __BITS(17,16), /* n */ 160 __BITS(4,0), /* m */ 161 __BITS(25,24), /* sel */ 162 0, /* enable */ 163 SUNXI_CCU_NM_POWER_OF_TWO), 164 165 SUNXI_CCU_NM(A83T_CLK_MMC0, "mmc0", mod_parents, 166 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 167 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 168 SUNXI_CCU_NM(A83T_CLK_MMC1, "mmc1", mod_parents, 169 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 170 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 171 SUNXI_CCU_NM(A83T_CLK_MMC2, "mmc2", mod_parents, 172 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 173 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 174 175 SUNXI_CCU_GATE(A83T_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 176 BUS_CLK_GATING_REG0, 8), 177 SUNXI_CCU_GATE(A83T_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 178 BUS_CLK_GATING_REG0, 9), 179 SUNXI_CCU_GATE(A83T_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 180 BUS_CLK_GATING_REG0, 10), 181 SUNXI_CCU_GATE(A83T_CLK_BUS_EMAC, "bus-emac", "ahb2", 182 BUS_CLK_GATING_REG0, 17), 183 SUNXI_CCU_GATE(A83T_CLK_BUS_OTG, "bus-otg", "ahb1", 184 BUS_CLK_GATING_REG0, 24), 185 SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 186 BUS_CLK_GATING_REG0, 26), 187 SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 188 BUS_CLK_GATING_REG0, 27), 189 SUNXI_CCU_GATE(A83T_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 190 BUS_CLK_GATING_REG0, 29), 191 192 SUNXI_CCU_GATE(A83T_CLK_BUS_PIO, "bus-pio", "apb1", 193 BUS_CLK_GATING_REG2, 5), 194 195 SUNXI_CCU_GATE(A83T_CLK_BUS_I2C0, "bus-i2c0", "apb2", 196 BUS_CLK_GATING_REG3, 0), 197 SUNXI_CCU_GATE(A83T_CLK_BUS_I2C1, "bus-i2c1", "apb2", 198 BUS_CLK_GATING_REG3, 1), 199 SUNXI_CCU_GATE(A83T_CLK_BUS_I2C2, "bus-i2c2", "apb2", 200 BUS_CLK_GATING_REG3, 2), 201 SUNXI_CCU_GATE(A83T_CLK_BUS_UART0, "bus-uart0", "apb2", 202 BUS_CLK_GATING_REG3, 16), 203 SUNXI_CCU_GATE(A83T_CLK_BUS_UART1, "bus-uart1", "apb2", 204 BUS_CLK_GATING_REG3, 17), 205 SUNXI_CCU_GATE(A83T_CLK_BUS_UART2, "bus-uart2", "apb2", 206 BUS_CLK_GATING_REG3, 18), 207 SUNXI_CCU_GATE(A83T_CLK_BUS_UART3, "bus-uart3", "apb2", 208 BUS_CLK_GATING_REG3, 19), 209 210 SUNXI_CCU_GATE(A83T_CLK_USB_PHY0, "usb-phy0", "hosc", 211 USBPHY_CFG_REG, 8), 212 SUNXI_CCU_GATE(A83T_CLK_USB_PHY1, "usb-phy1", "hosc", 213 USBPHY_CFG_REG, 9), 214 SUNXI_CCU_GATE(A83T_CLK_USB_OHCI0, "usb-ohci0", "hosc", 215 USBPHY_CFG_REG, 16), 216 }; 217 218 static void 219 sun8i_a83t_ccu_init(struct sunxi_ccu_softc *sc) 220 { 221 uint32_t val; 222 223 /* SDMMC2 has a mode select switch. Always use "New Mode". */ 224 val = CCU_READ(sc, SDMMC2_CLK_REG); 225 val |= SDMMC2_CLK_MODE_SELECT; 226 CCU_WRITE(sc, SDMMC2_CLK_REG, val); 227 } 228 229 static int 230 sun8i_a83t_ccu_match(device_t parent, cfdata_t cf, void *aux) 231 { 232 struct fdt_attach_args * const faa = aux; 233 234 return of_match_compatible(faa->faa_phandle, compatible); 235 } 236 237 static void 238 sun8i_a83t_ccu_attach(device_t parent, device_t self, void *aux) 239 { 240 struct sunxi_ccu_softc * const sc = device_private(self); 241 struct fdt_attach_args * const faa = aux; 242 243 sc->sc_dev = self; 244 sc->sc_phandle = faa->faa_phandle; 245 sc->sc_bst = faa->faa_bst; 246 247 sc->sc_resets = sun8i_a83t_ccu_resets; 248 sc->sc_nresets = __arraycount(sun8i_a83t_ccu_resets); 249 250 sc->sc_clks = sun8i_a83t_ccu_clks; 251 sc->sc_nclks = __arraycount(sun8i_a83t_ccu_clks); 252 253 if (sunxi_ccu_attach(sc) != 0) 254 return; 255 256 aprint_naive("\n"); 257 aprint_normal(": A83T CCU\n"); 258 259 sun8i_a83t_ccu_init(sc); 260 261 sunxi_ccu_print(sc); 262 } 263
Indexes created Sat Sep 27 14:09:57 GMT 2025