sunxi_hdmiphy.c revision 1.1
1 /* $NetBSD: sunxi_hdmiphy.c,v 1.1 2019/01/30 01:24:00 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: sunxi_hdmiphy.c,v 1.1 2019/01/30 01:24:00 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_hdmiphy.h> 42 43 #define DBG_CTRL 0x000 44 #define DBG_CTRL_POL __BITS(15,8) 45 #define DBG_CTRL_POL_NVSYNC 1 46 #define DBG_CTRL_POL_NHSYNC 2 47 48 #define READ_EN 0x010 49 #define READ_EN_MAGIC 0x54524545 /* "TREE" */ 50 51 #define UNSCRAMBLE 0x014 52 #define UNSCRAMBLE_MAGIC 0x42494E47 /* "BING" */ 53 54 #define ANA_CFG1 0x020 55 #define ANA_CFG1_ENRCAL __BIT(19) 56 #define ANA_CFG1_ENCALOG __BIT(18) 57 #define ANA_CFG1_TMDSCLK_EN __BIT(16) 58 #define ANA_CFG1_TXEN __BITS(15,12) 59 #define ANA_CFG1_BIASEN __BITS(11,8) 60 #define ANA_CFG1_ENP2S __BITS(7,4) 61 #define ANA_CFG1_CKEN __BIT(3) 62 #define ANA_CFG1_LDOEN __BIT(2) 63 #define ANA_CFG1_ENVBS __BIT(1) 64 #define ANA_CFG1_ENBI __BIT(0) 65 66 #define ANA_CFG2 0x024 67 #define ANA_CFG2_REG_RESDI __BITS(5,0) 68 69 #define ANA_CFG3 0x028 70 #define ANA_CFG3_REG_SDAEN __BIT(2) 71 #define ANA_CFG3_REG_SCLEN __BIT(0) 72 73 #define PLL_CFG1 0x02c 74 #define PLL_CFG1_REG_OD1 __BIT(31) 75 #define PLL_CFG1_REG_OD0 __BIT(30) 76 #define PLL_CFG1_CKIN_SEL __BIT(26) 77 #define PLL_CFG1_PLLEN __BIT(25) 78 #define PLL_CFG1_B_IN __BITS(5,0) 79 80 #define PLL_CFG2 0x030 81 #define PLL_CFG2_PREDIV __BITS(3,0) 82 83 #define PLL_CFG3 0x034 84 85 #define ANA_STS 0x038 86 #define ANA_STS_HPDO __BIT(19) 87 #define ANA_STS_B_OUT __BITS(16,11) 88 #define ANA_STS_RCALEND2D __BIT(7) 89 #define ANA_STS_RESDO2D __BITS(5,0) 90 91 #define CEC 0x03c 92 #define CEC_CONTROL_SEL __BIT(7) 93 #define CEC_INPUT_DATA __BIT(1) 94 #define CEC_OUTPUT_DATA __BIT(0) 95 96 #define CONTROLLER_VER 0xff8 97 98 #define PHY_VER 0xffc 99 100 struct sunxi_hdmiphy_softc; 101 102 static int sunxi_hdmiphy_match(device_t, cfdata_t, void *); 103 static void sunxi_hdmiphy_attach(device_t, device_t, void *); 104 105 static void sun50i_a64_hdmiphy_init(struct sunxi_hdmiphy_softc *); 106 static int sun50i_a64_hdmiphy_config(struct sunxi_hdmiphy_softc *, u_int); 107 108 struct sunxi_hdmiphy_data { 109 void (*init)(struct sunxi_hdmiphy_softc *); 110 int (*config)(struct sunxi_hdmiphy_softc *, u_int); 111 }; 112 113 static const struct sunxi_hdmiphy_data sun50i_a64_hdmiphy_data = { 114 .init = sun50i_a64_hdmiphy_init, 115 .config = sun50i_a64_hdmiphy_config, 116 }; 117 118 static const struct of_compat_data compat_data[] = { 119 { "allwinner,sun50i-a64-hdmi-phy", (uintptr_t)&sun50i_a64_hdmiphy_data }, 120 { NULL } 121 }; 122 123 struct sunxi_hdmiphy_softc { 124 device_t sc_dev; 125 bus_space_tag_t sc_bst; 126 bus_space_handle_t sc_bsh; 127 128 const struct sunxi_hdmiphy_data *sc_data; 129 130 struct clk *sc_clk_pll0; 131 132 u_int sc_rcalib; 133 }; 134 135 #define PHY_READ(sc, reg) \ 136 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 137 #define PHY_WRITE(sc, reg, val) \ 138 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 139 #define PHY_SET_CLEAR(sc, reg, set, clr) \ 140 do { \ 141 uint32_t _tval = PHY_READ((sc), (reg)); \ 142 _tval &= ~(clr); \ 143 _tval |= (set); \ 144 PHY_WRITE((sc), (reg), _tval); \ 145 } while (0) 146 #define PHY_SET(sc, reg, set) \ 147 PHY_SET_CLEAR(sc, reg, set, 0) 148 #define PHY_CLEAR(sc, reg, clr) \ 149 PHY_SET_CLEAR(sc, reg, 0, clr) 150 151 CFATTACH_DECL_NEW(sunxi_hdmiphy, sizeof(struct sunxi_hdmiphy_softc), 152 sunxi_hdmiphy_match, sunxi_hdmiphy_attach, NULL, NULL); 153 154 static void * 155 sunxi_hdmiphy_acquire(device_t dev, const void *data, size_t len) 156 { 157 struct sunxi_hdmiphy_softc * const sc = device_private(dev); 158 159 if (len != 0) 160 return NULL; 161 162 return sc; 163 } 164 165 static void 166 sunxi_hdmiphy_release(device_t dev, void *priv) 167 { 168 } 169 170 static int 171 sunxi_hdmiphy_enable(device_t dev, void *priv, bool enable) 172 { 173 struct sunxi_hdmiphy_softc * const sc = priv; 174 175 if (enable) { 176 sc->sc_data->init(sc); 177 } else { 178 sc->sc_data->config(sc, 0); 179 } 180 181 return 0; 182 } 183 184 static const struct fdtbus_phy_controller_func sunxi_hdmiphy_funcs = { 185 .acquire = sunxi_hdmiphy_acquire, 186 .release = sunxi_hdmiphy_release, 187 .enable = sunxi_hdmiphy_enable, 188 }; 189 190 #ifdef SUNXI_HDMIPHY_DEBUG 191 static void 192 sunxi_hdmiphy_dump(struct sunxi_hdmiphy_softc *sc) 193 { 194 device_printf(sc->sc_dev, "ANA_CFG1: %#x\tANA_CFG2: %#x\tANA_CFG3: %#x\n", 195 PHY_READ(sc, ANA_CFG1), PHY_READ(sc, ANA_CFG2), PHY_READ(sc, ANA_CFG3)); 196 device_printf(sc->sc_dev, "PLL_CFG1: %#x\tPLL_CFG2: %#x\tPLL_CFG3: %#x\n", 197 PHY_READ(sc, PLL_CFG1), PHY_READ(sc, PLL_CFG2), PHY_READ(sc, PLL_CFG3)); 198 device_printf(sc->sc_dev, "DBG_CTRL: %#x\tANA_STS: %#x\n", 199 PHY_READ(sc, DBG_CTRL), PHY_READ(sc, ANA_STS)); 200 } 201 #endif 202 203 static void 204 sun50i_a64_hdmiphy_init(struct sunxi_hdmiphy_softc *sc) 205 { 206 uint32_t val; 207 int retry; 208 209 PHY_WRITE(sc, ANA_CFG1, 0); 210 211 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENBI); 212 delay(5); 213 214 /* Enable TMDS clock */ 215 PHY_SET(sc, ANA_CFG1, ANA_CFG1_TMDSCLK_EN); 216 217 /* Enable common voltage reference bias module */ 218 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENVBS); 219 delay(20); 220 221 /* Enable internal LDO */ 222 PHY_SET(sc, ANA_CFG1, ANA_CFG1_LDOEN); 223 delay(5); 224 225 /* Enable common clock module */ 226 PHY_SET(sc, ANA_CFG1, ANA_CFG1_CKEN); 227 delay(100); 228 229 /* Enable resistance calibration analog and digital modules */ 230 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENRCAL); 231 delay(200); 232 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENCALOG); 233 234 /* P2S module enable for TMDS data lane */ 235 PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0x7, ANA_CFG1_ENP2S), ANA_CFG1_ENP2S); 236 237 /* Wait for resistance calibration to finish */ 238 for (retry = 2000; retry > 0; retry--) { 239 if ((PHY_READ(sc, ANA_STS) & ANA_STS_RCALEND2D) != 0) 240 break; 241 delay(1); 242 } 243 if (retry == 0) 244 aprint_error_dev(sc->sc_dev, "HDMI PHY resistance calibration timed out\n"); 245 246 /* Enable current and voltage module */ 247 PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0xf, ANA_CFG1_BIASEN), ANA_CFG1_BIASEN); 248 249 /* P2S module enable for TMDS clock lane */ 250 PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0xf, ANA_CFG1_ENP2S), ANA_CFG1_ENP2S); 251 252 /* Enable DDC */ 253 PHY_SET(sc, ANA_CFG3, ANA_CFG3_REG_SDAEN | ANA_CFG3_REG_SCLEN); 254 255 /* Set parent clock to videopll0 */ 256 PHY_CLEAR(sc, PLL_CFG1, PLL_CFG1_CKIN_SEL); 257 258 /* Clear software control of CEC pins */ 259 PHY_CLEAR(sc, CEC, CEC_CONTROL_SEL); 260 261 /* Read calibration value for source termination resistors */ 262 val = PHY_READ(sc, ANA_STS); 263 sc->sc_rcalib = __SHIFTOUT(val, ANA_STS_RESDO2D); 264 } 265 266 /* 267 * The following table is based on data from the "HDMI TX PHY S40 Specification". 268 */ 269 static const struct sun50i_a64_hdmiphy_init { 270 /* PLL Recommended Configuration */ 271 uint32_t pll_cfg1; 272 uint32_t pll_cfg2; 273 uint32_t pll_cfg3; 274 /* TMDS Characteristics Recommended Configuration */ 275 uint32_t ana_cfg1; 276 uint32_t ana_cfg2; 277 uint32_t ana_cfg3; 278 bool ana_cfg2_rcal_200; 279 u_int b_offset; 280 } sun50i_a64_hdmiphy_inittab[] = { 281 /* 27 MHz */ 282 [0] = { 283 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x8008430a, .pll_cfg3 = 0x1, 284 .ana_cfg1 = 0x11ffff7f, .ana_cfg2 = 0x80623000, .ana_cfg3 = 0x0f80c285, 285 .ana_cfg2_rcal_200 = true, 286 }, 287 /* 74.25 MHz */ 288 [1] = { 289 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084343, .pll_cfg3 = 0x1, 290 .ana_cfg1 = 0x11ffff7f, .ana_cfg2 = 0x80623000, .ana_cfg3 = 0x0f814385, 291 .ana_cfg2_rcal_200 = true, 292 }, 293 /* 148.5 MHz */ 294 [2] = { 295 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084381, .pll_cfg3 = 0x1, 296 .ana_cfg1 = 0x01ffff7f, .ana_cfg2 = 0x8063a800, .ana_cfg3 = 0x0f81c485, 297 }, 298 /* 297 MHz */ 299 [3] = { 300 .pll_cfg1 = 0x35dc5fc0, .pll_cfg2 = 0x800863c0, .pll_cfg3 = 0x1, 301 .ana_cfg1 = 0x01ffff7f, .ana_cfg2 = 0x8063b000, .ana_cfg3 = 0x0f8246b5, 302 .b_offset = 2, 303 }, 304 }; 305 306 static int 307 sun50i_a64_hdmiphy_config(struct sunxi_hdmiphy_softc *sc, u_int rate) 308 { 309 const struct sun50i_a64_hdmiphy_init *inittab; 310 u_int init_index, b_out, prediv; 311 uint32_t val, rcalib; 312 313 if (rate == 0) { 314 /* Disable the PHY */ 315 PHY_WRITE(sc, ANA_CFG1, ANA_CFG1_LDOEN | ANA_CFG1_ENVBS | ANA_CFG1_ENBI); 316 PHY_WRITE(sc, PLL_CFG1, 0); 317 return 0; 318 } 319 320 init_index = 0; 321 if (rate > 27000000) 322 init_index++; 323 if (rate > 74250000) 324 init_index++; 325 if (rate > 148500000) 326 init_index++; 327 inittab = &sun50i_a64_hdmiphy_inittab[init_index]; 328 329 val = PHY_READ(sc, PLL_CFG2); 330 prediv = val & PLL_CFG2_PREDIV; 331 332 /* Config PLL */ 333 PHY_WRITE(sc, PLL_CFG1, inittab->pll_cfg1 & ~PLL_CFG1_CKIN_SEL); 334 PHY_WRITE(sc, PLL_CFG2, (inittab->pll_cfg2 & ~PLL_CFG2_PREDIV) | prediv); 335 delay(15000); 336 PHY_WRITE(sc, PLL_CFG3, inittab->pll_cfg3); 337 338 /* Enable PLL */ 339 PHY_SET(sc, PLL_CFG1, PLL_CFG1_PLLEN); 340 delay(100000); 341 342 /* Config PLL */ 343 val = PHY_READ(sc, ANA_STS); 344 b_out = __SHIFTOUT(val, ANA_STS_B_OUT); 345 b_out = MIN(b_out + inittab->b_offset, __SHIFTOUT_MASK(ANA_STS_B_OUT)); 346 347 PHY_SET(sc, PLL_CFG1, PLL_CFG1_REG_OD1 | PLL_CFG1_REG_OD0); 348 PHY_SET(sc, PLL_CFG1, __SHIFTIN(b_out, PLL_CFG1_B_IN)); 349 delay(100000); 350 351 /* Config TMDS characteristics */ 352 if (inittab->ana_cfg2_rcal_200) 353 rcalib = sc->sc_rcalib >> 2; 354 else 355 rcalib = 0; 356 PHY_WRITE(sc, ANA_CFG1, inittab->ana_cfg1); 357 PHY_WRITE(sc, ANA_CFG2, inittab->ana_cfg2 | rcalib); 358 PHY_WRITE(sc, ANA_CFG3, inittab->ana_cfg3); 359 360 #ifdef SUNXI_HDMIPHY_DEBUG 361 sunxi_hdmiphy_dump(sc); 362 #endif 363 364 return 0; 365 } 366 367 static int 368 sunxi_hdmiphy_set_rate(struct sunxi_hdmiphy_softc *sc, u_int new_rate) 369 { 370 u_int prediv, best_prediv, best_rate; 371 372 if (sc->sc_clk_pll0 == NULL) 373 return 0; 374 375 const u_int parent_rate = clk_get_rate(sc->sc_clk_pll0); 376 377 best_rate = 0; 378 379 for (prediv = 0; prediv <= __SHIFTOUT_MASK(PLL_CFG2_PREDIV); prediv++) { 380 const u_int tmp_rate = parent_rate / (prediv + 1); 381 const int diff = new_rate - tmp_rate; 382 if (diff >= 0 && tmp_rate > best_rate) { 383 best_rate = tmp_rate; 384 best_prediv = prediv; 385 } 386 } 387 388 if (best_rate == 0) 389 return ERANGE; 390 391 PHY_SET_CLEAR(sc, PLL_CFG2, __SHIFTIN(best_prediv, PLL_CFG2_PREDIV), PLL_CFG2_PREDIV); 392 393 return 0; 394 } 395 396 static int 397 sunxi_hdmiphy_match(device_t parent, cfdata_t cf, void *aux) 398 { 399 struct fdt_attach_args * const faa = aux; 400 401 return of_match_compat_data(faa->faa_phandle, compat_data); 402 } 403 404 static void 405 sunxi_hdmiphy_attach(device_t parent, device_t self, void *aux) 406 { 407 struct sunxi_hdmiphy_softc * const sc = device_private(self); 408 struct fdt_attach_args * const faa = aux; 409 const int phandle = faa->faa_phandle; 410 struct clk *clk_bus, *clk_mod, *clk_pll0; 411 struct fdtbus_reset *rst; 412 bus_addr_t addr; 413 bus_size_t size; 414 415 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 416 aprint_error(": couldn't get registers\n"); 417 return; 418 } 419 420 rst = fdtbus_reset_get(phandle, "phy"); 421 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) { 422 aprint_error(": couldn't de-assert reset\n"); 423 return; 424 } 425 426 clk_bus = fdtbus_clock_get(phandle, "bus"); 427 if (clk_bus == NULL || clk_enable(clk_bus) != 0) { 428 aprint_error(": couldn't enable bus clock\n"); 429 return; 430 } 431 432 clk_mod = fdtbus_clock_get(phandle, "mod"); 433 if (clk_mod == NULL || clk_enable(clk_mod) != 0) { 434 aprint_error(": couldn't enable mod clock\n"); 435 return; 436 } 437 438 clk_pll0 = fdtbus_clock_get(phandle, "pll-0"); 439 if (clk_pll0 == NULL || clk_enable(clk_pll0) != 0) { 440 aprint_error(": couldn't enable pll-0 clock\n"); 441 return; 442 } 443 444 sc->sc_dev = self; 445 sc->sc_bst = faa->faa_bst; 446 sc->sc_data = (void *)of_search_compatible(phandle, compat_data)->data; 447 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 448 aprint_error(": couldn't map registers\n"); 449 return; 450 } 451 sc->sc_clk_pll0 = clk_pll0; 452 453 aprint_naive("\n"); 454 aprint_normal(": HDMI PHY\n"); 455 456 fdtbus_register_phy_controller(self, phandle, &sunxi_hdmiphy_funcs); 457 458 PHY_WRITE(sc, READ_EN, READ_EN_MAGIC); 459 PHY_WRITE(sc, UNSCRAMBLE, UNSCRAMBLE_MAGIC); 460 461 #ifdef SUNXI_HDMIPHY_DEBUG 462 sunxi_hdmiphy_dump(sc); 463 #endif 464 } 465 466 int 467 sunxi_hdmiphy_config(struct fdtbus_phy *phy, struct drm_display_mode *mode) 468 { 469 device_t dev = fdtbus_phy_device(phy); 470 struct sunxi_hdmiphy_softc * const sc = device_private(dev); 471 u_int pol; 472 int error; 473 474 pol = 0; 475 if ((mode->flags & DRM_MODE_FLAG_NHSYNC) != 0) 476 pol |= __SHIFTIN(DBG_CTRL_POL_NHSYNC, DBG_CTRL_POL); 477 if ((mode->flags & DRM_MODE_FLAG_NVSYNC) != 0) 478 pol |= __SHIFTIN(DBG_CTRL_POL_NVSYNC, DBG_CTRL_POL); 479 480 PHY_SET_CLEAR(sc, DBG_CTRL, pol, DBG_CTRL_POL); 481 482 error = sunxi_hdmiphy_set_rate(sc, mode->crtc_clock * 1000); 483 if (error != 0) { 484 aprint_error_dev(dev, "failed to set HDMI PHY clock: %d\n", error); 485 return error; 486 } 487 488 return sc->sc_data->config(sc, mode->crtc_clock * 1000); 489 } 490 491 bool 492 sunxi_hdmiphy_detect(struct fdtbus_phy *phy, bool force) 493 { 494 device_t dev = fdtbus_phy_device(phy); 495 struct sunxi_hdmiphy_softc * const sc = device_private(dev); 496 uint32_t val; 497 498 val = PHY_READ(sc, ANA_STS); 499 500 return ISSET(val, ANA_STS_HPDO); 501 } 502
Indexes created Tue Sep 30 20:09:53 GMT 2025