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History log of /src/sys/arch/arm/sunxi/sunxi_hdmiphy.c
RevisionDateAuthorComments
 1.8  27-Jan-2021  thorpej Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().

Standardize on of_compatible_match() for driver matching, and adapt
all call sites.
 1.7  27-Jan-2021  thorpej Use DEVICE_COMPAT_EOL.
 1.6  25-Jan-2021  thorpej Since we're using designated initialisers for compat data, we should
use a completely empty initializer for the sentinel.
 1.5  18-Jan-2021  thorpej Remove "struct of_compat_data" and replace its usage with
"struct device_compatible_entry"; they are ABI-compatible.

Fix several "loses const qualifier" bugs encountered during
this conversion.
 1.4  23-Nov-2019  jmcneill branches: 1.4.8;
Need to initialize the PHY before HPD sense and DDC will work
 1.3  23-Nov-2019  jmcneill HDMI PHY and TX share the same clocks. Do not enable clocks until both
reset resources have been deasserted. Explicitly set DDC clock dividers.
 1.2  31-Jan-2019  jmcneill branches: 1.2.4; 1.2.6;
Add support for Allwinner H3/H5 display pipeline.
 1.1  30-Jan-2019  jmcneill Add support for Allwinner A64's display pipeline.
 1.2.6.1  25-Nov-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #470):

sys/arch/arm/sunxi/sunxi_hdmiphy.c: revision 1.4
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.16
sys/dev/ic/dw_hdmi.c: revision 1.5
sys/arch/arm/sunxi/sunxi_hdmiphy.h: revision 1.2
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.17
sys/dev/ic/dw_hdmi.c: revision 1.6
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.18
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.19
sys/dev/ic/dw_hdmi.h: revision 1.5
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.8
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.9
sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.22
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.5
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.6
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.7
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.8
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.20
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.10
sys/arch/arm/dts/sun50i-a64-pinebook.dts: revision 1.17
sys/arch/arm/sunxi/sunxi_platform.c: revision 1.38
sys/dev/fdt/fdt_port.c: revision 1.3
sys/dev/fdt/fdt_port.c: revision 1.4
sys/arch/arm/sunxi/sunxi_ccu_fractional.c: revision 1.5
sys/arch/arm/sunxi/sunxi_lcdc.c: revision 1.7
sys/arch/arm/sunxi/sunxi_ccu_fractional.c: revision 1.6
sys/arch/arm/sunxi/sunxi_hdmiphy.c: revision 1.3

Fix CLK_BUS_HDMI bit

Enable TMDS clock

Store the flags passed to SUNXI_CCU_FRACTIONAL macro.
Previously the macro dropped the flags argument entirely, and did not
initialize the structure with it.

Allow bus glue to setup DDC clocks

Add TCON0 clock

HDMI PHY and TX share the same clocks. Do not enable clocks until both
reset resources have been deasserted. Explicitly set DDC clock dividers.
Honour SUNXI_CCU_FRACTIONAL_SET_ENABLE in fractional mode

Use fdtbus_get_reg to read "reg" property

Need to initialize the PHY before HPD sense and DDC will work

Set pixel clock on mode set

Set TCON1 parent to PLL_VIDEO1(1X)

Do not assume that an fb's pitch is width * 4 bytes.

Use actual hw mode, not proposed mode.

Set pre-divider M to 0 in fractional mode, as noted in user manual. Spotted by jak.

Support non-zero fb start pixels.

Set video PLLs to 297MHz

Do not assume the cursor pitch is the same as the primary fb

Enable HDMI and HDMI audio

Try to avoid changing hardware settings when the "nomodeset" kernel arg
is present.
 1.2.4.3  08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.4.2  10-Jun-2019  christos Sync with HEAD
 1.2.4.1  31-Jan-2019  christos file sunxi_hdmiphy.c was added on branch phil-wifi on 2019-06-10 22:05:56 +0000
 1.4.8.1  03-Apr-2021  thorpej Sync with HEAD.

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