sunxi_hdmiphy.c revision 1.3
1 /* $NetBSD: sunxi_hdmiphy.c,v 1.3 2019/11/23 12:30:45 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: sunxi_hdmiphy.c,v 1.3 2019/11/23 12:30:45 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_hdmiphy.h> 42 43 #define DBG_CTRL 0x000 44 #define DBG_CTRL_POL __BITS(15,8) 45 #define DBG_CTRL_POL_NVSYNC 1 46 #define DBG_CTRL_POL_NHSYNC 2 47 48 #define READ_EN 0x010 49 #define READ_EN_MAGIC 0x54524545 /* "TREE" */ 50 51 #define UNSCRAMBLE 0x014 52 #define UNSCRAMBLE_MAGIC 0x42494E47 /* "BING" */ 53 54 #define ANA_CFG1 0x020 55 #define ANA_CFG1_ENRCAL __BIT(19) 56 #define ANA_CFG1_ENCALOG __BIT(18) 57 #define ANA_CFG1_TMDSCLK_EN __BIT(16) 58 #define ANA_CFG1_TXEN __BITS(15,12) 59 #define ANA_CFG1_BIASEN __BITS(11,8) 60 #define ANA_CFG1_ENP2S __BITS(7,4) 61 #define ANA_CFG1_CKEN __BIT(3) 62 #define ANA_CFG1_LDOEN __BIT(2) 63 #define ANA_CFG1_ENVBS __BIT(1) 64 #define ANA_CFG1_ENBI __BIT(0) 65 66 #define ANA_CFG2 0x024 67 #define ANA_CFG2_REG_RESDI __BITS(5,0) 68 69 #define ANA_CFG3 0x028 70 #define ANA_CFG3_REG_SDAEN __BIT(2) 71 #define ANA_CFG3_REG_SCLEN __BIT(0) 72 73 #define PLL_CFG1 0x02c 74 #define PLL_CFG1_REG_OD1 __BIT(31) 75 #define PLL_CFG1_REG_OD0 __BIT(30) 76 #define PLL_CFG1_CKIN_SEL __BIT(26) 77 #define PLL_CFG1_PLLEN __BIT(25) 78 #define PLL_CFG1_B_IN __BITS(5,0) 79 80 #define PLL_CFG2 0x030 81 #define PLL_CFG2_PREDIV __BITS(3,0) 82 83 #define PLL_CFG3 0x034 84 85 #define ANA_STS 0x038 86 #define ANA_STS_HPDO __BIT(19) 87 #define ANA_STS_B_OUT __BITS(16,11) 88 #define ANA_STS_RCALEND2D __BIT(7) 89 #define ANA_STS_RESDO2D __BITS(5,0) 90 91 #define CEC 0x03c 92 #define CEC_CONTROL_SEL __BIT(7) 93 #define CEC_INPUT_DATA __BIT(1) 94 #define CEC_OUTPUT_DATA __BIT(0) 95 96 #define CONTROLLER_VER 0xff8 97 98 #define PHY_VER 0xffc 99 100 struct sunxi_hdmiphy_softc; 101 102 static int sunxi_hdmiphy_match(device_t, cfdata_t, void *); 103 static void sunxi_hdmiphy_attach(device_t, device_t, void *); 104 105 static void sun8i_h3_hdmiphy_init(struct sunxi_hdmiphy_softc *); 106 static int sun8i_h3_hdmiphy_config(struct sunxi_hdmiphy_softc *, u_int); 107 108 struct sunxi_hdmiphy_data { 109 void (*init)(struct sunxi_hdmiphy_softc *); 110 int (*config)(struct sunxi_hdmiphy_softc *, u_int); 111 }; 112 113 static const struct sunxi_hdmiphy_data sun8i_h3_hdmiphy_data = { 114 .init = sun8i_h3_hdmiphy_init, 115 .config = sun8i_h3_hdmiphy_config, 116 }; 117 118 static const struct of_compat_data compat_data[] = { 119 { "allwinner,sun8i-h3-hdmi-phy", (uintptr_t)&sun8i_h3_hdmiphy_data }, 120 { "allwinner,sun50i-a64-hdmi-phy", (uintptr_t)&sun8i_h3_hdmiphy_data }, 121 { NULL } 122 }; 123 124 struct sunxi_hdmiphy_softc { 125 device_t sc_dev; 126 bus_space_tag_t sc_bst; 127 bus_space_handle_t sc_bsh; 128 129 const struct sunxi_hdmiphy_data *sc_data; 130 131 struct clk *sc_clk_bus; 132 struct clk *sc_clk_mod; 133 struct clk *sc_clk_pll0; 134 135 u_int sc_rcalib; 136 }; 137 138 #define PHY_READ(sc, reg) \ 139 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 140 #define PHY_WRITE(sc, reg, val) \ 141 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 142 #define PHY_SET_CLEAR(sc, reg, set, clr) \ 143 do { \ 144 uint32_t _tval = PHY_READ((sc), (reg)); \ 145 _tval &= ~(clr); \ 146 _tval |= (set); \ 147 PHY_WRITE((sc), (reg), _tval); \ 148 } while (0) 149 #define PHY_SET(sc, reg, set) \ 150 PHY_SET_CLEAR(sc, reg, set, 0) 151 #define PHY_CLEAR(sc, reg, clr) \ 152 PHY_SET_CLEAR(sc, reg, 0, clr) 153 154 CFATTACH_DECL_NEW(sunxi_hdmiphy, sizeof(struct sunxi_hdmiphy_softc), 155 sunxi_hdmiphy_match, sunxi_hdmiphy_attach, NULL, NULL); 156 157 static void * 158 sunxi_hdmiphy_acquire(device_t dev, const void *data, size_t len) 159 { 160 struct sunxi_hdmiphy_softc * const sc = device_private(dev); 161 162 if (len != 0) 163 return NULL; 164 165 return sc; 166 } 167 168 static void 169 sunxi_hdmiphy_release(device_t dev, void *priv) 170 { 171 } 172 173 static int 174 sunxi_hdmiphy_enable(device_t dev, void *priv, bool enable) 175 { 176 struct sunxi_hdmiphy_softc * const sc = priv; 177 178 if (enable) { 179 sc->sc_data->init(sc); 180 } else { 181 sc->sc_data->config(sc, 0); 182 } 183 184 return 0; 185 } 186 187 static const struct fdtbus_phy_controller_func sunxi_hdmiphy_funcs = { 188 .acquire = sunxi_hdmiphy_acquire, 189 .release = sunxi_hdmiphy_release, 190 .enable = sunxi_hdmiphy_enable, 191 }; 192 193 #ifdef SUNXI_HDMIPHY_DEBUG 194 static void 195 sunxi_hdmiphy_dump(struct sunxi_hdmiphy_softc *sc) 196 { 197 device_printf(sc->sc_dev, "ANA_CFG1: %#x\tANA_CFG2: %#x\tANA_CFG3: %#x\n", 198 PHY_READ(sc, ANA_CFG1), PHY_READ(sc, ANA_CFG2), PHY_READ(sc, ANA_CFG3)); 199 device_printf(sc->sc_dev, "PLL_CFG1: %#x\tPLL_CFG2: %#x\tPLL_CFG3: %#x\n", 200 PHY_READ(sc, PLL_CFG1), PHY_READ(sc, PLL_CFG2), PHY_READ(sc, PLL_CFG3)); 201 device_printf(sc->sc_dev, "DBG_CTRL: %#x\tANA_STS: %#x\n", 202 PHY_READ(sc, DBG_CTRL), PHY_READ(sc, ANA_STS)); 203 } 204 #endif 205 206 static void 207 sun8i_h3_hdmiphy_init(struct sunxi_hdmiphy_softc *sc) 208 { 209 uint32_t val; 210 int retry; 211 212 PHY_WRITE(sc, ANA_CFG1, 0); 213 214 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENBI); 215 delay(5); 216 217 /* Enable TMDS clock */ 218 PHY_SET(sc, ANA_CFG1, ANA_CFG1_TMDSCLK_EN); 219 220 /* Enable common voltage reference bias module */ 221 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENVBS); 222 delay(20); 223 224 /* Enable internal LDO */ 225 PHY_SET(sc, ANA_CFG1, ANA_CFG1_LDOEN); 226 delay(5); 227 228 /* Enable common clock module */ 229 PHY_SET(sc, ANA_CFG1, ANA_CFG1_CKEN); 230 delay(100); 231 232 /* Enable resistance calibration analog and digital modules */ 233 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENRCAL); 234 delay(200); 235 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENCALOG); 236 237 /* P2S module enable for TMDS data lane */ 238 PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0x7, ANA_CFG1_ENP2S), ANA_CFG1_ENP2S); 239 240 /* Wait for resistance calibration to finish */ 241 for (retry = 2000; retry > 0; retry--) { 242 if ((PHY_READ(sc, ANA_STS) & ANA_STS_RCALEND2D) != 0) 243 break; 244 delay(1); 245 } 246 if (retry == 0) 247 aprint_error_dev(sc->sc_dev, "HDMI PHY resistance calibration timed out\n"); 248 249 /* Enable current and voltage module */ 250 PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0xf, ANA_CFG1_BIASEN), ANA_CFG1_BIASEN); 251 252 /* P2S module enable for TMDS clock lane */ 253 PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0xf, ANA_CFG1_ENP2S), ANA_CFG1_ENP2S); 254 255 /* Enable DDC */ 256 PHY_SET(sc, ANA_CFG3, ANA_CFG3_REG_SDAEN | ANA_CFG3_REG_SCLEN); 257 258 /* Set parent clock to videopll0 */ 259 PHY_CLEAR(sc, PLL_CFG1, PLL_CFG1_CKIN_SEL); 260 261 /* Clear software control of CEC pins */ 262 PHY_CLEAR(sc, CEC, CEC_CONTROL_SEL); 263 264 /* Read calibration value for source termination resistors */ 265 val = PHY_READ(sc, ANA_STS); 266 sc->sc_rcalib = __SHIFTOUT(val, ANA_STS_RESDO2D); 267 } 268 269 /* 270 * The following table is based on data from the "HDMI TX PHY S40 Specification". 271 */ 272 static const struct sun8i_h3_hdmiphy_init { 273 /* PLL Recommended Configuration */ 274 uint32_t pll_cfg1; 275 uint32_t pll_cfg2; 276 uint32_t pll_cfg3; 277 /* TMDS Characteristics Recommended Configuration */ 278 uint32_t ana_cfg1; 279 uint32_t ana_cfg2; 280 uint32_t ana_cfg3; 281 bool ana_cfg2_rcal_200; 282 u_int b_offset; 283 } sun8i_h3_hdmiphy_inittab[] = { 284 /* 27 MHz */ 285 [0] = { 286 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x8008430a, .pll_cfg3 = 0x1, 287 .ana_cfg1 = 0x11ffff7f, .ana_cfg2 = 0x80623000, .ana_cfg3 = 0x0f80c285, 288 .ana_cfg2_rcal_200 = true, 289 }, 290 /* 74.25 MHz */ 291 [1] = { 292 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084343, .pll_cfg3 = 0x1, 293 .ana_cfg1 = 0x11ffff7f, .ana_cfg2 = 0x80623000, .ana_cfg3 = 0x0f814385, 294 .ana_cfg2_rcal_200 = true, 295 }, 296 /* 148.5 MHz */ 297 [2] = { 298 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084381, .pll_cfg3 = 0x1, 299 .ana_cfg1 = 0x01ffff7f, .ana_cfg2 = 0x8063a800, .ana_cfg3 = 0x0f81c485, 300 }, 301 /* 297 MHz */ 302 [3] = { 303 .pll_cfg1 = 0x35dc5fc0, .pll_cfg2 = 0x800863c0, .pll_cfg3 = 0x1, 304 .ana_cfg1 = 0x01ffff7f, .ana_cfg2 = 0x8063b000, .ana_cfg3 = 0x0f8246b5, 305 .b_offset = 2, 306 }, 307 }; 308 309 static int 310 sun8i_h3_hdmiphy_config(struct sunxi_hdmiphy_softc *sc, u_int rate) 311 { 312 const struct sun8i_h3_hdmiphy_init *inittab; 313 u_int init_index, b_out, prediv; 314 uint32_t val, rcalib; 315 316 if (rate == 0) { 317 /* Disable the PHY */ 318 PHY_WRITE(sc, ANA_CFG1, ANA_CFG1_LDOEN | ANA_CFG1_ENVBS | ANA_CFG1_ENBI); 319 PHY_WRITE(sc, PLL_CFG1, 0); 320 return 0; 321 } 322 323 init_index = 0; 324 if (rate > 27000000) 325 init_index++; 326 if (rate > 74250000) 327 init_index++; 328 if (rate > 148500000) 329 init_index++; 330 inittab = &sun8i_h3_hdmiphy_inittab[init_index]; 331 332 val = PHY_READ(sc, PLL_CFG2); 333 prediv = val & PLL_CFG2_PREDIV; 334 335 /* Config PLL */ 336 PHY_WRITE(sc, PLL_CFG1, inittab->pll_cfg1 & ~PLL_CFG1_CKIN_SEL); 337 PHY_WRITE(sc, PLL_CFG2, (inittab->pll_cfg2 & ~PLL_CFG2_PREDIV) | prediv); 338 delay(15000); 339 PHY_WRITE(sc, PLL_CFG3, inittab->pll_cfg3); 340 341 /* Enable PLL */ 342 PHY_SET(sc, PLL_CFG1, PLL_CFG1_PLLEN); 343 delay(100000); 344 345 /* Config PLL */ 346 val = PHY_READ(sc, ANA_STS); 347 b_out = __SHIFTOUT(val, ANA_STS_B_OUT); 348 b_out = MIN(b_out + inittab->b_offset, __SHIFTOUT_MASK(ANA_STS_B_OUT)); 349 350 PHY_SET(sc, PLL_CFG1, PLL_CFG1_REG_OD1 | PLL_CFG1_REG_OD0); 351 PHY_SET(sc, PLL_CFG1, __SHIFTIN(b_out, PLL_CFG1_B_IN)); 352 delay(100000); 353 354 /* Config TMDS characteristics */ 355 if (inittab->ana_cfg2_rcal_200) 356 rcalib = sc->sc_rcalib >> 2; 357 else 358 rcalib = 0; 359 PHY_WRITE(sc, ANA_CFG1, inittab->ana_cfg1); 360 PHY_WRITE(sc, ANA_CFG2, inittab->ana_cfg2 | rcalib); 361 PHY_WRITE(sc, ANA_CFG3, inittab->ana_cfg3); 362 363 #ifdef SUNXI_HDMIPHY_DEBUG 364 sunxi_hdmiphy_dump(sc); 365 #endif 366 367 return 0; 368 } 369 370 static int 371 sunxi_hdmiphy_set_rate(struct sunxi_hdmiphy_softc *sc, u_int new_rate) 372 { 373 u_int prediv, best_prediv, best_rate; 374 375 if (sc->sc_clk_pll0 == NULL) 376 return 0; 377 378 const u_int parent_rate = clk_get_rate(sc->sc_clk_pll0); 379 380 best_rate = 0; 381 382 for (prediv = 0; prediv <= __SHIFTOUT_MASK(PLL_CFG2_PREDIV); prediv++) { 383 const u_int tmp_rate = parent_rate / (prediv + 1); 384 const int diff = new_rate - tmp_rate; 385 if (diff >= 0 && tmp_rate > best_rate) { 386 best_rate = tmp_rate; 387 best_prediv = prediv; 388 } 389 } 390 391 if (best_rate == 0) 392 return ERANGE; 393 394 PHY_SET_CLEAR(sc, PLL_CFG2, __SHIFTIN(best_prediv, PLL_CFG2_PREDIV), PLL_CFG2_PREDIV); 395 396 return 0; 397 } 398 399 static int 400 sunxi_hdmiphy_match(device_t parent, cfdata_t cf, void *aux) 401 { 402 struct fdt_attach_args * const faa = aux; 403 404 return of_match_compat_data(faa->faa_phandle, compat_data); 405 } 406 407 static void 408 sunxi_hdmiphy_attach(device_t parent, device_t self, void *aux) 409 { 410 struct sunxi_hdmiphy_softc * const sc = device_private(self); 411 struct fdt_attach_args * const faa = aux; 412 const int phandle = faa->faa_phandle; 413 struct clk *clk_bus, *clk_mod, *clk_pll0; 414 struct fdtbus_reset *rst; 415 bus_addr_t addr; 416 bus_size_t size; 417 418 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 419 aprint_error(": couldn't get registers\n"); 420 return; 421 } 422 423 rst = fdtbus_reset_get(phandle, "phy"); 424 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) { 425 aprint_error(": couldn't de-assert reset\n"); 426 return; 427 } 428 429 clk_bus = fdtbus_clock_get(phandle, "bus"); 430 clk_mod = fdtbus_clock_get(phandle, "mod"); 431 clk_pll0 = fdtbus_clock_get(phandle, "pll-0"); 432 if (clk_bus == NULL || clk_mod == NULL || clk_pll0 == NULL) { 433 aprint_error(": couldn't get clocks\n"); 434 return; 435 } 436 437 sc->sc_dev = self; 438 sc->sc_bst = faa->faa_bst; 439 sc->sc_data = (void *)of_search_compatible(phandle, compat_data)->data; 440 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 441 aprint_error(": couldn't map registers\n"); 442 return; 443 } 444 sc->sc_clk_bus = clk_bus; 445 sc->sc_clk_mod = clk_mod; 446 sc->sc_clk_pll0 = clk_pll0; 447 448 aprint_naive("\n"); 449 aprint_normal(": HDMI PHY\n"); 450 451 fdtbus_register_phy_controller(self, phandle, &sunxi_hdmiphy_funcs); 452 } 453 454 void 455 sunxi_hdmiphy_init(struct fdtbus_phy *phy) 456 { 457 device_t dev = fdtbus_phy_device(phy); 458 struct sunxi_hdmiphy_softc * const sc = device_private(dev); 459 460 clk_enable(sc->sc_clk_bus); 461 clk_enable(sc->sc_clk_mod); 462 clk_enable(sc->sc_clk_pll0); 463 464 PHY_WRITE(sc, READ_EN, READ_EN_MAGIC); 465 PHY_WRITE(sc, UNSCRAMBLE, UNSCRAMBLE_MAGIC); 466 467 #ifdef SUNXI_HDMIPHY_DEBUG 468 sunxi_hdmiphy_dump(sc); 469 #endif 470 } 471 472 int 473 sunxi_hdmiphy_config(struct fdtbus_phy *phy, struct drm_display_mode *mode) 474 { 475 device_t dev = fdtbus_phy_device(phy); 476 struct sunxi_hdmiphy_softc * const sc = device_private(dev); 477 u_int pol; 478 int error; 479 480 pol = 0; 481 if ((mode->flags & DRM_MODE_FLAG_NHSYNC) != 0) 482 pol |= __SHIFTIN(DBG_CTRL_POL_NHSYNC, DBG_CTRL_POL); 483 if ((mode->flags & DRM_MODE_FLAG_NVSYNC) != 0) 484 pol |= __SHIFTIN(DBG_CTRL_POL_NVSYNC, DBG_CTRL_POL); 485 486 PHY_SET_CLEAR(sc, DBG_CTRL, pol, DBG_CTRL_POL); 487 488 error = sunxi_hdmiphy_set_rate(sc, mode->crtc_clock * 1000); 489 if (error != 0) { 490 aprint_error_dev(dev, "failed to set HDMI PHY clock: %d\n", error); 491 return error; 492 } 493 494 return sc->sc_data->config(sc, mode->crtc_clock * 1000); 495 } 496 497 bool 498 sunxi_hdmiphy_detect(struct fdtbus_phy *phy, bool force) 499 { 500 device_t dev = fdtbus_phy_device(phy); 501 struct sunxi_hdmiphy_softc * const sc = device_private(dev); 502 uint32_t val; 503 504 val = PHY_READ(sc, ANA_STS); 505 506 return ISSET(val, ANA_STS_HPDO); 507 } 508
Indexes created Tue Sep 30 11:09:46 GMT 2025