sunxi_nmi.c revision 1.4
1 /* $NetBSD: sunxi_nmi.c,v 1.4 2020/01/07 10:20:07 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define _INTR_PRIVATE 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_nmi.c,v 1.4 2020/01/07 10:20:07 skrll Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 #include <sys/lwp.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <arm/cpu.h> 45 #include <arm/pic/picvar.h> 46 #include <arm/fdt/arm_fdtvar.h> 47 48 /* ctrl_reg */ 49 #define NMI_CTRL_IRQ_LOW_LEVEL 0 50 #define NMI_CTRL_IRQ_LOW_EDGE 1 51 #define NMI_CTRL_IRQ_HIGH_LEVEL 2 52 #define NMI_CTRL_IRQ_HIGH_EDGE 3 53 #define NMI_CTRL_IRQ_TYPE __BITS(1,0) 54 55 /* pend_reg */ 56 #define NMI_PEND_IRQ_ACK __BIT(0) 57 58 /* enable_reg */ 59 #define NMI_ENABLE_IRQEN __BIT(0) 60 61 struct sunxi_nmi_config { 62 const char * name; 63 bus_size_t ctrl_reg; 64 bus_size_t pend_reg; 65 bus_size_t enable_reg; 66 }; 67 68 static const struct sunxi_nmi_config sun7i_a20_sc_nmi_config = { 69 .name = "NMI", 70 .ctrl_reg = 0x00, 71 .pend_reg = 0x04, 72 .enable_reg = 0x08, 73 }; 74 75 static const struct sunxi_nmi_config sun6i_a31_r_intc_config = { 76 .name = "R_INTC", 77 .ctrl_reg = 0x0c, 78 .pend_reg = 0x10, 79 .enable_reg = 0x40, 80 }; 81 82 static const struct sunxi_nmi_config sun9i_a80_nmi_config = { 83 .name = "NMI", 84 .ctrl_reg = 0x00, 85 .pend_reg = 0x04, 86 .enable_reg = 0x08, 87 }; 88 89 static const struct of_compat_data compat_data[] = { 90 { "allwinner,sun7i-a20-sc-nmi", (uintptr_t)&sun7i_a20_sc_nmi_config }, 91 { "allwinner,sun6i-a31-r-intc", (uintptr_t)&sun6i_a31_r_intc_config }, 92 { "allwinner,sun9i-a80-nmi", (uintptr_t)&sun9i_a80_nmi_config }, 93 { NULL } 94 }; 95 96 struct sunxi_nmi_softc { 97 device_t sc_dev; 98 bus_space_tag_t sc_bst; 99 bus_space_handle_t sc_bsh; 100 int sc_phandle; 101 102 const struct sunxi_nmi_config *sc_config; 103 104 int (*sc_func)(void *); 105 void *sc_arg; 106 }; 107 108 #define NMI_READ(sc, reg) \ 109 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 110 #define NMI_WRITE(sc, reg, val) \ 111 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 112 113 static void 114 sunxi_nmi_irq_ack(struct sunxi_nmi_softc *sc) 115 { 116 uint32_t val; 117 118 val = NMI_READ(sc, sc->sc_config->pend_reg); 119 val |= NMI_PEND_IRQ_ACK; 120 NMI_WRITE(sc, sc->sc_config->pend_reg, val); 121 } 122 123 static void 124 sunxi_nmi_irq_enable(struct sunxi_nmi_softc *sc, bool on) 125 { 126 uint32_t val; 127 128 val = NMI_READ(sc, sc->sc_config->enable_reg); 129 if (on) 130 val |= NMI_ENABLE_IRQEN; 131 else 132 val &= ~NMI_ENABLE_IRQEN; 133 NMI_WRITE(sc, sc->sc_config->enable_reg, val); 134 } 135 136 static void 137 sunxi_nmi_irq_set_type(struct sunxi_nmi_softc *sc, u_int irq_type) 138 { 139 uint32_t val; 140 141 val = NMI_READ(sc, sc->sc_config->ctrl_reg); 142 val &= ~NMI_CTRL_IRQ_TYPE; 143 val |= __SHIFTIN(irq_type, NMI_CTRL_IRQ_TYPE); 144 NMI_WRITE(sc, sc->sc_config->ctrl_reg, val); 145 } 146 147 static int 148 sunxi_nmi_intr(void *priv) 149 { 150 struct sunxi_nmi_softc * const sc = priv; 151 int rv = 0; 152 153 if (sc->sc_func) 154 rv = sc->sc_func(sc->sc_arg); 155 156 sunxi_nmi_irq_ack(sc); 157 158 return rv; 159 } 160 161 static void * 162 sunxi_nmi_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 163 int (*func)(void *), void *arg) 164 { 165 struct sunxi_nmi_softc * const sc = device_private(dev); 166 u_int irq_type; 167 168 /* 1st cell is the interrupt number */ 169 const u_int irq = be32toh(specifier[0]); 170 /* 2nd cell is polarity */ 171 const u_int pol = be32toh(specifier[1]); 172 173 if (sc->sc_func != NULL) { 174 #ifdef DIAGNOSTIC 175 device_printf(dev, "%s in use\n", sc->sc_config->name); 176 #endif 177 return NULL; 178 } 179 180 if (irq != 0) { 181 #ifdef DIAGNOSTIC 182 device_printf(dev, "IRQ %u is invalid\n", irq); 183 #endif 184 return NULL; 185 } 186 187 switch (pol & 0x7) { 188 case 1: /* IRQ_TYPE_EDGE_RISING */ 189 irq_type = NMI_CTRL_IRQ_HIGH_EDGE; 190 break; 191 case 2: /* IRQ_TYPE_EDGE_FALLING */ 192 irq_type = NMI_CTRL_IRQ_LOW_EDGE; 193 break; 194 case 3: /* IRQ_TYPE_LEVEL_HIGH */ 195 irq_type = NMI_CTRL_IRQ_HIGH_LEVEL; 196 break; 197 case 4: /* IRQ_TYPE_LEVEL_LOW */ 198 irq_type = NMI_CTRL_IRQ_LOW_LEVEL; 199 break; 200 default: 201 irq_type = NMI_CTRL_IRQ_LOW_LEVEL; 202 break; 203 } 204 205 sc->sc_func = func; 206 sc->sc_arg = arg; 207 208 sunxi_nmi_irq_set_type(sc, irq_type); 209 sunxi_nmi_irq_enable(sc, true); 210 211 return fdtbus_intr_establish(sc->sc_phandle, 0, ipl, flags, 212 sunxi_nmi_intr, sc); 213 } 214 215 static void 216 sunxi_nmi_fdt_disestablish(device_t dev, void *ih) 217 { 218 struct sunxi_nmi_softc * const sc = device_private(dev); 219 220 sunxi_nmi_irq_enable(sc, false); 221 222 fdtbus_intr_disestablish(sc->sc_phandle, ih); 223 224 sc->sc_func = NULL; 225 sc->sc_arg = NULL; 226 } 227 228 static bool 229 sunxi_nmi_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 230 { 231 struct sunxi_nmi_softc * const sc = device_private(dev); 232 233 snprintf(buf, buflen, "%s", sc->sc_config->name); 234 235 return true; 236 } 237 238 static const struct fdtbus_interrupt_controller_func sunxi_nmi_fdt_funcs = { 239 .establish = sunxi_nmi_fdt_establish, 240 .disestablish = sunxi_nmi_fdt_disestablish, 241 .intrstr = sunxi_nmi_fdt_intrstr, 242 }; 243 244 static int 245 sunxi_nmi_match(device_t parent, cfdata_t cf, void *aux) 246 { 247 struct fdt_attach_args * const faa = aux; 248 249 return of_match_compat_data(faa->faa_phandle, compat_data); 250 } 251 252 static void 253 sunxi_nmi_attach(device_t parent, device_t self, void *aux) 254 { 255 struct sunxi_nmi_softc * const sc = device_private(self); 256 struct fdt_attach_args * const faa = aux; 257 const int phandle = faa->faa_phandle; 258 bus_addr_t addr; 259 bus_size_t size; 260 int error; 261 262 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 263 aprint_error(": couldn't get registers\n"); 264 return; 265 } 266 267 sc->sc_dev = self; 268 sc->sc_phandle = phandle; 269 sc->sc_config = (void *)of_search_compatible(phandle, compat_data)->data; 270 sc->sc_bst = faa->faa_bst; 271 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 272 aprint_error(": couldn't map registers\n"); 273 return; 274 } 275 276 aprint_naive("\n"); 277 aprint_normal(": %s\n", sc->sc_config->name); 278 279 sunxi_nmi_irq_enable(sc, false); 280 sunxi_nmi_irq_ack(sc); 281 282 error = fdtbus_register_interrupt_controller(self, phandle, 283 &sunxi_nmi_fdt_funcs); 284 if (error) { 285 aprint_error_dev(self, "couldn't register with fdtbus: %d\n", 286 error); 287 return; 288 } 289 } 290 291 CFATTACH_DECL_NEW(sunxi_nmi, sizeof(struct sunxi_nmi_softc), 292 sunxi_nmi_match, sunxi_nmi_attach, NULL, NULL); 293
Indexes created Sun Oct 19 02:09:48 GMT 2025