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sunxi_usbphy.c revision 1.10 
      1 /* $NetBSD: sunxi_usbphy.c,v 1.10 2017/10/28 12:56:27 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 
     31 __KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.10 2017/10/28 12:56:27 jmcneill Exp $");
     32 
     33 #include <sys/param.h>
     34 #include <sys/bus.h>
     35 #include <sys/device.h>
     36 #include <sys/intr.h>
     37 #include <sys/systm.h>
     38 #include <sys/time.h>
     39 
     40 #include <dev/fdt/fdtvar.h>
     41 
     42 /* PHY control registers */
     43 #define	PHYCTL_ICR		0x00
     44 #define	 PHYCTL_ICR_ID_PULLUP	__BIT(17)
     45 #define	 PHYCTL_ICR_DPDM_PULLUP	__BIT(16)
     46 #define	 PHYCTL_ICR_FORCE_ID	__BITS(15,14)
     47 #define	  PHYCTL_ICR_FORCE_ID_LOW	2
     48 #define	  PHYCTL_ICR_FORCE_ID_HIGH	3
     49 #define	 PHYCTL_ICR_FORCE_VBUS	__BITS(13,12)
     50 #define	  PHYCTL_ICR_FORCE_VBUS_LOW	2
     51 #define	  PHYCTL_ICR_FORCE_VBUS_HIGH	3
     52 #define	PHYCTL_A10		0x04
     53 #define	PHYCTL_A33		0x10
     54 #define	 PHYCTL_ADDR		__BITS(15,8)
     55 #define	 PHYCTL_DATA		__BIT(7)
     56 #define	PHYCTL_OTG_CFG		0x20
     57 #define	 PHYCTL_OTG_ROUTE_OTG	__BIT(0)
     58 
     59 /* PHY registers */
     60 #define	PHY_RES45_CAL_EN	0x0c
     61 #define	PHY_TX_AMPLITUDE_TUNE	0x20
     62 #define	PHY_DISCON_TH_SEL	0x2a
     63 
     64 /* PMU registers */
     65 #define	PMU_CFG			0x00
     66 #define	 AHB_INCR8		__BIT(10)
     67 #define	 AHB_INCR4		__BIT(9)
     68 #define	 AHB_INCRX_ALIGN	__BIT(8)
     69 #define	 ULPI_BYPASS		__BIT(0)
     70 #define	PMU_UNK_H3		0x10
     71 #define	 PMU_UNK_H3_CLR		__BIT(1)
     72 
     73 static int sunxi_usbphy_match(device_t, cfdata_t, void *);
     74 static void sunxi_usbphy_attach(device_t, device_t, void *);
     75 
     76 enum sunxi_usbphy_type {
     77 	USBPHY_A10 = 1,
     78 	USBPHY_A13,
     79 	USBPHY_A20,
     80 	USBPHY_A31,
     81 	USBPHY_A64,
     82 	USBPHY_A83T,
     83 	USBPHY_H3,
     84 };
     85 
     86 static const struct of_compat_data compat_data[] = {
     87 	{ "allwinner,sun4i-a10-usb-phy",	USBPHY_A10 },
     88 	{ "allwinner,sun5i-a13-usb-phy",	USBPHY_A13 },
     89 	{ "allwinner,sun6i-a31-usb-phy",	USBPHY_A31 },
     90 	{ "allwinner,sun7i-a20-usb-phy",	USBPHY_A20 },
     91 	{ "allwinner,sun8i-a83t-usb-phy",	USBPHY_A83T },
     92 	{ "allwinner,sun8i-h3-usb-phy",		USBPHY_H3 },
     93 	{ "allwinner,sun50i-a64-usb-phy",	USBPHY_A64 },
     94 	{ NULL }
     95 };
     96 
     97 #define	SUNXI_MAXUSBPHY		4
     98 
     99 struct sunxi_usbphy {
    100 	u_int			phy_index;
    101 	bus_space_handle_t	phy_bsh;
    102 	struct fdtbus_regulator *phy_reg;
    103 };
    104 
    105 struct sunxi_usbphy_softc {
    106 	device_t		sc_dev;
    107 	bus_space_tag_t		sc_bst;
    108 	bus_space_handle_t	sc_bsh_phy_ctrl;
    109 	enum sunxi_usbphy_type	sc_type;
    110 
    111 	struct sunxi_usbphy	sc_phys[SUNXI_MAXUSBPHY];
    112 	u_int			sc_nphys;
    113 
    114 	struct fdtbus_gpio_pin	*sc_gpio_id_det;
    115 	struct fdtbus_gpio_pin	*sc_gpio_vbus_det;
    116 };
    117 
    118 #define	PHYCTL_READ(sc, reg)				\
    119 	bus_space_read_4((sc)->sc_bst,			\
    120 	    (sc)->sc_bsh_phy_ctrl, (reg))
    121 #define	PHYCTL_WRITE(sc, reg, val)			\
    122 	bus_space_write_4((sc)->sc_bst,			\
    123 	    (sc)->sc_bsh_phy_ctrl, (reg), (val))
    124 #define	PMU_READ(sc, id, reg)			\
    125 	bus_space_read_4((sc)->sc_bst,			\
    126 	    (sc)->sc_phys[(id)].phy_bsh, (reg))
    127 #define	PMU_WRITE(sc, id, reg, val)			\
    128 	bus_space_write_4((sc)->sc_bst,			\
    129 	    (sc)->sc_phys[(id)].phy_bsh, (reg), (val))
    130 
    131 CFATTACH_DECL_NEW(sunxi_usbphy, sizeof(struct sunxi_usbphy_softc),
    132 	sunxi_usbphy_match, sunxi_usbphy_attach, NULL, NULL);
    133 
    134 static void
    135 sunxi_usbphy_write(struct sunxi_usbphy_softc *sc,
    136     struct sunxi_usbphy *phy, u_int bit_addr, u_int bits,
    137     u_int len)
    138 {
    139 	const uint32_t usbc_mask = __BIT(phy->phy_index * 2);;
    140 	bus_size_t reg;
    141 	uint32_t val;
    142 
    143 	switch (sc->sc_type) {
    144 	case USBPHY_A10:
    145 	case USBPHY_A13:
    146 	case USBPHY_A20:
    147 	case USBPHY_A31:
    148 		reg = PHYCTL_A10;
    149 		break;
    150 	case USBPHY_H3:
    151 	case USBPHY_A64:
    152 	case USBPHY_A83T:
    153 		reg = PHYCTL_A33;
    154 		break;
    155 	default:
    156 		panic("unsupported phy type");
    157 	}
    158 
    159 	if (reg == PHYCTL_A33)
    160 		PHYCTL_WRITE(sc, reg, 0);
    161 
    162 	for (; len > 0; bit_addr++, bits >>= 1, len--) {
    163 		val = PHYCTL_READ(sc, reg);
    164 		val &= ~PHYCTL_ADDR;
    165 		val |= __SHIFTIN(bit_addr, PHYCTL_ADDR);
    166 		PHYCTL_WRITE(sc, reg, val);
    167 
    168 		val = PHYCTL_READ(sc, reg);
    169 		val &= ~PHYCTL_DATA;
    170 		val |= __SHIFTIN(bits & 1, PHYCTL_DATA);
    171 		PHYCTL_WRITE(sc, reg, val);
    172 
    173 		PHYCTL_READ(sc, reg);
    174 		val |= usbc_mask;
    175 		PHYCTL_WRITE(sc, reg, val);
    176 
    177 		PHYCTL_READ(sc, reg);
    178 		val &= ~usbc_mask;
    179 		PHYCTL_WRITE(sc, reg, val);
    180 	}
    181 }
    182 
    183 static bool
    184 sunxi_usbphy_vbus_detect(struct sunxi_usbphy_softc *sc)
    185 {
    186 	if (sc->sc_gpio_vbus_det)
    187 		return fdtbus_gpio_read(sc->sc_gpio_vbus_det);
    188 	return 1;
    189 }
    190 
    191 static void *
    192 sunxi_usbphy_acquire(device_t dev, const void *data, size_t len)
    193 {
    194 	struct sunxi_usbphy_softc * const sc = device_private(dev);
    195 
    196 	if (len != 4)
    197 		return NULL;
    198 
    199 	const int phy_id = be32dec(data);
    200 	if (phy_id >= sc->sc_nphys)
    201 		return NULL;
    202 
    203 	return &sc->sc_phys[phy_id];
    204 }
    205 
    206 static void
    207 sunxi_usbphy_release(device_t dev, void *priv)
    208 {
    209 }
    210 
    211 static int
    212 sunxi_usbphy_enable(device_t dev, void *priv, bool enable)
    213 {
    214 	struct sunxi_usbphy_softc * const sc = device_private(dev);
    215 	struct sunxi_usbphy * const phy = priv;
    216 	u_int disc_thresh;
    217 	bool phy0_reroute;
    218 	uint32_t val;
    219 
    220 	switch (sc->sc_type) {
    221 	case USBPHY_A13:
    222 		disc_thresh = 0x2;
    223 		phy0_reroute = false;
    224 		break;
    225 	case USBPHY_A10:
    226 	case USBPHY_A20:
    227 	case USBPHY_A31:
    228 		disc_thresh = 0x3;
    229 		phy0_reroute = false;
    230 		break;
    231 	case USBPHY_A64:
    232 	case USBPHY_H3:
    233 		disc_thresh = 0x3;
    234 		phy0_reroute = true;
    235 		break;
    236 	case USBPHY_A83T:
    237 		disc_thresh = 0x0;
    238 		phy0_reroute = false;
    239 		break;
    240 	default:
    241 		aprint_error_dev(dev, "unsupported board\n");
    242 		return ENXIO;
    243 	}
    244 
    245 	if (phy->phy_bsh) {
    246 		/* Enable/disable passby */
    247 		const uint32_t mask =
    248 		    ULPI_BYPASS|AHB_INCR8|AHB_INCR4|AHB_INCRX_ALIGN;
    249 		val = PMU_READ(sc, phy->phy_index, PMU_CFG);
    250 		if (enable)
    251 			val |= mask;
    252 		else
    253 			val &= ~mask;
    254 		PMU_WRITE(sc, phy->phy_index, PMU_CFG, val);
    255 	}
    256 
    257 	switch (sc->sc_type) {
    258 	case USBPHY_H3:
    259 	case USBPHY_A64:
    260 		if (enable && phy->phy_bsh) {
    261 			val = PMU_READ(sc, phy->phy_index, PMU_UNK_H3);
    262 			val &= ~PMU_UNK_H3_CLR;
    263 			PMU_WRITE(sc, phy->phy_index, PMU_UNK_H3, val);
    264 		}
    265 		break;
    266 	default:
    267 		break;
    268 	}
    269 
    270 	if (enable) {
    271 		if (phy->phy_index == 0)
    272 			sunxi_usbphy_write(sc, phy, PHY_RES45_CAL_EN, 0x1, 1);
    273 		sunxi_usbphy_write(sc, phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
    274 		sunxi_usbphy_write(sc, phy, PHY_DISCON_TH_SEL, disc_thresh, 2);
    275 	}
    276 
    277 	if (phy->phy_index == 0) {
    278 		const uint32_t mask =
    279 		    PHYCTL_ICR_ID_PULLUP|PHYCTL_ICR_DPDM_PULLUP;
    280 		val = PHYCTL_READ(sc, PHYCTL_ICR);
    281 
    282 		if (enable)
    283 			val |= mask;
    284 		else
    285 			val &= ~mask;
    286 
    287 		/* XXX only host mode is supported */
    288 		val &= ~PHYCTL_ICR_FORCE_ID;
    289 		val |= __SHIFTIN(PHYCTL_ICR_FORCE_ID_LOW, PHYCTL_ICR_FORCE_ID);
    290 		val &= ~PHYCTL_ICR_FORCE_VBUS;
    291 		val |= __SHIFTIN(PHYCTL_ICR_FORCE_VBUS_HIGH, PHYCTL_ICR_FORCE_VBUS);
    292 
    293 		PHYCTL_WRITE(sc, PHYCTL_ICR, val);
    294 
    295 		if (phy0_reroute) {
    296 			val = PHYCTL_READ(sc, PHYCTL_OTG_CFG);
    297 			val &= ~PHYCTL_OTG_ROUTE_OTG;
    298 			PHYCTL_WRITE(sc, PHYCTL_OTG_CFG, val);
    299 		}
    300 	}
    301 
    302 	if (phy->phy_reg == NULL)
    303 		return 0;
    304 
    305 	if (enable) {
    306 		/* If an external vbus is detected, do not enable phy 0 */
    307 		if (phy->phy_index == 0 && sunxi_usbphy_vbus_detect(sc))
    308 			return 0;
    309 		return fdtbus_regulator_enable(phy->phy_reg);
    310 	} else {
    311 		return fdtbus_regulator_disable(phy->phy_reg);
    312 	}
    313 }
    314 
    315 const struct fdtbus_phy_controller_func sunxi_usbphy_funcs = {
    316 	.acquire = sunxi_usbphy_acquire,
    317 	.release = sunxi_usbphy_release,
    318 	.enable = sunxi_usbphy_enable,
    319 };
    320 
    321 static int
    322 sunxi_usbphy_match(device_t parent, cfdata_t cf, void *aux)
    323 {
    324 	struct fdt_attach_args * const faa = aux;
    325 
    326 	return of_match_compat_data(faa->faa_phandle, compat_data);
    327 }
    328 
    329 static void
    330 sunxi_usbphy_attach(device_t parent, device_t self, void *aux)
    331 {
    332 	struct sunxi_usbphy_softc * const sc = device_private(self);
    333 	struct fdt_attach_args * const faa = aux;
    334 	const int phandle = faa->faa_phandle;
    335 	struct fdtbus_reset *rst;
    336 	struct sunxi_usbphy *phy;
    337 	struct clk *clk;
    338 	bus_addr_t addr;
    339 	bus_size_t size;
    340 	char pname[20];
    341 	u_int n;
    342 
    343 	sc->sc_dev = self;
    344 	sc->sc_bst = faa->faa_bst;
    345 	sc->sc_type = of_search_compatible(phandle, compat_data)->data;
    346 
    347 	if (fdtbus_get_reg_byname(phandle, "phy_ctrl", &addr, &size) != 0) {
    348 		aprint_error(": couldn't get phy ctrl registers\n");
    349 		return;
    350 	}
    351 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_phy_ctrl) != 0) {
    352 		aprint_error(": couldn't map phy ctrl registers\n");
    353 		return;
    354 	}
    355 
    356 	for (sc->sc_nphys = 0; sc->sc_nphys < SUNXI_MAXUSBPHY; sc->sc_nphys++) {
    357 		phy = &sc->sc_phys[sc->sc_nphys];
    358 		phy->phy_index = sc->sc_nphys;
    359 		snprintf(pname, sizeof(pname), "pmu%d", sc->sc_nphys);
    360 		if (fdtbus_get_reg_byname(phandle, pname, &addr, &size) != 0) {
    361 			/* There may be no registers for OTG PHY */
    362 			if (sc->sc_nphys > 0)
    363 				break;
    364 		} else if (bus_space_map(sc->sc_bst, addr, size, 0, &phy->phy_bsh) != 0) {
    365 			aprint_error(": failed to map reg #%d\n", sc->sc_nphys);
    366 			return;
    367 		}
    368 		/* Get optional regulator */
    369 		snprintf(pname, sizeof(pname), "usb%d_vbus-supply", sc->sc_nphys);
    370 		phy->phy_reg = fdtbus_regulator_acquire(phandle, pname);
    371 	}
    372 
    373 	/* Enable clocks */
    374 	for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
    375 		if (clk_enable(clk) != 0) {
    376 			aprint_error(": couldn't enable clock #%d\n", n);
    377 			return;
    378 		}
    379 	/* De-assert resets */
    380 	for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++)
    381 		if (fdtbus_reset_deassert(rst) != 0) {
    382 			aprint_error(": couldn't de-assert reset #%d\n", n);
    383 			return;
    384 		}
    385 
    386 	aprint_naive("\n");
    387 	aprint_normal(": USB PHY\n");
    388 
    389 	fdtbus_register_phy_controller(self, phandle, &sunxi_usbphy_funcs);
    390 }
    391