sunxi_usbphy.c revision 1.2
1 /* $NetBSD: sunxi_usbphy.c,v 1.2 2017/06/29 20:54:03 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.2 2017/06/29 20:54:03 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #define OTG_PHY_CFG 0x20 43 #define OTG_PHY_ROUTE_OTG __BIT(0) 44 45 #define HCI_ICR 0x00 46 #define HCI_AHB_INCR8 __BIT(10) 47 #define HCI_AHB_INCR4 __BIT(9) 48 #define HCI_AHB_INCRX_ALIGN __BIT(8) 49 #define HCI_ULPI_BYPASS __BIT(0) 50 #define PMU_UNK_H3 0x10 51 #define PMU_UNK_H3_CLR __BIT(1) 52 53 static int sunxi_usbphy_match(device_t, cfdata_t, void *); 54 static void sunxi_usbphy_attach(device_t, device_t, void *); 55 56 static const char * const compatible[] = { 57 "allwinner,sun8i-h3-usb-phy", 58 NULL 59 }; 60 61 #define SUNXI_MAXUSBPHY 4 62 63 struct sunxi_usbphy { 64 u_int phy_index; 65 bus_space_handle_t phy_bsh; 66 struct fdtbus_regulator *phy_reg; 67 }; 68 69 struct sunxi_usbphy_softc { 70 device_t sc_dev; 71 bus_space_tag_t sc_bst; 72 bus_space_handle_t sc_bsh_phy_ctrl; 73 74 struct sunxi_usbphy sc_phys[SUNXI_MAXUSBPHY]; 75 u_int sc_nphys; 76 77 struct fdtbus_gpio_pin *sc_gpio_id_det; 78 struct fdtbus_gpio_pin *sc_gpio_vbus_det; 79 }; 80 81 #define USBPHY_READ(sc, id, reg) \ 82 bus_space_read_4((sc)->sc_bst, \ 83 (sc)->sc_phys[(id)].phy_bsh, (reg)) 84 #define USBPHY_WRITE(sc, id, reg, val) \ 85 bus_space_write_4((sc)->sc_bst, \ 86 (sc)->sc_phys[(id)].phy_bsh, (reg), (val)) 87 88 CFATTACH_DECL_NEW(sunxi_usbphy, sizeof(struct sunxi_usbphy_softc), 89 sunxi_usbphy_match, sunxi_usbphy_attach, NULL, NULL); 90 91 static bool 92 sunxi_usbphy_vbus_detect(struct sunxi_usbphy_softc *sc) 93 { 94 if (sc->sc_gpio_vbus_det) 95 return fdtbus_gpio_read(sc->sc_gpio_vbus_det); 96 return 1; 97 } 98 99 static void * 100 sunxi_usbphy_acquire(device_t dev, const void *data, size_t len) 101 { 102 struct sunxi_usbphy_softc * const sc = device_private(dev); 103 104 if (len != 4) 105 return NULL; 106 107 const int phy_id = be32dec(data); 108 if (phy_id >= sc->sc_nphys) 109 return NULL; 110 111 return &sc->sc_phys[phy_id]; 112 } 113 114 static void 115 sunxi_usbphy_release(device_t dev, void *priv) 116 { 117 } 118 119 static int 120 sunxi_usbphy_enable(device_t dev, void *priv, bool enable) 121 { 122 struct sunxi_usbphy_softc * const sc = device_private(dev); 123 struct sunxi_usbphy * const phy = priv; 124 uint32_t val; 125 126 if (phy->phy_index > 0) { 127 /* Enable passby */ 128 val = USBPHY_READ(sc, phy->phy_index, HCI_ICR); 129 val |= HCI_ULPI_BYPASS; 130 val |= HCI_AHB_INCR8; 131 val |= HCI_AHB_INCR4; 132 val |= HCI_AHB_INCRX_ALIGN; 133 USBPHY_WRITE(sc, phy->phy_index, HCI_ICR, val); 134 } 135 136 /* H3-specific */ 137 val = USBPHY_READ(sc, phy->phy_index, PMU_UNK_H3); 138 val &= ~PMU_UNK_H3_CLR; 139 USBPHY_WRITE(sc, phy->phy_index, PMU_UNK_H3, val); 140 141 if (phy->phy_reg == NULL) 142 return 0; 143 144 if (enable) { 145 /* If an external vbus is detected, do not enable phy 0 */ 146 if (phy->phy_index == 0 && sunxi_usbphy_vbus_detect(sc)) 147 return 0; 148 return fdtbus_regulator_enable(phy->phy_reg); 149 } else { 150 return fdtbus_regulator_disable(phy->phy_reg); 151 } 152 } 153 154 const struct fdtbus_phy_controller_func sunxi_usbphy_funcs = { 155 .acquire = sunxi_usbphy_acquire, 156 .release = sunxi_usbphy_release, 157 .enable = sunxi_usbphy_enable, 158 }; 159 160 static int 161 sunxi_usbphy_match(device_t parent, cfdata_t cf, void *aux) 162 { 163 struct fdt_attach_args * const faa = aux; 164 165 return of_match_compatible(faa->faa_phandle, compatible); 166 } 167 168 static void 169 sunxi_usbphy_attach(device_t parent, device_t self, void *aux) 170 { 171 struct sunxi_usbphy_softc * const sc = device_private(self); 172 struct fdt_attach_args * const faa = aux; 173 const int phandle = faa->faa_phandle; 174 struct fdtbus_reset *rst; 175 struct sunxi_usbphy *phy; 176 struct clk *clk; 177 bus_addr_t addr; 178 bus_size_t size; 179 char pname[20]; 180 u_int n; 181 182 sc->sc_dev = self; 183 sc->sc_bst = faa->faa_bst; 184 185 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 186 aprint_error(": couldn't get phy ctrl registers\n"); 187 return; 188 } 189 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_phy_ctrl) != 0) { 190 aprint_error(": couldn't map phy ctrl registers\n"); 191 return; 192 } 193 194 for (sc->sc_nphys = 0; sc->sc_nphys < SUNXI_MAXUSBPHY; sc->sc_nphys++) { 195 if (fdtbus_get_reg(phandle, sc->sc_nphys + 1, &addr, &size) != 0) 196 break; 197 phy = &sc->sc_phys[sc->sc_nphys]; 198 phy->phy_index = sc->sc_nphys; 199 if (bus_space_map(sc->sc_bst, addr, size, 0, &phy->phy_bsh) != 0) { 200 aprint_error(": failed to map reg #%d\n", sc->sc_nphys); 201 return; 202 } 203 /* Get optional regulator */ 204 snprintf(pname, sizeof(pname), "usb%d_vbus-supply", sc->sc_nphys); 205 phy->phy_reg = fdtbus_regulator_acquire(phandle, pname); 206 } 207 208 /* Enable clocks */ 209 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 210 if (clk_enable(clk) != 0) { 211 aprint_error(": couldn't enable clock #%d\n", n); 212 return; 213 } 214 /* De-assert resets */ 215 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 216 if (fdtbus_reset_deassert(rst) != 0) { 217 aprint_error(": couldn't de-assert reset #%d\n", n); 218 return; 219 } 220 221 aprint_naive("\n"); 222 aprint_normal(": USB PHY\n"); 223 224 fdtbus_register_phy_controller(self, phandle, &sunxi_usbphy_funcs); 225 } 226
Indexes created Tue Sep 23 02:09:52 GMT 2025