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sunxi_usbphy.c revision 1.8 
      1 /* $NetBSD: sunxi_usbphy.c,v 1.8 2017/09/09 11:58:34 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 
     31 __KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.8 2017/09/09 11:58:34 jmcneill Exp $");
     32 
     33 #include <sys/param.h>
     34 #include <sys/bus.h>
     35 #include <sys/device.h>
     36 #include <sys/intr.h>
     37 #include <sys/systm.h>
     38 #include <sys/time.h>
     39 
     40 #include <dev/fdt/fdtvar.h>
     41 
     42 /* PHY control registers */
     43 #define	PHYCTL_ICR		0x00
     44 #define	 PHYCTL_ICR_ID_PULLUP	__BIT(17)
     45 #define	 PHYCTL_ICR_DPDM_PULLUP	__BIT(16)
     46 #define	 PHYCTL_ICR_FORCE_ID	__BITS(15,14)
     47 #define	  PHYCTL_ICR_FORCE_ID_LOW	2
     48 #define	  PHYCTL_ICR_FORCE_ID_HIGH	3
     49 #define	 PHYCTL_ICR_FORCE_VBUS	__BITS(13,12)
     50 #define	  PHYCTL_ICR_FORCE_VBUS_LOW	2
     51 #define	  PHYCTL_ICR_FORCE_VBUS_HIGH	3
     52 #define	PHYCTL_A10		0x04
     53 #define	PHYCTL_A33		0x10
     54 #define	 PHYCTL_ADDR		__BITS(15,8)
     55 #define	 PHYCTL_DATA		__BIT(7)
     56 #define	PHYCTL_OTG_CFG		0x20
     57 #define	 PHYCTL_OTG_ROUTE_OTG	__BIT(0)
     58 
     59 /* PHY registers */
     60 #define	PHY_RES45_CAL_EN	0x0c
     61 #define	PHY_TX_AMPLITUDE_TUNE	0x20
     62 #define	PHY_DISCON_TH_SEL	0x2a
     63 
     64 /* PMU registers */
     65 #define	PMU_CFG			0x00
     66 #define	 AHB_INCR8		__BIT(10)
     67 #define	 AHB_INCR4		__BIT(9)
     68 #define	 AHB_INCRX_ALIGN	__BIT(8)
     69 #define	 ULPI_BYPASS		__BIT(0)
     70 #define	PMU_UNK_H3		0x10
     71 #define	 PMU_UNK_H3_CLR		__BIT(1)
     72 
     73 static int sunxi_usbphy_match(device_t, cfdata_t, void *);
     74 static void sunxi_usbphy_attach(device_t, device_t, void *);
     75 
     76 enum sunxi_usbphy_type {
     77 	USBPHY_A13,
     78 	USBPHY_A31,
     79 	USBPHY_H3,
     80 	USBPHY_A64,
     81 };
     82 
     83 static const struct of_compat_data compat_data[] = {
     84 	{ "allwinner,sun5i-a13-usb-phy",	USBPHY_A13 },
     85 	{ "allwinner,sun6i-a31-usb-phy",	USBPHY_A31 },
     86 	{ "allwinner,sun8i-h3-usb-phy",		USBPHY_H3 },
     87 	{ "allwinner,sun50i-a64-usb-phy",	USBPHY_A64 },
     88 	{ NULL }
     89 };
     90 
     91 #define	SUNXI_MAXUSBPHY		4
     92 
     93 struct sunxi_usbphy {
     94 	u_int			phy_index;
     95 	bus_space_handle_t	phy_bsh;
     96 	struct fdtbus_regulator *phy_reg;
     97 };
     98 
     99 struct sunxi_usbphy_softc {
    100 	device_t		sc_dev;
    101 	bus_space_tag_t		sc_bst;
    102 	bus_space_handle_t	sc_bsh_phy_ctrl;
    103 	enum sunxi_usbphy_type	sc_type;
    104 
    105 	struct sunxi_usbphy	sc_phys[SUNXI_MAXUSBPHY];
    106 	u_int			sc_nphys;
    107 
    108 	struct fdtbus_gpio_pin	*sc_gpio_id_det;
    109 	struct fdtbus_gpio_pin	*sc_gpio_vbus_det;
    110 };
    111 
    112 #define	PHYCTL_READ(sc, reg)				\
    113 	bus_space_read_4((sc)->sc_bst,			\
    114 	    (sc)->sc_bsh_phy_ctrl, (reg))
    115 #define	PHYCTL_WRITE(sc, reg, val)			\
    116 	bus_space_write_4((sc)->sc_bst,			\
    117 	    (sc)->sc_bsh_phy_ctrl, (reg), (val))
    118 #define	PMU_READ(sc, id, reg)			\
    119 	bus_space_read_4((sc)->sc_bst,			\
    120 	    (sc)->sc_phys[(id)].phy_bsh, (reg))
    121 #define	PMU_WRITE(sc, id, reg, val)			\
    122 	bus_space_write_4((sc)->sc_bst,			\
    123 	    (sc)->sc_phys[(id)].phy_bsh, (reg), (val))
    124 
    125 CFATTACH_DECL_NEW(sunxi_usbphy, sizeof(struct sunxi_usbphy_softc),
    126 	sunxi_usbphy_match, sunxi_usbphy_attach, NULL, NULL);
    127 
    128 static void
    129 sunxi_usbphy_write(struct sunxi_usbphy_softc *sc,
    130     struct sunxi_usbphy *phy, u_int bit_addr, u_int bits,
    131     u_int len)
    132 {
    133 	const uint32_t usbc_mask = __BIT(phy->phy_index * 2);;
    134 	bus_size_t reg;
    135 	uint32_t val;
    136 
    137 	switch (sc->sc_type) {
    138 	case USBPHY_A13:
    139 	case USBPHY_A31:
    140 		reg = PHYCTL_A10;
    141 		break;
    142 	case USBPHY_H3:
    143 	case USBPHY_A64:
    144 		reg = PHYCTL_A33;
    145 		break;
    146 	default:
    147 		panic("unsupported phy type");
    148 	}
    149 
    150 	if (reg == PHYCTL_A33)
    151 		PHYCTL_WRITE(sc, reg, 0);
    152 
    153 	for (; len > 0; bit_addr++, bits >>= 1, len--) {
    154 		val = PHYCTL_READ(sc, reg);
    155 		val &= ~PHYCTL_ADDR;
    156 		val |= __SHIFTIN(bit_addr, PHYCTL_ADDR);
    157 		PHYCTL_WRITE(sc, reg, val);
    158 
    159 		val = PHYCTL_READ(sc, reg);
    160 		val &= ~PHYCTL_DATA;
    161 		val |= __SHIFTIN(bits & 1, PHYCTL_DATA);
    162 		PHYCTL_WRITE(sc, reg, val);
    163 
    164 		PHYCTL_READ(sc, reg);
    165 		val |= usbc_mask;
    166 		PHYCTL_WRITE(sc, reg, val);
    167 
    168 		PHYCTL_READ(sc, reg);
    169 		val &= ~usbc_mask;
    170 		PHYCTL_WRITE(sc, reg, val);
    171 	}
    172 }
    173 
    174 static bool
    175 sunxi_usbphy_vbus_detect(struct sunxi_usbphy_softc *sc)
    176 {
    177 	if (sc->sc_gpio_vbus_det)
    178 		return fdtbus_gpio_read(sc->sc_gpio_vbus_det);
    179 	return 1;
    180 }
    181 
    182 static void *
    183 sunxi_usbphy_acquire(device_t dev, const void *data, size_t len)
    184 {
    185 	struct sunxi_usbphy_softc * const sc = device_private(dev);
    186 
    187 	if (len != 4)
    188 		return NULL;
    189 
    190 	const int phy_id = be32dec(data);
    191 	if (phy_id >= sc->sc_nphys)
    192 		return NULL;
    193 
    194 	return &sc->sc_phys[phy_id];
    195 }
    196 
    197 static void
    198 sunxi_usbphy_release(device_t dev, void *priv)
    199 {
    200 }
    201 
    202 static int
    203 sunxi_usbphy_enable(device_t dev, void *priv, bool enable)
    204 {
    205 	struct sunxi_usbphy_softc * const sc = device_private(dev);
    206 	struct sunxi_usbphy * const phy = priv;
    207 	u_int disc_thresh;
    208 	bool phy0_reroute;
    209 	uint32_t val;
    210 
    211 	switch (sc->sc_type) {
    212 	case USBPHY_A13:
    213 		disc_thresh = 0x2;
    214 		phy0_reroute = false;
    215 		break;
    216 	case USBPHY_A31:
    217 		disc_thresh = 0x3;
    218 		phy0_reroute = false;
    219 		break;
    220 	case USBPHY_A64:
    221 	case USBPHY_H3:
    222 		disc_thresh = 0x3;
    223 		phy0_reroute = true;
    224 		break;
    225 	}
    226 
    227 	if (phy->phy_bsh) {
    228 		/* Enable/disable passby */
    229 		const uint32_t mask =
    230 		    ULPI_BYPASS|AHB_INCR8|AHB_INCR4|AHB_INCRX_ALIGN;
    231 		val = PMU_READ(sc, phy->phy_index, PMU_CFG);
    232 		if (enable)
    233 			val |= mask;
    234 		else
    235 			val &= ~mask;
    236 		PMU_WRITE(sc, phy->phy_index, PMU_CFG, val);
    237 	}
    238 
    239 	switch (sc->sc_type) {
    240 	case USBPHY_H3:
    241 	case USBPHY_A64:
    242 		if (enable && phy->phy_bsh) {
    243 			val = PMU_READ(sc, phy->phy_index, PMU_UNK_H3);
    244 			val &= ~PMU_UNK_H3_CLR;
    245 			PMU_WRITE(sc, phy->phy_index, PMU_UNK_H3, val);
    246 		}
    247 		break;
    248 	default:
    249 		break;
    250 	}
    251 
    252 	if (enable) {
    253 		if (phy->phy_index == 0)
    254 			sunxi_usbphy_write(sc, phy, PHY_RES45_CAL_EN, 0x1, 1);
    255 		sunxi_usbphy_write(sc, phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
    256 		sunxi_usbphy_write(sc, phy, PHY_DISCON_TH_SEL, disc_thresh, 2);
    257 	}
    258 
    259 	if (phy->phy_index == 0) {
    260 		const uint32_t mask =
    261 		    PHYCTL_ICR_ID_PULLUP|PHYCTL_ICR_DPDM_PULLUP;
    262 		val = PHYCTL_READ(sc, PHYCTL_ICR);
    263 
    264 		if (enable)
    265 			val |= mask;
    266 		else
    267 			val &= ~mask;
    268 
    269 		/* XXX only host mode is supported */
    270 		val &= ~PHYCTL_ICR_FORCE_ID;
    271 		val |= __SHIFTIN(PHYCTL_ICR_FORCE_ID_LOW, PHYCTL_ICR_FORCE_ID);
    272 		val &= ~PHYCTL_ICR_FORCE_VBUS;
    273 		val |= __SHIFTIN(PHYCTL_ICR_FORCE_VBUS_HIGH, PHYCTL_ICR_FORCE_VBUS);
    274 
    275 		PHYCTL_WRITE(sc, PHYCTL_ICR, val);
    276 
    277 		if (phy0_reroute) {
    278 			val = PHYCTL_READ(sc, PHYCTL_OTG_CFG);
    279 			val &= ~PHYCTL_OTG_ROUTE_OTG;
    280 			PHYCTL_WRITE(sc, PHYCTL_OTG_CFG, val);
    281 		}
    282 	}
    283 
    284 	if (phy->phy_reg == NULL)
    285 		return 0;
    286 
    287 	if (enable) {
    288 		/* If an external vbus is detected, do not enable phy 0 */
    289 		if (phy->phy_index == 0 && sunxi_usbphy_vbus_detect(sc))
    290 			return 0;
    291 		return fdtbus_regulator_enable(phy->phy_reg);
    292 	} else {
    293 		return fdtbus_regulator_disable(phy->phy_reg);
    294 	}
    295 }
    296 
    297 const struct fdtbus_phy_controller_func sunxi_usbphy_funcs = {
    298 	.acquire = sunxi_usbphy_acquire,
    299 	.release = sunxi_usbphy_release,
    300 	.enable = sunxi_usbphy_enable,
    301 };
    302 
    303 static int
    304 sunxi_usbphy_match(device_t parent, cfdata_t cf, void *aux)
    305 {
    306 	struct fdt_attach_args * const faa = aux;
    307 
    308 	return of_match_compat_data(faa->faa_phandle, compat_data);
    309 }
    310 
    311 static void
    312 sunxi_usbphy_attach(device_t parent, device_t self, void *aux)
    313 {
    314 	struct sunxi_usbphy_softc * const sc = device_private(self);
    315 	struct fdt_attach_args * const faa = aux;
    316 	const int phandle = faa->faa_phandle;
    317 	struct fdtbus_reset *rst;
    318 	struct sunxi_usbphy *phy;
    319 	struct clk *clk;
    320 	bus_addr_t addr;
    321 	bus_size_t size;
    322 	char pname[20];
    323 	u_int n;
    324 
    325 	sc->sc_dev = self;
    326 	sc->sc_bst = faa->faa_bst;
    327 	sc->sc_type = of_search_compatible(phandle, compat_data)->data;
    328 
    329 	if (fdtbus_get_reg_byname(phandle, "phy_ctrl", &addr, &size) != 0) {
    330 		aprint_error(": couldn't get phy ctrl registers\n");
    331 		return;
    332 	}
    333 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_phy_ctrl) != 0) {
    334 		aprint_error(": couldn't map phy ctrl registers\n");
    335 		return;
    336 	}
    337 
    338 	for (sc->sc_nphys = 0; sc->sc_nphys < SUNXI_MAXUSBPHY; sc->sc_nphys++) {
    339 		phy = &sc->sc_phys[sc->sc_nphys];
    340 		phy->phy_index = sc->sc_nphys;
    341 		snprintf(pname, sizeof(pname), "pmu%d", sc->sc_nphys);
    342 		if (fdtbus_get_reg_byname(phandle, pname, &addr, &size) != 0) {
    343 			/* There may be no registers for OTG PHY */
    344 			if (sc->sc_nphys > 0)
    345 				break;
    346 		} else if (bus_space_map(sc->sc_bst, addr, size, 0, &phy->phy_bsh) != 0) {
    347 			aprint_error(": failed to map reg #%d\n", sc->sc_nphys);
    348 			return;
    349 		}
    350 		/* Get optional regulator */
    351 		snprintf(pname, sizeof(pname), "usb%d_vbus-supply", sc->sc_nphys);
    352 		phy->phy_reg = fdtbus_regulator_acquire(phandle, pname);
    353 	}
    354 
    355 	/* Enable clocks */
    356 	for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
    357 		if (clk_enable(clk) != 0) {
    358 			aprint_error(": couldn't enable clock #%d\n", n);
    359 			return;
    360 		}
    361 	/* De-assert resets */
    362 	for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++)
    363 		if (fdtbus_reset_deassert(rst) != 0) {
    364 			aprint_error(": couldn't de-assert reset #%d\n", n);
    365 			return;
    366 		}
    367 
    368 	aprint_naive("\n");
    369 	aprint_normal(": USB PHY\n");
    370 
    371 	fdtbus_register_phy_controller(self, phandle, &sunxi_usbphy_funcs);
    372 }
    373