1 /* $NetBSD: am18xx_gpio.c,v 1.1 2026/09/27 19:56:21 yurix Exp $ */ 2 3 /*- 4 * Copyright (c) 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Yuri Honegger. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * GPIOs for the TI AM18XX SoC 34 */ 35 36 #include <sys/param.h> 37 #include <sys/cdefs.h> 38 #include <sys/device.h> 39 #include <sys/gpio.h> 40 #include <sys/kmem.h> 41 #include <sys/mutex.h> 42 43 #include <dev/fdt/fdtvar.h> 44 #include <dev/gpio/gpiovar.h> 45 46 struct am18xx_gpio_fdt_pin { 47 int pin_nr; 48 bool pin_actlo; 49 }; 50 51 struct am18xx_gpio_softc { 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 kmutex_t sc_lock; 55 struct gpio_chipset_tag sc_gc; 56 int sc_num_gpios; 57 }; 58 59 static int am18xx_gpio_match(device_t, cfdata_t, void *); 60 static void am18xx_gpio_attach(device_t, device_t, void *); 61 static void * am18xx_gpio_fdt_acquire(device_t, const void *, size_t, int); 62 static void am18xx_gpio_fdt_release(device_t, void *); 63 static int am18xx_gpio_fdt_read(device_t, void *, bool); 64 static void am18xx_gpio_fdt_write(device_t, void *, int, bool); 65 static int am18xx_gpio_gp_pin_read(void *, int); 66 static void am18xx_gpio_gp_pin_write(void *, int, int); 67 static void am18xx_gpio_gp_pin_ctl(void *, int, int); 68 69 CFATTACH_DECL_NEW(am18xxgpio, sizeof(struct am18xx_gpio_softc), 70 am18xx_gpio_match, am18xx_gpio_attach, NULL, NULL); 71 72 #define AM18XX_GPIO_BANK_BASE 0x10 73 #define AM18XX_GPIO_BANK_SIZE 0x28 74 #define AM18XX_GPIO_BANK_DIR 0x0 75 #define AM18XX_GPIO_BANK_SET 0x8 76 #define AM18XX_GPIO_BANK_CLEAR 0xC 77 #define AM18XX_GPIO_BANK_INPUT 0x10 78 79 #define GPIO_READ(sc, reg) \ 80 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg) 81 #define GPIO_WRITE(sc, reg, val) \ 82 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val) 83 84 static const struct device_compatible_entry compat_data[] = { 85 { .compat = "ti,dm6441-gpio" }, 86 DEVICE_COMPAT_EOL 87 }; 88 89 static const struct fdtbus_gpio_controller_func am18xx_gpio_fdt_funcs = { 90 .acquire = am18xx_gpio_fdt_acquire, 91 .release = am18xx_gpio_fdt_release, 92 .read = am18xx_gpio_fdt_read, 93 .write = am18xx_gpio_fdt_write, 94 }; 95 96 static void * 97 am18xx_gpio_fdt_acquire(device_t dev, const void *rdata, size_t len, int flags) 98 { 99 struct am18xx_gpio_softc * const sc = device_private(dev); 100 const uint32_t *data = rdata; 101 struct am18xx_gpio_fdt_pin *pin; 102 103 if (len != 12) 104 return NULL; 105 106 int pin_nr = be32toh(data[1]); 107 int actlo = be32toh(data[2]) & 1; 108 109 if (pin_nr < 0 || pin_nr >= sc->sc_num_gpios) 110 return NULL; 111 112 pin = kmem_zalloc(sizeof(struct am18xx_gpio_fdt_pin), KM_SLEEP); 113 if (pin == NULL) { 114 return NULL; 115 } 116 117 pin->pin_nr = pin_nr; 118 pin->pin_actlo = actlo; 119 120 gpiobus_pin_ctl(&sc->sc_gc, pin->pin_nr, flags); 121 122 return pin; 123 } 124 125 static void 126 am18xx_gpio_fdt_release(device_t dev, void *priv) 127 { 128 struct am18xx_gpio_softc * const sc = device_private(dev); 129 struct am18xx_gpio_fdt_pin * const pin = priv; 130 131 am18xx_gpio_gp_pin_ctl(sc, pin->pin_nr, GPIO_PIN_INPUT); 132 133 kmem_free(pin, sizeof(*pin)); 134 } 135 136 static int 137 am18xx_gpio_fdt_read(device_t dev, void *priv, bool raw) 138 { 139 struct am18xx_gpio_softc * const sc = device_private(dev); 140 struct am18xx_gpio_fdt_pin * const pin = priv; 141 int val; 142 143 val = am18xx_gpio_gp_pin_read(sc, pin->pin_nr); 144 145 if (!raw && pin->pin_actlo) 146 val = !val; 147 148 return val; 149 } 150 151 static void 152 am18xx_gpio_fdt_write(device_t dev, void *priv, int val, bool raw) 153 { 154 struct am18xx_gpio_softc * const sc = device_private(dev); 155 struct am18xx_gpio_fdt_pin * const pin = priv; 156 157 if (!raw && pin->pin_actlo) 158 val = !val; 159 160 am18xx_gpio_gp_pin_write(sc, pin->pin_nr, val); 161 } 162 163 static int 164 am18xx_gpio_gp_pin_read(void *priv, int pin) 165 { 166 struct am18xx_gpio_softc * const sc = priv; 167 168 KASSERT(pin >= 0 && pin < sc->sc_num_gpios); 169 170 int bank_group = pin / 32; 171 uint32_t group_bit = __BIT(pin % 32); 172 int bank_base = AM18XX_GPIO_BANK_BASE + 173 bank_group * AM18XX_GPIO_BANK_SIZE; 174 175 /* GPIO input value reads are built to be atomic */ 176 uint32_t val = GPIO_READ(sc, bank_base + AM18XX_GPIO_BANK_INPUT); 177 178 return (val & group_bit) != 0; 179 } 180 181 static void 182 am18xx_gpio_gp_pin_write(void *priv, int pin, int val) 183 { 184 struct am18xx_gpio_softc * const sc = priv; 185 186 KASSERT(pin >= 0 && pin < sc->sc_num_gpios); 187 188 int bank_group = pin / 32; 189 uint32_t group_bit = __BIT(pin % 32); 190 int bank_base = AM18XX_GPIO_BANK_BASE + 191 bank_group * AM18XX_GPIO_BANK_SIZE; 192 193 /* 194 * We do *not* need the lock because BANK_SET/BANK_CLEAR is built to 195 * be set by multiple threads at once. 196 */ 197 if (val) { 198 GPIO_WRITE(sc, bank_base + AM18XX_GPIO_BANK_SET, group_bit); 199 } else { 200 GPIO_WRITE(sc, bank_base + AM18XX_GPIO_BANK_CLEAR, group_bit); 201 } 202 } 203 204 static void 205 am18xx_gpio_gp_pin_ctl(void *priv, int pin, int flags) 206 { 207 struct am18xx_gpio_softc * const sc = priv; 208 209 KASSERT(pin >= 0 && pin < sc->sc_num_gpios); 210 211 int bank_group = pin / 32; 212 uint32_t group_bit = __BIT(pin % 32); 213 int bank_base = AM18XX_GPIO_BANK_BASE + 214 bank_group * AM18XX_GPIO_BANK_SIZE; 215 216 mutex_enter(&sc->sc_lock); 217 if (flags & GPIO_PIN_OUTPUT) { 218 uint32_t val = GPIO_READ(sc, bank_base + AM18XX_GPIO_BANK_DIR); 219 val &= ~group_bit; 220 GPIO_WRITE(sc, bank_base + AM18XX_GPIO_BANK_DIR, val); 221 } else if (flags & GPIO_PIN_INPUT) { 222 uint32_t val = GPIO_READ(sc, bank_base + AM18XX_GPIO_BANK_DIR); 223 val |= group_bit; 224 GPIO_WRITE(sc, bank_base + AM18XX_GPIO_BANK_DIR, val); 225 } 226 mutex_exit(&sc->sc_lock); 227 } 228 229 int 230 am18xx_gpio_match(device_t parent, cfdata_t cf, void *aux) 231 { 232 struct fdt_attach_args * const faa = aux; 233 234 return of_compatible_match(faa->faa_phandle, compat_data); 235 } 236 237 void 238 am18xx_gpio_attach(device_t parent, device_t self, void *aux) 239 { 240 struct am18xx_gpio_softc * const sc = device_private(self); 241 struct fdt_attach_args * const faa = aux; 242 const int phandle = faa->faa_phandle; 243 bus_addr_t addr; 244 bus_size_t size; 245 246 sc->sc_bst = faa->faa_bst; 247 248 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 249 250 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 251 aprint_error(": couldn't get registers\n"); 252 return; 253 } 254 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 255 aprint_error(": couldn't map registers\n"); 256 return; 257 } 258 259 if (fdtbus_clock_enable(phandle, "gpio", true) != 0) { 260 aprint_error(": couldn't enable clock\n"); 261 return; 262 } 263 264 if (of_getprop_uint32(phandle, "ti,ngpio", &sc->sc_num_gpios) != 0) { 265 aprint_error(": couldn't get gpio count\n"); 266 return; 267 } 268 269 gpio_pin_t *gpio_pin_desc = kmem_alloc( 270 sc->sc_num_gpios * sizeof(gpio_pin_t), KM_SLEEP); 271 if (gpio_pin_desc == NULL) { 272 aprint_error(": couldn't allocate memory\n"); 273 return; 274 } 275 memset(gpio_pin_desc, 0, sc->sc_num_gpios * sizeof(gpio_pin_t)); 276 for (int i = 0; i < sc->sc_num_gpios; i++) { 277 gpio_pin_desc[i].pin_num = i; 278 gpio_pin_desc[i].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 279 GPIO_PIN_INOUT | GPIO_PIN_PUSHPULL; 280 gpio_pin_desc[i].pin_gc = &sc->sc_gc; 281 } 282 283 sc->sc_gc.gp_cookie = sc; 284 sc->sc_gc.gp_pin_read = am18xx_gpio_gp_pin_read; 285 sc->sc_gc.gp_pin_write = am18xx_gpio_gp_pin_write; 286 sc->sc_gc.gp_pin_ctl = am18xx_gpio_gp_pin_ctl; 287 288 struct gpiobus_attach_args gpiobus_aa; 289 gpiobus_aa.gba_gc = &sc->sc_gc; 290 gpiobus_aa.gba_npins = sc->sc_num_gpios; 291 gpiobus_aa.gba_pins = gpio_pin_desc; 292 293 aprint_naive("\n"); 294 aprint_normal("\n"); 295 296 config_found(self, &gpiobus_aa, gpiobus_print, CFARGS_NONE); 297 298 fdtbus_register_gpio_controller(self, phandle, &am18xx_gpio_fdt_funcs); 299 } 300 301
Indexes created Mon Oct 05 00:25:34 UTC 2026