omap2_nand.c revision 1.2.10.2
1 1.2.10.2 martin /* $NetBSD: omap2_nand.c,v 1.2.10.2 2020/04/13 08:03:38 martin Exp $ */ 2 1.2.10.2 martin 3 1.2.10.2 martin /*- 4 1.2.10.2 martin * Copyright (c) 2010 Department of Software Engineering, 5 1.2.10.2 martin * University of Szeged, Hungary 6 1.2.10.2 martin * Copyright (c) 2010 Adam Hoka <ahoka (at) NetBSD.org> 7 1.2.10.2 martin * All rights reserved. 8 1.2.10.2 martin * 9 1.2.10.2 martin * This code is derived from software contributed to The NetBSD Foundation 10 1.2.10.2 martin * by the Department of Software Engineering, University of Szeged, Hungary 11 1.2.10.2 martin * 12 1.2.10.2 martin * Redistribution and use in source and binary forms, with or without 13 1.2.10.2 martin * modification, are permitted provided that the following conditions 14 1.2.10.2 martin * are met: 15 1.2.10.2 martin * 1. Redistributions of source code must retain the above copyright 16 1.2.10.2 martin * notice, this list of conditions and the following disclaimer. 17 1.2.10.2 martin * 2. Redistributions in binary form must reproduce the above copyright 18 1.2.10.2 martin * notice, this list of conditions and the following disclaimer in the 19 1.2.10.2 martin * documentation and/or other materials provided with the distribution. 20 1.2.10.2 martin * 21 1.2.10.2 martin * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 1.2.10.2 martin * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 1.2.10.2 martin * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 1.2.10.2 martin * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 1.2.10.2 martin * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 1.2.10.2 martin * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 1.2.10.2 martin * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 1.2.10.2 martin * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 1.2.10.2 martin * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 1.2.10.2 martin * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 1.2.10.2 martin * SUCH DAMAGE. 32 1.2.10.2 martin */ 33 1.2.10.2 martin 34 1.2.10.2 martin /* Device driver for the NAND controller found in Texas Instruments OMAP2 35 1.2.10.2 martin * and later SOCs. 36 1.2.10.2 martin */ 37 1.2.10.2 martin 38 1.2.10.2 martin #include <sys/cdefs.h> 39 1.2.10.2 martin __KERNEL_RCSID(0, "$NetBSD: omap2_nand.c,v 1.2.10.2 2020/04/13 08:03:38 martin Exp $"); 40 1.2.10.2 martin 41 1.2.10.2 martin /* TODO move to opt_* */ 42 1.2.10.2 martin #undef OMAP2_NAND_HARDWARE_ECC 43 1.2.10.2 martin 44 1.2.10.2 martin #include <sys/param.h> 45 1.2.10.2 martin #include <sys/systm.h> 46 1.2.10.2 martin #include <sys/cdefs.h> 47 1.2.10.2 martin #include <sys/device.h> 48 1.2.10.2 martin 49 1.2.10.2 martin #include <sys/bus.h> 50 1.2.10.2 martin 51 1.2.10.2 martin #include <arm/ti/omap2_gpmcreg.h> 52 1.2.10.2 martin 53 1.2.10.2 martin #include <dev/nand/nand.h> 54 1.2.10.2 martin #include <dev/nand/onfi.h> 55 1.2.10.2 martin 56 1.2.10.2 martin #include <dev/fdt/fdtvar.h> 57 1.2.10.2 martin 58 1.2.10.2 martin extern struct flash_interface nand_flash_if; 59 1.2.10.2 martin extern int flash_print(void *, const char *); 60 1.2.10.2 martin 61 1.2.10.2 martin /* GPMC_STATUS */ 62 1.2.10.2 martin #define WAIT0 __BIT(8) /* active low */ 63 1.2.10.2 martin 64 1.2.10.2 martin /* GPMC_ECC_CONTROL */ 65 1.2.10.2 martin #define ECCCLEAR __BIT(8) 66 1.2.10.2 martin #define ECCPOINTER __BITS(3,0) 67 1.2.10.2 martin 68 1.2.10.2 martin /* GPMC_ECC_CONFIG */ 69 1.2.10.2 martin #define ECCALGORITHM __BIT(16) 70 1.2.10.2 martin #define ECCCS __BITS(3,1) 71 1.2.10.2 martin #define ECC16B __BIT(7) 72 1.2.10.2 martin #define ECCENABLE __BIT(0) 73 1.2.10.2 martin /* GPMC_ECC_SIZE_CONFIG */ 74 1.2.10.2 martin #define ECCSIZE1 __BITS(29,22) 75 1.2.10.2 martin 76 1.2.10.2 martin /* GPMC_CONFIG1_i */ 77 1.2.10.2 martin #define DEVICETYPE __BITS(11,10) 78 1.2.10.2 martin #define DEVICESIZE __BITS(13,12) 79 1.2.10.2 martin 80 1.2.10.2 martin #define MASKEDINT(mask, integer) ((integer) << (ffs(mask) - 1) & mask) 81 1.2.10.2 martin 82 1.2.10.2 martin /* NAND status register */ 83 1.2.10.2 martin #define NAND_WP_BIT __BIT(4) 84 1.2.10.2 martin 85 1.2.10.2 martin static int omap2_nand_match(device_t, cfdata_t, void *); 86 1.2.10.2 martin static void omap2_nand_attach(device_t, device_t, void *); 87 1.2.10.2 martin 88 1.2.10.2 martin static void omap2_nand_command(device_t self, uint8_t command); 89 1.2.10.2 martin static void omap2_nand_address(device_t self, uint8_t address); 90 1.2.10.2 martin static void omap2_nand_busy(device_t self); 91 1.2.10.2 martin static void omap2_nand_read_1(device_t self, uint8_t *data); 92 1.2.10.2 martin static void omap2_nand_write_1(device_t self, uint8_t data); 93 1.2.10.2 martin static void omap2_nand_read_2(device_t self, uint16_t *data); 94 1.2.10.2 martin static void omap2_nand_write_2(device_t self, uint16_t data); 95 1.2.10.2 martin bool omap2_nand_isbusy(device_t self); 96 1.2.10.2 martin static void omap2_nand_read_buf_1(device_t self, void *buf, size_t len); 97 1.2.10.2 martin static void omap2_nand_read_buf_2(device_t self, void *buf, size_t len); 98 1.2.10.2 martin static void omap2_nand_write_buf_1(device_t self, const void *buf, size_t len); 99 1.2.10.2 martin static void omap2_nand_write_buf_2(device_t self, const void *buf, size_t len); 100 1.2.10.2 martin 101 1.2.10.2 martin #ifdef OMAP2_NAND_HARDWARE_ECC 102 1.2.10.2 martin static int omap2_nand_ecc_init(device_t self); 103 1.2.10.2 martin static int omap2_nand_ecc_prepare(device_t self, int mode); 104 1.2.10.2 martin static int omap2_nand_ecc_compute(device_t self, const uint8_t *data, uint8_t *ecc); 105 1.2.10.2 martin static int omap2_nand_ecc_correct(device_t self, uint8_t *data, const uint8_t *oldecc, 106 1.2.10.2 martin const uint8_t *calcecc); 107 1.2.10.2 martin #endif 108 1.2.10.2 martin 109 1.2.10.2 martin struct omap2_nand_softc { 110 1.2.10.2 martin device_t sc_dev; 111 1.2.10.2 martin device_t sc_nanddev; 112 1.2.10.2 martin 113 1.2.10.2 martin int sc_cs; 114 1.2.10.2 martin int sc_buswidth; /* 0: 8bit, 1: 16bit */ 115 1.2.10.2 martin 116 1.2.10.2 martin struct nand_interface sc_nand_if; 117 1.2.10.2 martin 118 1.2.10.2 martin bus_space_tag_t sc_iot; 119 1.2.10.2 martin bus_space_handle_t sc_ioh; 120 1.2.10.2 martin bus_space_handle_t sc_gpmc_ioh; 121 1.2.10.2 martin 122 1.2.10.2 martin bus_size_t sc_cmd_reg; 123 1.2.10.2 martin bus_size_t sc_addr_reg; 124 1.2.10.2 martin bus_size_t sc_data_reg; 125 1.2.10.2 martin }; 126 1.2.10.2 martin 127 1.2.10.2 martin static const char * compatible[] = { 128 1.2.10.2 martin "ti,omap2-nand", 129 1.2.10.2 martin "ti,omap2-onenand", 130 1.2.10.2 martin NULL 131 1.2.10.2 martin }; 132 1.2.10.2 martin 133 1.2.10.2 martin CFATTACH_DECL_NEW(omapnand, sizeof(struct omap2_nand_softc), omap2_nand_match, 134 1.2.10.2 martin omap2_nand_attach, NULL, NULL); 135 1.2.10.2 martin 136 1.2.10.2 martin static inline uint32_t 137 1.2.10.2 martin gpmc_register_read(struct omap2_nand_softc *sc, bus_size_t reg) 138 1.2.10.2 martin { 139 1.2.10.2 martin return bus_space_read_4(sc->sc_iot, sc->sc_gpmc_ioh, reg); 140 1.2.10.2 martin } 141 1.2.10.2 martin 142 1.2.10.2 martin static inline void 143 1.2.10.2 martin gpmc_register_write(struct omap2_nand_softc *sc, bus_size_t reg, const uint32_t data) 144 1.2.10.2 martin { 145 1.2.10.2 martin bus_space_write_4(sc->sc_iot, sc->sc_gpmc_ioh, reg, data); 146 1.2.10.2 martin } 147 1.2.10.2 martin 148 1.2.10.2 martin static void 149 1.2.10.2 martin omap2_nand_command(device_t self, uint8_t command) 150 1.2.10.2 martin { 151 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 152 1.2.10.2 martin 153 1.2.10.2 martin bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->sc_cmd_reg, command); 154 1.2.10.2 martin }; 155 1.2.10.2 martin 156 1.2.10.2 martin static void 157 1.2.10.2 martin omap2_nand_address(device_t self, uint8_t address) 158 1.2.10.2 martin { 159 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 160 1.2.10.2 martin 161 1.2.10.2 martin bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->sc_addr_reg, address); 162 1.2.10.2 martin }; 163 1.2.10.2 martin 164 1.2.10.2 martin bool 165 1.2.10.2 martin omap2_nand_isbusy(device_t self) 166 1.2.10.2 martin { 167 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 168 1.2.10.2 martin uint8_t status; 169 1.2.10.2 martin 170 1.2.10.2 martin DELAY(1); /* just to be sure we are not early */ 171 1.2.10.2 martin 172 1.2.10.2 martin bus_space_write_1(sc->sc_iot, sc->sc_ioh, 173 1.2.10.2 martin sc->sc_cmd_reg, ONFI_READ_STATUS); 174 1.2.10.2 martin 175 1.2.10.2 martin DELAY(1); 176 1.2.10.2 martin 177 1.2.10.2 martin status = bus_space_read_1(sc->sc_iot, 178 1.2.10.2 martin sc->sc_ioh, sc->sc_data_reg); 179 1.2.10.2 martin 180 1.2.10.2 martin return !(status & ONFI_STATUS_RDY); 181 1.2.10.2 martin }; 182 1.2.10.2 martin 183 1.2.10.2 martin static int 184 1.2.10.2 martin omap2_nand_match(device_t parent, cfdata_t match, void *aux) 185 1.2.10.2 martin { 186 1.2.10.2 martin struct fdt_attach_args * const faa = aux; 187 1.2.10.2 martin 188 1.2.10.2 martin return of_match_compatible(faa->faa_phandle, compatible); 189 1.2.10.2 martin } 190 1.2.10.2 martin 191 1.2.10.2 martin static void 192 1.2.10.2 martin omap2_nand_attach(device_t parent, device_t self, void *aux) 193 1.2.10.2 martin { 194 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 195 1.2.10.2 martin struct fdt_attach_args * const faa = aux; 196 1.2.10.2 martin const int phandle = faa->faa_phandle; 197 1.2.10.2 martin struct flash_attach_args flash; 198 1.2.10.2 martin bus_addr_t addr, part_addr; 199 1.2.10.2 martin bus_size_t size, part_size; 200 1.2.10.2 martin const u_int *prop; 201 1.2.10.2 martin uint32_t val; 202 1.2.10.2 martin int len, child; 203 1.2.10.2 martin 204 1.2.10.2 martin if (fdtbus_get_reg(OF_parent(phandle), 0, &addr, &size) != 0) { 205 1.2.10.2 martin aprint_error(": couldn't get registers\n"); 206 1.2.10.2 martin return; 207 1.2.10.2 martin } 208 1.2.10.2 martin 209 1.2.10.2 martin sc->sc_iot = faa->faa_bst; 210 1.2.10.2 martin sc->sc_dev = self; 211 1.2.10.2 martin 212 1.2.10.2 martin prop = fdtbus_get_prop(phandle, "reg", &len); 213 1.2.10.2 martin if (prop == NULL || len < 4) { 214 1.2.10.2 martin aprint_error(": couldn't read reg property\n"); 215 1.2.10.2 martin return; 216 1.2.10.2 martin } 217 1.2.10.2 martin 218 1.2.10.2 martin sc->sc_cs = be32toh(prop[0]); 219 1.2.10.2 martin 220 1.2.10.2 martin /* map i/o space */ 221 1.2.10.2 martin if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_gpmc_ioh) != 0) { 222 1.2.10.2 martin aprint_error(": couldn't map registers\n"); 223 1.2.10.2 martin return; 224 1.2.10.2 martin } 225 1.2.10.2 martin if (bus_space_subregion(sc->sc_iot, sc->sc_gpmc_ioh, GPMC_CS_CONFIG(sc->sc_cs), 0x30, &sc->sc_ioh) != 0) { 226 1.2.10.2 martin aprint_error(": couldn't map cs registers\n"); 227 1.2.10.2 martin return; 228 1.2.10.2 martin } 229 1.2.10.2 martin 230 1.2.10.2 martin aprint_naive("\n"); 231 1.2.10.2 martin aprint_normal(": CS%d\n", sc->sc_cs); 232 1.2.10.2 martin 233 1.2.10.2 martin sc->sc_cmd_reg = GPMC_NAND_COMMAND_0 - GPMC_CONFIG1_0; 234 1.2.10.2 martin sc->sc_addr_reg = GPMC_NAND_ADDRESS_0 - GPMC_CONFIG1_0; 235 1.2.10.2 martin sc->sc_data_reg = GPMC_NAND_DATA_0 - GPMC_CONFIG1_0; 236 1.2.10.2 martin 237 1.2.10.2 martin /* turn off write protection if enabled */ 238 1.2.10.2 martin val = gpmc_register_read(sc, GPMC_CONFIG); 239 1.2.10.2 martin val |= NAND_WP_BIT; 240 1.2.10.2 martin gpmc_register_write(sc, GPMC_CONFIG, val); 241 1.2.10.2 martin 242 1.2.10.2 martin /* 243 1.2.10.2 martin * do the reset dance for NAND 244 1.2.10.2 martin */ 245 1.2.10.2 martin bus_space_write_1(sc->sc_iot, sc->sc_ioh, 246 1.2.10.2 martin sc->sc_cmd_reg, ONFI_RESET); 247 1.2.10.2 martin 248 1.2.10.2 martin omap2_nand_busy(self); 249 1.2.10.2 martin 250 1.2.10.2 martin /* read GPMC_CONFIG1_i to get buswidth */ 251 1.2.10.2 martin val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPMC_CONFIG1_i); 252 1.2.10.2 martin 253 1.2.10.2 martin if ((val & DEVICESIZE) == MASKEDINT(DEVICESIZE, 0x01)) { 254 1.2.10.2 martin /* 16bit */ 255 1.2.10.2 martin sc->sc_buswidth = 1; 256 1.2.10.2 martin } else if ((val & DEVICESIZE) == MASKEDINT(DEVICESIZE, 0x00)) { 257 1.2.10.2 martin /* 8bit */ 258 1.2.10.2 martin sc->sc_buswidth = 0; 259 1.2.10.2 martin } else { 260 1.2.10.2 martin panic("invalid buswidth reported by config1"); 261 1.2.10.2 martin } 262 1.2.10.2 martin 263 1.2.10.2 martin nand_init_interface(&sc->sc_nand_if); 264 1.2.10.2 martin 265 1.2.10.2 martin sc->sc_nand_if.command = &omap2_nand_command; 266 1.2.10.2 martin sc->sc_nand_if.address = &omap2_nand_address; 267 1.2.10.2 martin sc->sc_nand_if.read_buf_1 = &omap2_nand_read_buf_1; 268 1.2.10.2 martin sc->sc_nand_if.read_buf_2 = &omap2_nand_read_buf_2; 269 1.2.10.2 martin sc->sc_nand_if.read_1 = &omap2_nand_read_1; 270 1.2.10.2 martin sc->sc_nand_if.read_2 = &omap2_nand_read_2; 271 1.2.10.2 martin sc->sc_nand_if.write_buf_1 = &omap2_nand_write_buf_1; 272 1.2.10.2 martin sc->sc_nand_if.write_buf_2 = &omap2_nand_write_buf_2; 273 1.2.10.2 martin sc->sc_nand_if.write_1 = &omap2_nand_write_1; 274 1.2.10.2 martin sc->sc_nand_if.write_2 = &omap2_nand_write_2; 275 1.2.10.2 martin sc->sc_nand_if.busy = &omap2_nand_busy; 276 1.2.10.2 martin 277 1.2.10.2 martin #ifdef OMAP2_NAND_HARDWARE_ECC 278 1.2.10.2 martin omap2_nand_ecc_init(self); 279 1.2.10.2 martin sc->sc_nand_if.ecc_compute = &omap2_nand_ecc_compute; 280 1.2.10.2 martin sc->sc_nand_if.ecc_correct = &omap2_nand_ecc_correct; 281 1.2.10.2 martin sc->sc_nand_if.ecc_prepare = &omap2_nand_ecc_prepare; 282 1.2.10.2 martin sc->sc_nand_if.ecc.necc_code_size = 3; 283 1.2.10.2 martin sc->sc_nand_if.ecc.necc_block_size = 512; 284 1.2.10.2 martin sc->sc_nand_if.ecc.necc_type = NAND_ECC_TYPE_HW; 285 1.2.10.2 martin #else 286 1.2.10.2 martin sc->sc_nand_if.ecc.necc_code_size = 3; 287 1.2.10.2 martin sc->sc_nand_if.ecc.necc_block_size = 256; 288 1.2.10.2 martin #endif /* OMAP2_NAND_HARDWARE_ECC */ 289 1.2.10.2 martin 290 1.2.10.2 martin if (!pmf_device_register1(sc->sc_dev, NULL, NULL, NULL)) 291 1.2.10.2 martin aprint_error_dev(sc->sc_dev, 292 1.2.10.2 martin "couldn't establish power handler\n"); 293 1.2.10.2 martin 294 1.2.10.2 martin sc->sc_nanddev = nand_attach_mi(&sc->sc_nand_if, sc->sc_dev); 295 1.2.10.2 martin if (sc->sc_nanddev == NULL) 296 1.2.10.2 martin return; 297 1.2.10.2 martin 298 1.2.10.2 martin for (child = OF_child(phandle); child; child = OF_peer(child)) { 299 1.2.10.2 martin if (!fdtbus_status_okay(child)) 300 1.2.10.2 martin continue; 301 1.2.10.2 martin 302 1.2.10.2 martin if (fdtbus_get_reg(child, 0, &part_addr, &part_size) != 0) { 303 1.2.10.2 martin aprint_error_dev(self, "couldn't parse partition %s\n", 304 1.2.10.2 martin fdtbus_get_string(child, "name")); 305 1.2.10.2 martin continue; 306 1.2.10.2 martin } 307 1.2.10.2 martin 308 1.2.10.2 martin memset(&flash, 0, sizeof(flash)); 309 1.2.10.2 martin flash.flash_if = &nand_flash_if; 310 1.2.10.2 martin flash.partinfo.part_offset = part_addr; 311 1.2.10.2 martin flash.partinfo.part_size = part_size; 312 1.2.10.2 martin flash.partinfo.part_flags = 0; 313 1.2.10.2 martin flash.partinfo.part_name = fdtbus_get_string(child, "label"); 314 1.2.10.2 martin if (flash.partinfo.part_name == NULL) 315 1.2.10.2 martin flash.partinfo.part_name = fdtbus_get_string(child, "name"); 316 1.2.10.2 martin 317 1.2.10.2 martin config_found_ia(sc->sc_nanddev, "flashbus", &flash, flash_print); 318 1.2.10.2 martin } 319 1.2.10.2 martin } 320 1.2.10.2 martin 321 1.2.10.2 martin static void 322 1.2.10.2 martin omap2_nand_busy(device_t self) 323 1.2.10.2 martin { 324 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 325 1.2.10.2 martin 326 1.2.10.2 martin while (!(gpmc_register_read(sc, GPMC_STATUS) & WAIT0)) { 327 1.2.10.2 martin DELAY(1); 328 1.2.10.2 martin } 329 1.2.10.2 martin } 330 1.2.10.2 martin 331 1.2.10.2 martin static void 332 1.2.10.2 martin omap2_nand_read_1(device_t self, uint8_t *data) 333 1.2.10.2 martin { 334 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 335 1.2.10.2 martin 336 1.2.10.2 martin *data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->sc_data_reg); 337 1.2.10.2 martin } 338 1.2.10.2 martin 339 1.2.10.2 martin static void 340 1.2.10.2 martin omap2_nand_write_1(device_t self, uint8_t data) 341 1.2.10.2 martin { 342 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 343 1.2.10.2 martin 344 1.2.10.2 martin bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->sc_data_reg, data); 345 1.2.10.2 martin } 346 1.2.10.2 martin 347 1.2.10.2 martin static void 348 1.2.10.2 martin omap2_nand_read_2(device_t self, uint16_t *data) 349 1.2.10.2 martin { 350 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 351 1.2.10.2 martin 352 1.2.10.2 martin *data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->sc_data_reg); 353 1.2.10.2 martin } 354 1.2.10.2 martin 355 1.2.10.2 martin static void 356 1.2.10.2 martin omap2_nand_write_2(device_t self, uint16_t data) 357 1.2.10.2 martin { 358 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 359 1.2.10.2 martin 360 1.2.10.2 martin bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_data_reg, data); 361 1.2.10.2 martin } 362 1.2.10.2 martin 363 1.2.10.2 martin static void 364 1.2.10.2 martin omap2_nand_read_buf_1(device_t self, void *buf, size_t len) 365 1.2.10.2 martin { 366 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 367 1.2.10.2 martin 368 1.2.10.2 martin KASSERT(buf != NULL); 369 1.2.10.2 martin KASSERT(len >= 1); 370 1.2.10.2 martin 371 1.2.10.2 martin bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 372 1.2.10.2 martin sc->sc_data_reg, buf, len); 373 1.2.10.2 martin } 374 1.2.10.2 martin 375 1.2.10.2 martin static void 376 1.2.10.2 martin omap2_nand_read_buf_2(device_t self, void *buf, size_t len) 377 1.2.10.2 martin { 378 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 379 1.2.10.2 martin 380 1.2.10.2 martin KASSERT(buf != NULL); 381 1.2.10.2 martin KASSERT(len >= 2); 382 1.2.10.2 martin KASSERT(!(len & 0x01)); 383 1.2.10.2 martin 384 1.2.10.2 martin bus_space_read_multi_2(sc->sc_iot, sc->sc_ioh, 385 1.2.10.2 martin sc->sc_data_reg, buf, len / 2); 386 1.2.10.2 martin } 387 1.2.10.2 martin 388 1.2.10.2 martin static void 389 1.2.10.2 martin omap2_nand_write_buf_1(device_t self, const void *buf, size_t len) 390 1.2.10.2 martin { 391 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 392 1.2.10.2 martin 393 1.2.10.2 martin KASSERT(buf != NULL); 394 1.2.10.2 martin KASSERT(len >= 1); 395 1.2.10.2 martin 396 1.2.10.2 martin bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 397 1.2.10.2 martin sc->sc_data_reg, buf, len); 398 1.2.10.2 martin } 399 1.2.10.2 martin 400 1.2.10.2 martin static void 401 1.2.10.2 martin omap2_nand_write_buf_2(device_t self, const void *buf, size_t len) 402 1.2.10.2 martin { 403 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 404 1.2.10.2 martin 405 1.2.10.2 martin KASSERT(buf != NULL); 406 1.2.10.2 martin KASSERT(len >= 2); 407 1.2.10.2 martin KASSERT(!(len & 0x01)); 408 1.2.10.2 martin 409 1.2.10.2 martin bus_space_write_multi_2(sc->sc_iot, sc->sc_ioh, 410 1.2.10.2 martin sc->sc_data_reg, buf, len / 2); 411 1.2.10.2 martin } 412 1.2.10.2 martin 413 1.2.10.2 martin #ifdef OMAP2_NAND_HARDWARE_ECC 414 1.2.10.2 martin static uint32_t 415 1.2.10.2 martin convert_ecc(const uint8_t *ecc) 416 1.2.10.2 martin { 417 1.2.10.2 martin return ecc[0] | (ecc[1] << 16) | ((ecc[2] & 0xf0) << 20) | 418 1.2.10.2 martin ((ecc[2] & 0x0f) << 8); 419 1.2.10.2 martin } 420 1.2.10.2 martin 421 1.2.10.2 martin static int 422 1.2.10.2 martin omap2_nand_ecc_init(device_t self) 423 1.2.10.2 martin { 424 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 425 1.2.10.2 martin uint32_t val; 426 1.2.10.2 martin 427 1.2.10.2 martin val = gpmc_register_read(sc, GPMC_ECC_CONTROL); 428 1.2.10.2 martin /* clear ecc, select ecc register 1 */ 429 1.2.10.2 martin val &= ~ECCPOINTER; 430 1.2.10.2 martin val |= ECCCLEAR | MASKEDINT(ECCPOINTER, 1); 431 1.2.10.2 martin gpmc_register_write(sc, GPMC_ECC_CONTROL, val); 432 1.2.10.2 martin 433 1.2.10.2 martin /* XXX too many MAGIC */ 434 1.2.10.2 martin /* set ecc size to 512, set all regs to eccsize1*/ 435 1.2.10.2 martin val = gpmc_register_read(sc, GPMC_ECC_SIZE_CONFIG); 436 1.2.10.2 martin val &= ~ECCSIZE1; 437 1.2.10.2 martin val |= MASKEDINT(ECCSIZE1, 512) | 0x0f; 438 1.2.10.2 martin gpmc_register_write(sc, GPMC_ECC_CONTROL, val); 439 1.2.10.2 martin 440 1.2.10.2 martin return 0; 441 1.2.10.2 martin } 442 1.2.10.2 martin 443 1.2.10.2 martin static int 444 1.2.10.2 martin omap2_nand_ecc_compute(device_t self, const uint8_t *data, uint8_t *ecc) 445 1.2.10.2 martin { 446 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 447 1.2.10.2 martin uint32_t val; 448 1.2.10.2 martin 449 1.2.10.2 martin /* read ecc result register */ 450 1.2.10.2 martin val = gpmc_register_read(sc, GPMC_ECC1_RESULT); 451 1.2.10.2 martin 452 1.2.10.2 martin ecc[0] = val & 0xff; 453 1.2.10.2 martin ecc[1] = (val >> 16) & 0xff; 454 1.2.10.2 martin ecc[2] = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); 455 1.2.10.2 martin 456 1.2.10.2 martin /* disable ecc engine */ 457 1.2.10.2 martin val = gpmc_register_read(sc, GPMC_ECC_CONFIG); 458 1.2.10.2 martin val &= ~ECCENABLE; 459 1.2.10.2 martin gpmc_register_write(sc, GPMC_ECC_CONFIG, val); 460 1.2.10.2 martin 461 1.2.10.2 martin return 0; 462 1.2.10.2 martin } 463 1.2.10.2 martin 464 1.2.10.2 martin static int 465 1.2.10.2 martin omap2_nand_ecc_prepare(device_t self, int mode) 466 1.2.10.2 martin { 467 1.2.10.2 martin struct omap2_nand_softc *sc = device_private(self); 468 1.2.10.2 martin uint32_t val; 469 1.2.10.2 martin 470 1.2.10.2 martin /* same for read/write */ 471 1.2.10.2 martin switch (mode) { 472 1.2.10.2 martin case NAND_ECC_READ: 473 1.2.10.2 martin case NAND_ECC_WRITE: 474 1.2.10.2 martin val = gpmc_register_read(sc, GPMC_ECC_CONTROL); 475 1.2.10.2 martin /* clear ecc, select ecc register 1 */ 476 1.2.10.2 martin val &= ~ECCPOINTER; 477 1.2.10.2 martin val |= ECCCLEAR | MASKEDINT(ECCPOINTER, 1); 478 1.2.10.2 martin gpmc_register_write(sc, GPMC_ECC_CONTROL, val); 479 1.2.10.2 martin 480 1.2.10.2 martin val = gpmc_register_read(sc, GPMC_ECC_CONFIG); 481 1.2.10.2 martin val &= ~ECCCS; 482 1.2.10.2 martin val |= ECCENABLE | MASKEDINT(ECCCS, sc->sc_cs); 483 1.2.10.2 martin if (sc->sc_buswidth == 1) 484 1.2.10.2 martin val |= ECC16B; 485 1.2.10.2 martin else 486 1.2.10.2 martin val &= ~ECC16B; 487 1.2.10.2 martin gpmc_register_write(sc, GPMC_ECC_CONFIG, val); 488 1.2.10.2 martin 489 1.2.10.2 martin break; 490 1.2.10.2 martin default: 491 1.2.10.2 martin aprint_error_dev(self, "invalid i/o mode for ecc prepare\n"); 492 1.2.10.2 martin return -1; 493 1.2.10.2 martin } 494 1.2.10.2 martin 495 1.2.10.2 martin return 0; 496 1.2.10.2 martin } 497 1.2.10.2 martin 498 1.2.10.2 martin static int 499 1.2.10.2 martin omap2_nand_ecc_correct(device_t self, uint8_t *data, const uint8_t *oldecc, 500 1.2.10.2 martin const uint8_t *calcecc) 501 1.2.10.2 martin { 502 1.2.10.2 martin uint32_t oecc, cecc, xor; 503 1.2.10.2 martin uint16_t parity, offset; 504 1.2.10.2 martin uint8_t bit; 505 1.2.10.2 martin 506 1.2.10.2 martin oecc = convert_ecc(oldecc); 507 1.2.10.2 martin cecc = convert_ecc(calcecc); 508 1.2.10.2 martin 509 1.2.10.2 martin /* get the difference */ 510 1.2.10.2 martin xor = oecc ^ cecc; 511 1.2.10.2 martin 512 1.2.10.2 martin /* the data was correct if all bits are zero */ 513 1.2.10.2 martin if (xor == 0x00) 514 1.2.10.2 martin return NAND_ECC_OK; 515 1.2.10.2 martin 516 1.2.10.2 martin switch (popcount32(xor)) { 517 1.2.10.2 martin case 12: 518 1.2.10.2 martin /* single byte error */ 519 1.2.10.2 martin parity = xor >> 16; 520 1.2.10.2 martin bit = (parity & 0x07); 521 1.2.10.2 martin offset = (parity >> 3) & 0x01ff; 522 1.2.10.2 martin /* correct bit */ 523 1.2.10.2 martin data[offset] ^= (0x01 << bit); 524 1.2.10.2 martin return NAND_ECC_CORRECTED; 525 1.2.10.2 martin case 1: 526 1.2.10.2 martin return NAND_ECC_INVALID; 527 1.2.10.2 martin default: 528 1.2.10.2 martin /* erased page! */ 529 1.2.10.2 martin if ((oecc == 0x0fff0fff) && (cecc == 0x00000000)) 530 1.2.10.2 martin return NAND_ECC_OK; 531 1.2.10.2 martin 532 1.2.10.2 martin return NAND_ECC_TWOBIT; 533 1.2.10.2 martin } 534 1.2.10.2 martin } 535 1.2.10.2 martin #endif /* !OMAP2_NAND_HARDWARE_ECC */ 536
Indexes created Thu Oct 02 10:09:58 GMT 2025