1 /* $NetBSD: zynq_xadc.c,v 1.1 2022/11/11 20:31:30 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2022 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Xilinx 7 series ADC ("XADC") 31 * 32 * Documentation can be found on the Xilinx web site: 33 * - Zynq-7000 SoC Technical Reference Manual UG585 (v1.13) 34 * - XADC User Guide 3 UG480 (v1.11) 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: zynq_xadc.c,v 1.1 2022/11/11 20:31:30 jmcneill Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/bitops.h> 42 #include <sys/bus.h> 43 #include <sys/device.h> 44 #include <sys/intr.h> 45 #include <sys/kmem.h> 46 #include <sys/lwp.h> 47 #include <sys/mutex.h> 48 #include <sys/systm.h> 49 50 #include <dev/sysmon/sysmonvar.h> 51 #include <dev/fdt/fdtvar.h> 52 53 /* PS-XADC interface registers */ 54 #define XADCIF_CFG 0x00 55 #define CFG_ENABLE __BIT(31) 56 #define CFG_WEDGE __BIT(13) 57 #define CFG_REDGE __BIT(12) 58 #define CFG_TCKRATE __BITS(9,8) 59 #define CFG_TCKRATE_DIV4 1 60 #define XADCIF_INT_STS 0x04 61 #define XADCIF_INT_MASK 0x08 62 #define XADCIF_MSTS 0x0c 63 #define MSTS_CFIFOE __BIT(10) 64 #define XADCIF_CMDFIFO 0x10 65 #define XADCIF_RDFIFO 0x14 66 #define XADCIF_MCTL 0x18 67 68 /* XADC registers */ 69 #define XADC_STATUS_TEMP 0x00 70 #define XADC_STATUS_VCCINT 0x01 71 #define XADC_STATUS_VCCAUX 0x02 72 #define XADC_STATUS_VPVN 0x03 73 #define XADC_STATUS_VREFP 0x04 74 #define XADC_STATUS_VREFN 0x05 75 #define XADC_STATUS_VCCBRAM 0x06 76 #define XADC_STATUS_VCCPINT 0x0d 77 #define XADC_STATUS_VCCPAUX 0x0e 78 #define XADC_STATUS_VCCO_DDR 0x0f 79 #define XADC_STATUS_FLAG 0x3f 80 #define FLAG_OT __BIT(3) 81 #define XADC_CONF(n) (0x40 + (n)) 82 #define CONF1_SEQ __BITS(15,12) 83 #define CONF1_SEQ_CONT 2 84 #define XADC_SEQ(n) (0x48 + (n)) 85 #define SEQ0_CALIB __BIT(0) 86 #define SEQ0_ALL __BITS(5,14) 87 #define SEQ4_VREFN __BIT(13) 88 89 /* XADC commands */ 90 #define XADC_COMMAND_CMD __BITS(29,26) 91 #define XADC_COMMAND_DRP_ADDR __BITS(25,16) 92 #define XADC_COMMAND_DRP_DATA __BITS(15,0) 93 #define XADC_COMMAND(cmd, addr, data) \ 94 (__SHIFTIN(cmd, XADC_COMMAND_CMD) | \ 95 __SHIFTIN(addr, XADC_COMMAND_DRP_ADDR) | \ 96 __SHIFTIN(data, XADC_COMMAND_DRP_DATA)) 97 #define XADC_CMD_NOP 0 98 #define XADC_CMD_READ 1 99 #define XADC_CMD_WRITE 2 100 101 enum { 102 XADC_SENSOR_TEMP, 103 XADC_SENSOR_VCCINT, 104 XADC_SENSOR_VCCAUX, 105 XADC_SENSOR_VPVN, 106 XADC_SENSOR_VREFP, 107 XADC_SENSOR_VREFN, 108 XADC_SENSOR_VCCBRAM, 109 XADC_SENSOR_VCCPINT, 110 XADC_SENSOR_VCCPAUX, 111 XADC_SENSOR_VCCO_DDR, 112 XADC_NSENSOR 113 }; 114 115 static const struct { 116 const char *name; 117 uint32_t units; 118 uint16_t reg; 119 } zynq_xadc_sensors[] = { 120 [XADC_SENSOR_TEMP] = { "temperature", ENVSYS_STEMP, XADC_STATUS_TEMP }, 121 [XADC_SENSOR_VCCINT] = { "vccint", ENVSYS_SVOLTS_DC, XADC_STATUS_VCCINT }, 122 [XADC_SENSOR_VCCAUX] = { "vccaux", ENVSYS_SVOLTS_DC, XADC_STATUS_VCCAUX }, 123 [XADC_SENSOR_VPVN] = { "vp/vn", ENVSYS_SVOLTS_DC, XADC_STATUS_VPVN }, 124 [XADC_SENSOR_VREFP] = { "vrefp", ENVSYS_SVOLTS_DC, XADC_STATUS_VREFP }, 125 [XADC_SENSOR_VREFN] = { "vrefn", ENVSYS_SVOLTS_DC, XADC_STATUS_VREFN }, 126 [XADC_SENSOR_VCCBRAM] = { "vccbram", ENVSYS_SVOLTS_DC, XADC_STATUS_VCCBRAM }, 127 [XADC_SENSOR_VCCPINT] = { "vccpint", ENVSYS_SVOLTS_DC, XADC_STATUS_VCCPINT }, 128 [XADC_SENSOR_VCCPAUX] = { "vccpaux", ENVSYS_SVOLTS_DC, XADC_STATUS_VCCPAUX }, 129 [XADC_SENSOR_VCCO_DDR] = { "vcco_ddr", ENVSYS_SVOLTS_DC, XADC_STATUS_VCCO_DDR }, 130 }; 131 132 static const struct device_compatible_entry compat_data[] = { 133 { .compat = "xlnx,zynq-xadc-1.00.a" }, 134 DEVICE_COMPAT_EOL 135 }; 136 137 struct zynq_xadc_softc { 138 device_t sc_dev; 139 bus_space_tag_t sc_bst; 140 bus_space_handle_t sc_bsh; 141 kmutex_t sc_lock; 142 143 struct sysmon_envsys *sc_sme; 144 envsys_data_t sc_sensor[XADC_NSENSOR]; 145 }; 146 147 #define RD4(sc, reg) \ 148 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 149 #define WR4(sc, reg, val) \ 150 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 151 152 static int zynq_xadc_match(device_t, cfdata_t, void *); 153 static void zynq_xadc_attach(device_t, device_t, void *); 154 155 CFATTACH_DECL_NEW(zynqxadc, sizeof(struct zynq_xadc_softc), 156 zynq_xadc_match, zynq_xadc_attach, NULL, NULL); 157 158 static void 159 zynq_xadc_write(struct zynq_xadc_softc *sc, uint16_t reg, 160 uint16_t data) 161 { 162 int retry = 10000; 163 164 /* 165 * Write sequence is: 166 * 167 * 1. Prepare write command 168 * 2. Write data to Command FIFO 169 * 3. Wait until the Command FIFO becomes empty 170 */ 171 172 WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_WRITE, reg, data)); 173 while (--retry > 0) { 174 if ((RD4(sc, XADCIF_MSTS) & MSTS_CFIFOE) != 0) { 175 break; 176 } 177 delay(10); 178 } 179 if (retry == 0) { 180 device_printf(sc->sc_dev, "command FIFO timeout (write)\n"); 181 } 182 /* 183 * Every write to Command FIFO shifts data into Read FIFO, so 184 * drain that after the command completes. 185 */ 186 RD4(sc, XADCIF_RDFIFO); 187 } 188 189 static uint16_t 190 zynq_xadc_read(struct zynq_xadc_softc *sc, uint16_t reg) 191 { 192 int retry = 10000; 193 uint32_t val; 194 195 /* 196 * Read sequence is: 197 * 198 * 1. Prepare read command 199 * 2. Write data to Command FIFO 200 * 3. Wait until the Command FIFO becomes empty 201 * 4. Read dummy data from the Read Data FIFO 202 * 5. Prepare nop command 203 * 6. Write data to Command FIFO 204 * 7. Read the Read Data FIFO 205 */ 206 207 WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_READ, reg, 0)); 208 WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_NOP, 0, 0)); 209 while (--retry > 0) { 210 if ((RD4(sc, XADCIF_MSTS) & MSTS_CFIFOE) != 0) { 211 break; 212 } 213 delay(10); 214 } 215 if (retry == 0) { 216 device_printf(sc->sc_dev, "command FIFO timeout (read)\n"); 217 return 0xffff; 218 } 219 val = RD4(sc, XADCIF_RDFIFO); 220 val = RD4(sc, XADCIF_RDFIFO); 221 222 return val & 0xffff; 223 } 224 225 static void 226 zynq_xadc_init(struct zynq_xadc_softc *sc, struct clk *clk) 227 { 228 uint32_t val; 229 230 /* Enable the PS-XADC interface */ 231 val = RD4(sc, XADCIF_CFG); 232 val |= CFG_ENABLE; 233 val &= ~CFG_TCKRATE; 234 val |= __SHIFTIN(CFG_TCKRATE_DIV4, CFG_TCKRATE); 235 val |= CFG_WEDGE | CFG_REDGE; 236 WR4(sc, XADCIF_CFG, val); 237 WR4(sc, XADCIF_MCTL, 0); 238 239 /* Turn on continuous sampling for all ADC channels we monitor */ 240 zynq_xadc_write(sc, XADC_SEQ(0), SEQ0_CALIB | SEQ0_ALL); 241 zynq_xadc_write(sc, XADC_SEQ(4), SEQ4_VREFN); 242 zynq_xadc_write(sc, XADC_CONF(0), 0); 243 zynq_xadc_write(sc, XADC_CONF(1), 244 __SHIFTIN(CONF1_SEQ_CONT, CONF1_SEQ)); 245 246 } 247 248 static void 249 zynq_xadc_sensors_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 250 { 251 struct zynq_xadc_softc *sc = sme->sme_cookie; 252 union { 253 uint16_t u16; 254 int16_t s16; 255 } val; 256 int64_t temp; 257 258 259 val.u16 = zynq_xadc_read(sc, zynq_xadc_sensors[edata->sensor].reg); 260 if (edata->units == ENVSYS_STEMP) { 261 if (val.u16 == 0) { 262 edata->state = ENVSYS_SINVALID; 263 } else { 264 temp = ((int64_t)(val.u16 >> 4) * 503975) / 4096; 265 edata->value_cur = 1000 * temp; 266 edata->state = ENVSYS_SVALID; 267 } 268 269 val.u16 = zynq_xadc_read(sc, XADC_STATUS_FLAG); 270 if ((val.u16 & FLAG_OT) != 0) { 271 edata->state = ENVSYS_SCRITOVER; 272 } 273 } else { 274 KASSERT(edata->units == ENVSYS_SVOLTS_DC); 275 switch (edata->sensor) { 276 case XADC_SENSOR_VPVN: 277 edata->value_cur = (((val.u16 >> 4) * 1000) / 4096) * 1000; 278 break; 279 case XADC_SENSOR_VREFN: 280 edata->value_cur = (((val.s16 >> 4) * 3000) / 4096) * 1000; 281 break; 282 default: 283 edata->value_cur = (((val.u16 >> 4) * 3000) / 4096) * 1000; 284 break; 285 } 286 edata->state = ENVSYS_SVALID; 287 } 288 } 289 290 static int 291 zynq_xadc_match(device_t parent, cfdata_t cf, void *aux) 292 { 293 struct fdt_attach_args * const faa = aux; 294 295 return of_compatible_match(faa->faa_phandle, compat_data); 296 } 297 298 static void 299 zynq_xadc_attach(device_t parent, device_t self, void *aux) 300 { 301 struct zynq_xadc_softc * const sc = device_private(self); 302 struct fdt_attach_args * const faa = aux; 303 const int phandle = faa->faa_phandle; 304 struct clk *clk; 305 bus_addr_t addr; 306 bus_size_t size; 307 u_int n; 308 309 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 310 aprint_error(": couldn't get registers\n"); 311 return; 312 } 313 clk = fdtbus_clock_get_index(phandle, 0); 314 if (clk == NULL || clk_enable(clk) != 0) { 315 aprint_error(": couldn't enable clock\n"); 316 return; 317 } 318 319 sc->sc_dev = self; 320 sc->sc_bst = faa->faa_bst; 321 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 322 aprint_error(": couldn't map registers\n"); 323 return; 324 } 325 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 326 327 aprint_naive("\n"); 328 aprint_normal(": ADC\n"); 329 330 zynq_xadc_init(sc, clk); 331 332 sc->sc_sme = sysmon_envsys_create(); 333 sc->sc_sme->sme_name = device_xname(self); 334 sc->sc_sme->sme_cookie = sc; 335 sc->sc_sme->sme_refresh = zynq_xadc_sensors_refresh; 336 337 for (n = 0; n < XADC_NSENSOR; n++) { 338 sc->sc_sensor[n].units = zynq_xadc_sensors[n].units; 339 sc->sc_sensor[n].state = ENVSYS_SINVALID; 340 sc->sc_sensor[n].flags = ENVSYS_FHAS_ENTROPY; 341 if (zynq_xadc_sensors[n].units == ENVSYS_STEMP) { 342 sc->sc_sensor[n].flags |= ENVSYS_FMONCRITICAL; 343 } 344 strncpy(sc->sc_sensor[n].desc, zynq_xadc_sensors[n].name, 345 sizeof(sc->sc_sensor[n].desc)); 346 sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[n]); 347 } 348 349 sysmon_envsys_register(sc->sc_sme); 350 } 351
Indexes created Sat Sep 20 22:09:52 GMT 2025