1 /* $NetBSD: becc_timer.c,v 1.16 2020/05/29 12:30:39 rin Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Timer/clock support for the ADI Engineering Big Endian Companion Chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: becc_timer.c,v 1.16 2020/05/29 12:30:39 rin Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/atomic.h> 49 #include <sys/time.h> 50 #include <sys/timetc.h> 51 52 #include <dev/clock_subr.h> 53 54 #include <sys/bus.h> 55 #include <arm/cpufunc.h> 56 57 #include <arm/xscale/beccreg.h> 58 #include <arm/xscale/beccvar.h> 59 60 void (*becc_hardclock_hook)(void); 61 62 /* 63 * Note, since COUNTS_PER_USEC doesn't divide evenly, we round up. 64 */ 65 #define COUNTS_PER_SEC BECC_PERIPH_CLOCK 66 #define COUNTS_PER_USEC ((COUNTS_PER_SEC / 1000000) + 1) 67 68 static void *clock_ih; 69 70 static u_int becc_get_timecount(struct timecounter *); 71 72 static struct timecounter becc_timecounter = { 73 .tc_get_timecount = becc_get_timecount, 74 .tc_counter_mask = 0xffffffff, 75 .tc_frequency = COUNTS_PER_SEC, 76 .tc_name = "becc", 77 .tc_quality = 100, 78 }; 79 80 static volatile uint32_t becc_base; 81 82 /* 83 * Since the timer interrupts when the counter underflows, we need to 84 * subtract 1 from counts_per_hz when loading the preload register. 85 */ 86 static uint32_t counts_per_hz; 87 88 int clockhandler(void *); 89 90 /* 91 * becc_calibrate_delay: 92 * 93 * Calibrate the delay loop. 94 */ 95 void 96 becc_calibrate_delay(void) 97 { 98 99 /* 100 * Just use hz=100 for now -- we'll adjust it, if necessary, 101 * in cpu_initclocks(). 102 */ 103 counts_per_hz = COUNTS_PER_SEC / 100; 104 105 /* Stop both timers, clear interrupts. */ 106 BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TIF); 107 BECC_CSR_WRITE(BECC_TSCRB, TSCRx_TIF); 108 109 /* Set the timer preload value. */ 110 BECC_CSR_WRITE(BECC_TPRA, counts_per_hz - 1); 111 112 /* Start the timer. */ 113 BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM); 114 } 115 116 /* 117 * cpu_initclocks: 118 * 119 * Initialize the clock and get them going. 120 */ 121 void 122 cpu_initclocks(void) 123 { 124 u_int oldirqstate; 125 126 #if 0 127 if (hz < 50 || COUNTS_PER_SEC % hz) { 128 printf("Cannot get %d Hz clock; using 100 Hz\n", hz); 129 hz = 100; 130 } 131 #endif 132 133 /* 134 * We only have one timer available; stathz and profhz are 135 * always left as 0 (the upper-layer clock code deals with 136 * this situation). 137 */ 138 if (stathz != 0) 139 printf("Cannot get %d Hz statclock\n", stathz); 140 stathz = 0; 141 142 if (profhz != 0) 143 printf("Cannot get %d Hz profclock\n", profhz); 144 profhz = 0; 145 146 /* Report the clock frequency. */ 147 aprint_normal("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz); 148 149 oldirqstate = disable_interrupts(I32_bit); 150 151 /* Hook up the clock interrupt handler. */ 152 clock_ih = becc_intr_establish(ICU_TIMERA, IPL_CLOCK, 153 clockhandler, NULL); 154 if (clock_ih == NULL) 155 panic("cpu_initclocks: unable to register timer interrupt"); 156 157 /* Set up the new clock parameters. */ 158 159 /* Stop timer, clear interrupt */ 160 BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TIF); 161 162 counts_per_hz = COUNTS_PER_SEC / hz; 163 164 /* Set the timer preload value. */ 165 BECC_CSR_WRITE(BECC_TPRA, counts_per_hz - 1); 166 167 /* ...and start it in motion. */ 168 BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM); 169 170 #ifdef __HAVE_FAST_SOFTINTS 171 /* register soft interrupt handler as well */ 172 becc_intr_establish(ICU_SOFT, IPL_SOFTCLOCK, becc_softint, NULL); 173 #endif 174 175 restore_interrupts(oldirqstate); 176 177 tc_init(&becc_timecounter); 178 } 179 180 /* 181 * setstatclockrate: 182 * 183 * Set the rate of the statistics clock. 184 * 185 * We assume that hz is either stathz or profhz, and that neither 186 * will change after being set by cpu_initclocks(). We could 187 * recalculate the intervals here, but that would be a pain. 188 */ 189 void 190 setstatclockrate(int new_hz) 191 { 192 193 /* 194 * XXX Use TMR1? 195 */ 196 } 197 198 static u_int 199 becc_get_timecount(struct timecounter *tc) 200 { 201 uint32_t counter, base; 202 u_int oldirqstate; 203 204 oldirqstate = disable_interrupts(I32_bit); 205 counter = BECC_CSR_READ(BECC_TCVRA); 206 base = becc_base; 207 restore_interrupts(oldirqstate); 208 209 return base - counter; 210 } 211 212 /* 213 * delay: 214 * 215 * Delay for at least N microseconds. 216 */ 217 void 218 delay(u_int n) 219 { 220 uint32_t cur, last, delta, usecs; 221 222 /* 223 * This works by polling the timer and counting the 224 * number of microseconds that go by. 225 */ 226 last = BECC_CSR_READ(BECC_TCVRA); 227 delta = usecs = 0; 228 229 while (n > usecs) { 230 cur = BECC_CSR_READ(BECC_TCVRA); 231 232 /* Check to see if the timer has wrapped around. */ 233 if (last < cur) 234 delta += (last + (counts_per_hz - cur)); 235 else 236 delta += (last - cur); 237 238 last = cur; 239 240 if (delta >= COUNTS_PER_USEC) { 241 usecs += delta / COUNTS_PER_USEC; 242 delta %= COUNTS_PER_USEC; 243 } 244 } 245 } 246 247 /* 248 * clockhandler: 249 * 250 * Handle the hardclock interrupt. 251 */ 252 int 253 clockhandler(void *arg) 254 { 255 struct clockframe *frame = arg; 256 257 /* ACK the interrupt. */ 258 BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM | TSCRx_TIF); 259 260 hardclock(frame); 261 262 atomic_add_32(&becc_base, counts_per_hz); 263 264 if (becc_hardclock_hook != NULL) 265 (*becc_hardclock_hook)(); 266 267 return (1); 268 } 269
Indexes created Sat Sep 20 22:09:52 GMT 2025