1 /* $NetBSD: iopi2c.c,v 1.12 2025/09/15 13:23:01 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Intel i80321 I/O Processor I2C Controller Unit support. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: iopi2c.c,v 1.12 2025/09/15 13:23:01 thorpej Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/mutex.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> 50 51 #include <sys/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/i2c/i2cvar.h> 55 56 #include <arm/xscale/iopi2creg.h> 57 #include <arm/xscale/iopi2cvar.h> 58 59 static int iopiic_send_start(void *, int); 60 static int iopiic_send_stop(void *, int); 61 static int iopiic_initiate_xfer(void *, uint16_t, int); 62 static int iopiic_read_byte(void *, uint8_t *, int); 63 static int iopiic_write_byte(void *, uint8_t, int); 64 65 void 66 iopiic_attach(struct iopiic_softc *sc) 67 { 68 69 iic_tag_init(&sc->sc_i2c); 70 sc->sc_i2c.ic_cookie = sc; 71 sc->sc_i2c.ic_send_start = iopiic_send_start; 72 sc->sc_i2c.ic_send_stop = iopiic_send_stop; 73 sc->sc_i2c.ic_initiate_xfer = iopiic_initiate_xfer; 74 sc->sc_i2c.ic_read_byte = iopiic_read_byte; 75 sc->sc_i2c.ic_write_byte = iopiic_write_byte; 76 77 iicbus_attach(sc->sc_dev, &sc->sc_i2c); 78 } 79 80 #define IOPIIC_TIMEOUT 100 /* protocol timeout, in uSecs */ 81 82 static int 83 iopiic_wait(struct iopiic_softc *sc, int bit, int flags) 84 { 85 uint32_t isr; 86 int timeout, error=0; 87 88 /* XXX We never sleep, we always poll. Fix me. */ 89 90 /* 91 * For some reason, we seem to run into problems if we poll 92 * the ISR while the transfer is in progress--at least on the 93 * i80312. The condition that we're looking for never seems 94 * to appear on a read, and it's not clear why; perhaps reads 95 * of the I2C register file interfere with its proper operation? 96 * For now, just delay for a while up front. 97 * 98 * We _really_ need this to be interrupt-driven, but a problem 99 * with that is that the i80312 has no way to mask interrupts... 100 * So we need to deal with that. For DMA and AAU, too, for that 101 * matter. 102 * Note that delay(100) doesn't quite work on the npwr w/ m41t00. 103 */ 104 delay(110); 105 for (timeout = IOPIIC_TIMEOUT; timeout != 0; timeout--) { 106 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_ISR); 107 if (isr & (bit | IIC_ISR_BED)) 108 break; 109 delay(1); 110 } 111 112 if (isr & (IIC_ISR_BED | (bit & IIC_ISR_ALD))) 113 error = EIO; 114 else if (isr & (bit & ~IIC_ISR_ALD)) 115 error = 0; 116 else 117 error = ETIMEDOUT; 118 119 if (error) 120 device_printf(sc->sc_dev, 121 "iopiic_wait, (%08x) error %d: ISR = 0x%08x\n", 122 bit, error, isr); 123 124 /* 125 * The IIC_ISR is Read/Clear apart from the bottom 4 bits, which are 126 * read-only. So simply write back our copy of the ISR to clear any 127 * latched status. 128 */ 129 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISR, isr); 130 131 return (error); 132 } 133 134 static int 135 iopiic_send_start(void *cookie, int flags) 136 { 137 struct iopiic_softc *sc = cookie; 138 139 /* 140 * This may only work in conjunction with a data transfer; 141 * we might need to un-export the "start" primitive. 142 */ 143 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 144 sc->sc_icr | IIC_ICR_START); 145 delay(IOPIIC_TIMEOUT); 146 147 return (0); 148 } 149 150 static int 151 iopiic_send_stop(void *cookie, int flags) 152 { 153 struct iopiic_softc *sc = cookie; 154 155 /* 156 * The STOP bit is only used in conjunction with 157 * a data transfer, so we need to use MA in this 158 * case. 159 * 160 * Consider adding an I2C_F_STOP so we can 161 * do a read-with-STOP and write-with-STOP. 162 */ 163 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 164 sc->sc_icr | IIC_ICR_MA); 165 delay(IOPIIC_TIMEOUT); 166 167 return (0); 168 } 169 170 static int 171 iopiic_initiate_xfer(void *cookie, uint16_t addr, int flags) 172 { 173 struct iopiic_softc *sc = cookie; 174 int error, rd_req = (flags & I2C_F_READ) != 0; 175 uint32_t idbr; 176 177 /* We only support 7-bit addressing. */ 178 if ((addr & 0x78) == 0x78) 179 return (EINVAL); 180 181 idbr = (addr << 1) | (rd_req ? 1 : 0); 182 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, idbr); 183 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 184 sc->sc_icr | IIC_ICR_START | IIC_ICR_TB); 185 186 error = iopiic_wait(sc, IIC_ISR_ITE, flags); 187 #if 0 188 if (error) 189 device_printf(sc->sc_dev, "failed to initiate %s xfer\n", 190 rd_req ? "read" : "write"); 191 #endif 192 return (error); 193 } 194 195 static int 196 iopiic_read_byte(void *cookie, uint8_t *bytep, int flags) 197 { 198 struct iopiic_softc *sc = cookie; 199 int error, last_byte = (flags & I2C_F_LAST) != 0, 200 send_stop = (flags & I2C_F_STOP) != 0; 201 202 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 203 sc->sc_icr | IIC_ICR_TB | (last_byte ? IIC_ICR_NACK : 0) | 204 (send_stop ? IIC_ICR_STOP : 0)); 205 if ((error = iopiic_wait(sc, IIC_ISR_IRF | IIC_ISR_ALD, flags)) == 0) 206 *bytep = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_IDBR); 207 #if 0 208 if (error) 209 device_printf(sc->sc_dev, "read byte failed\n"); 210 #endif 211 212 return (error); 213 } 214 215 static int 216 iopiic_write_byte(void *cookie, uint8_t byte, int flags) 217 { 218 struct iopiic_softc *sc = cookie; 219 int error, send_stop = (flags & I2C_F_STOP) != 0; 220 221 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, byte); 222 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 223 sc->sc_icr | IIC_ICR_TB | (send_stop ? IIC_ICR_STOP : 0)); 224 error = iopiic_wait(sc, IIC_ISR_ITE | IIC_ISR_ALD, flags); 225 226 #if 0 227 if (error) 228 device_printf(sc->sc_dev, "write byte failed\n"); 229 #endif 230 231 return (error); 232 } 233
Indexes created Sat Sep 20 22:09:52 GMT 2025