iopi2c.c revision 1.4
1 /* $NetBSD: iopi2c.c,v 1.4 2006/06/26 18:21:39 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Intel i80321 I/O Processor I2C Controller Unit support. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: iopi2c.c,v 1.4 2006/06/26 18:21:39 drochner Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/lock.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/i2c/i2cvar.h> 55 56 #include <arm/xscale/iopi2creg.h> 57 #include <arm/xscale/iopi2cvar.h> 58 59 static int iopiic_acquire_bus(void *, int); 60 static void iopiic_release_bus(void *, int); 61 62 static int iopiic_send_start(void *, int); 63 static int iopiic_send_stop(void *, int); 64 static int iopiic_initiate_xfer(void *, uint16_t, int); 65 static int iopiic_read_byte(void *, uint8_t *, int); 66 static int iopiic_write_byte(void *, uint8_t, int); 67 68 void 69 iopiic_attach(struct iopiic_softc *sc) 70 { 71 struct i2cbus_attach_args iba; 72 73 sc->sc_i2c.ic_cookie = sc; 74 sc->sc_i2c.ic_acquire_bus = iopiic_acquire_bus; 75 sc->sc_i2c.ic_release_bus = iopiic_release_bus; 76 sc->sc_i2c.ic_send_start = iopiic_send_start; 77 sc->sc_i2c.ic_send_stop = iopiic_send_stop; 78 sc->sc_i2c.ic_initiate_xfer = iopiic_initiate_xfer; 79 sc->sc_i2c.ic_read_byte = iopiic_read_byte; 80 sc->sc_i2c.ic_write_byte = iopiic_write_byte; 81 82 iba.iba_tag = &sc->sc_i2c; 83 (void) config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 84 } 85 86 static int 87 iopiic_acquire_bus(void *cookie, int flags) 88 { 89 struct iopiic_softc *sc = cookie; 90 91 /* XXX What should we do for the polling case? */ 92 if (flags & I2C_F_POLL) 93 return (0); 94 95 return (lockmgr(&sc->sc_buslock, LK_EXCLUSIVE, NULL)); 96 } 97 98 static void 99 iopiic_release_bus(void *cookie, int flags) 100 { 101 struct iopiic_softc *sc = cookie; 102 103 /* XXX See above. */ 104 if (flags & I2C_F_POLL) 105 return; 106 107 (void) lockmgr(&sc->sc_buslock, LK_RELEASE, NULL); 108 } 109 110 #define IOPIIC_TIMEOUT 100 /* protocol timeout, in uSecs */ 111 112 static int 113 iopiic_wait(struct iopiic_softc *sc, int bit, int flags) 114 { 115 uint32_t isr; 116 int timeout, error=0; 117 118 /* XXX We never sleep, we always poll. Fix me. */ 119 120 /* 121 * For some reason, we seem to run into problems if we poll 122 * the ISR while the transfer is in progress--at least on the 123 * i80312. The condition that we're looking for never seems 124 * to appear on a read, and it's not clear why; perhaps reads 125 * of the I2C register file interfere with its proper operation? 126 * For now, just delay for a while up front. 127 * 128 * We _really_ need this to be interrupt-driven, but a problem 129 * with that is that the i80312 has no way to mask interrupts... 130 * So we need to deal with that. For DMA and AAU, too, for that 131 * matter. 132 * Note that delay(100) doesn't quite work on the npwr w/ m41t00. 133 */ 134 delay(110); 135 for (timeout = IOPIIC_TIMEOUT; timeout != 0; timeout--) { 136 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_ISR); 137 if (isr & (bit | IIC_ISR_BED)) 138 break; 139 delay(1); 140 } 141 142 if (isr & (IIC_ISR_BED | (bit & IIC_ISR_ALD))) 143 error = EIO; 144 else if (isr & (bit & ~IIC_ISR_ALD)) 145 error = 0; 146 else 147 error = ETIMEDOUT; 148 149 if (error) 150 printf("%s: iopiic_wait, (%08x) error %d: ISR = 0x%08x\n", 151 sc->sc_dev.dv_xname, bit, error, isr); 152 153 /* 154 * The IIC_ISR is Read/Clear apart from the bottom 4 bits, which are 155 * read-only. So simply write back our copy of the ISR to clear any 156 * latched status. 157 */ 158 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISR, isr); 159 160 return (error); 161 } 162 163 static int 164 iopiic_send_start(void *cookie, int flags) 165 { 166 struct iopiic_softc *sc = cookie; 167 168 /* 169 * This may only work in conjunction with a data transfer; 170 * we might need to un-export the "start" primitive. 171 */ 172 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 173 sc->sc_icr | IIC_ICR_START); 174 delay(IOPIIC_TIMEOUT); 175 176 return (0); 177 } 178 179 static int 180 iopiic_send_stop(void *cookie, int flags) 181 { 182 struct iopiic_softc *sc = cookie; 183 184 /* 185 * The STOP bit is only used in conjunction with 186 * a data transfer, so we need to use MA in this 187 * case. 188 * 189 * Consider adding an I2C_F_STOP so we can 190 * do a read-with-STOP and write-with-STOP. 191 */ 192 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 193 sc->sc_icr | IIC_ICR_MA); 194 delay(IOPIIC_TIMEOUT); 195 196 return (0); 197 } 198 199 static int 200 iopiic_initiate_xfer(void *cookie, uint16_t addr, int flags) 201 { 202 struct iopiic_softc *sc = cookie; 203 int error, rd_req = (flags & I2C_F_READ) != 0; 204 uint32_t idbr; 205 206 /* We only support 7-bit addressing. */ 207 if ((addr & 0x78) == 0x78) 208 return (EINVAL); 209 210 idbr = (addr << 1) | (rd_req ? 1 : 0); 211 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, idbr); 212 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 213 sc->sc_icr | IIC_ICR_START | IIC_ICR_TB); 214 215 error = iopiic_wait(sc, IIC_ISR_ITE, flags); 216 #if 0 217 if (error) 218 printf("%s: failed to initiate %s xfer\n", sc->sc_dev.dv_xname, 219 rd_req ? "read" : "write"); 220 #endif 221 return (error); 222 } 223 224 static int 225 iopiic_read_byte(void *cookie, uint8_t *bytep, int flags) 226 { 227 struct iopiic_softc *sc = cookie; 228 int error, last_byte = (flags & I2C_F_LAST) != 0, 229 send_stop = (flags & I2C_F_STOP) != 0; 230 231 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 232 sc->sc_icr | IIC_ICR_TB | (last_byte ? IIC_ICR_NACK : 0) | 233 (send_stop ? IIC_ICR_STOP : 0)); 234 if ((error = iopiic_wait(sc, IIC_ISR_IRF | IIC_ISR_ALD, flags)) == 0) 235 *bytep = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_IDBR); 236 #if 0 237 if (error) 238 printf("%s: read byte failed\n", sc->sc_dev.dv_xname); 239 #endif 240 241 return (error); 242 } 243 244 static int 245 iopiic_write_byte(void *cookie, uint8_t byte, int flags) 246 { 247 struct iopiic_softc *sc = cookie; 248 int error, send_stop = (flags & I2C_F_STOP) != 0; 249 250 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, byte); 251 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 252 sc->sc_icr | IIC_ICR_TB | (send_stop ? IIC_ICR_STOP : 0)); 253 error = iopiic_wait(sc, IIC_ISR_ITE | IIC_ISR_ALD, flags); 254 255 #if 0 256 if (error) 257 printf("%s: write byte failed\n", sc->sc_dev.dv_xname); 258 #endif 259 260 return (error); 261 } 262
Indexes created Fri Sep 26 20:09:58 GMT 2025