iopi2c.c revision 1.9
1 /* $NetBSD: iopi2c.c,v 1.9 2019/12/22 23:23:30 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Intel i80321 I/O Processor I2C Controller Unit support. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: iopi2c.c,v 1.9 2019/12/22 23:23:30 thorpej Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/mutex.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> 50 51 #include <sys/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/i2c/i2cvar.h> 55 56 #include <arm/xscale/iopi2creg.h> 57 #include <arm/xscale/iopi2cvar.h> 58 59 static int iopiic_send_start(void *, int); 60 static int iopiic_send_stop(void *, int); 61 static int iopiic_initiate_xfer(void *, uint16_t, int); 62 static int iopiic_read_byte(void *, uint8_t *, int); 63 static int iopiic_write_byte(void *, uint8_t, int); 64 65 void 66 iopiic_attach(struct iopiic_softc *sc) 67 { 68 struct i2cbus_attach_args iba; 69 70 iic_tag_init(&sc->sc_i2c); 71 sc->sc_i2c.ic_cookie = sc; 72 sc->sc_i2c.ic_send_start = iopiic_send_start; 73 sc->sc_i2c.ic_send_stop = iopiic_send_stop; 74 sc->sc_i2c.ic_initiate_xfer = iopiic_initiate_xfer; 75 sc->sc_i2c.ic_read_byte = iopiic_read_byte; 76 sc->sc_i2c.ic_write_byte = iopiic_write_byte; 77 78 memset(&iba, 0, sizeof(iba)); 79 iba.iba_tag = &sc->sc_i2c; 80 (void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print); 81 } 82 83 #define IOPIIC_TIMEOUT 100 /* protocol timeout, in uSecs */ 84 85 static int 86 iopiic_wait(struct iopiic_softc *sc, int bit, int flags) 87 { 88 uint32_t isr; 89 int timeout, error=0; 90 91 /* XXX We never sleep, we always poll. Fix me. */ 92 93 /* 94 * For some reason, we seem to run into problems if we poll 95 * the ISR while the transfer is in progress--at least on the 96 * i80312. The condition that we're looking for never seems 97 * to appear on a read, and it's not clear why; perhaps reads 98 * of the I2C register file interfere with its proper operation? 99 * For now, just delay for a while up front. 100 * 101 * We _really_ need this to be interrupt-driven, but a problem 102 * with that is that the i80312 has no way to mask interrupts... 103 * So we need to deal with that. For DMA and AAU, too, for that 104 * matter. 105 * Note that delay(100) doesn't quite work on the npwr w/ m41t00. 106 */ 107 delay(110); 108 for (timeout = IOPIIC_TIMEOUT; timeout != 0; timeout--) { 109 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_ISR); 110 if (isr & (bit | IIC_ISR_BED)) 111 break; 112 delay(1); 113 } 114 115 if (isr & (IIC_ISR_BED | (bit & IIC_ISR_ALD))) 116 error = EIO; 117 else if (isr & (bit & ~IIC_ISR_ALD)) 118 error = 0; 119 else 120 error = ETIMEDOUT; 121 122 if (error) 123 device_printf(sc->sc_dev, 124 "iopiic_wait, (%08x) error %d: ISR = 0x%08x\n", 125 bit, error, isr); 126 127 /* 128 * The IIC_ISR is Read/Clear apart from the bottom 4 bits, which are 129 * read-only. So simply write back our copy of the ISR to clear any 130 * latched status. 131 */ 132 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISR, isr); 133 134 return (error); 135 } 136 137 static int 138 iopiic_send_start(void *cookie, int flags) 139 { 140 struct iopiic_softc *sc = cookie; 141 142 /* 143 * This may only work in conjunction with a data transfer; 144 * we might need to un-export the "start" primitive. 145 */ 146 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 147 sc->sc_icr | IIC_ICR_START); 148 delay(IOPIIC_TIMEOUT); 149 150 return (0); 151 } 152 153 static int 154 iopiic_send_stop(void *cookie, int flags) 155 { 156 struct iopiic_softc *sc = cookie; 157 158 /* 159 * The STOP bit is only used in conjunction with 160 * a data transfer, so we need to use MA in this 161 * case. 162 * 163 * Consider adding an I2C_F_STOP so we can 164 * do a read-with-STOP and write-with-STOP. 165 */ 166 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 167 sc->sc_icr | IIC_ICR_MA); 168 delay(IOPIIC_TIMEOUT); 169 170 return (0); 171 } 172 173 static int 174 iopiic_initiate_xfer(void *cookie, uint16_t addr, int flags) 175 { 176 struct iopiic_softc *sc = cookie; 177 int error, rd_req = (flags & I2C_F_READ) != 0; 178 uint32_t idbr; 179 180 /* We only support 7-bit addressing. */ 181 if ((addr & 0x78) == 0x78) 182 return (EINVAL); 183 184 idbr = (addr << 1) | (rd_req ? 1 : 0); 185 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, idbr); 186 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 187 sc->sc_icr | IIC_ICR_START | IIC_ICR_TB); 188 189 error = iopiic_wait(sc, IIC_ISR_ITE, flags); 190 #if 0 191 if (error) 192 device_printf(sc->sc_dev, "failed to initiate %s xfer\n", 193 rd_req ? "read" : "write"); 194 #endif 195 return (error); 196 } 197 198 static int 199 iopiic_read_byte(void *cookie, uint8_t *bytep, int flags) 200 { 201 struct iopiic_softc *sc = cookie; 202 int error, last_byte = (flags & I2C_F_LAST) != 0, 203 send_stop = (flags & I2C_F_STOP) != 0; 204 205 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 206 sc->sc_icr | IIC_ICR_TB | (last_byte ? IIC_ICR_NACK : 0) | 207 (send_stop ? IIC_ICR_STOP : 0)); 208 if ((error = iopiic_wait(sc, IIC_ISR_IRF | IIC_ISR_ALD, flags)) == 0) 209 *bytep = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_IDBR); 210 #if 0 211 if (error) 212 device_printf(sc->sc_dev, "read byte failed\n"); 213 #endif 214 215 return (error); 216 } 217 218 static int 219 iopiic_write_byte(void *cookie, uint8_t byte, int flags) 220 { 221 struct iopiic_softc *sc = cookie; 222 int error, send_stop = (flags & I2C_F_STOP) != 0; 223 224 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, byte); 225 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 226 sc->sc_icr | IIC_ICR_TB | (send_stop ? IIC_ICR_STOP : 0)); 227 error = iopiic_wait(sc, IIC_ISR_ITE | IIC_ISR_ALD, flags); 228 229 #if 0 230 if (error) 231 device_printf(sc->sc_dev, "write byte failed\n"); 232 #endif 233 234 return (error); 235 } 236
Indexes created Thu Sep 25 02:09:54 GMT 2025