ixp425_timer.c revision 1.18
1 /* $NetBSD: ixp425_timer.c,v 1.18 2012/11/12 18:00:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_timer.c,v 1.18 2012/11/12 18:00:38 skrll Exp $"); 32 33 #include "opt_ixp425.h" 34 #include "opt_perfctrs.h" 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/atomic.h> 41 #include <sys/time.h> 42 #include <sys/timetc.h> 43 #include <sys/device.h> 44 45 #include <dev/clock_subr.h> 46 47 #include <sys/bus.h> 48 #include <machine/intr.h> 49 50 #include <arm/cpufunc.h> 51 52 #include <arm/xscale/ixp425reg.h> 53 #include <arm/xscale/ixp425var.h> 54 #include <arm/xscale/ixp425_sipvar.h> 55 56 static int ixpclk_match(device_t, cfdata_t, void *); 57 static void ixpclk_attach(device_t, device_t, void *); 58 static u_int ixpclk_get_timecount(struct timecounter *); 59 60 static uint32_t counts_per_hz; 61 62 static void *clock_ih; 63 64 /* callback functions for intr_functions */ 65 int ixpclk_intr(void *); 66 67 struct ixpclk_softc { 68 bus_addr_t sc_baseaddr; 69 bus_space_tag_t sc_iot; 70 bus_space_handle_t sc_ioh; 71 }; 72 73 #ifndef IXP425_CLOCK_FREQ 74 #define COUNTS_PER_SEC 66666600 /* 66MHz */ 75 #else 76 #define COUNTS_PER_SEC IXP425_CLOCK_FREQ 77 #endif 78 #define COUNTS_PER_USEC ((COUNTS_PER_SEC / 1000000) + 1) 79 80 static struct ixpclk_softc *ixpclk_sc; 81 82 static struct timecounter ixpclk_timecounter = { 83 ixpclk_get_timecount, /* get_timecount */ 84 0, /* no poll_pps */ 85 0xffffffff, /* counter_mask */ 86 COUNTS_PER_SEC, /* frequency */ 87 "ixpclk", /* name */ 88 100, /* quality */ 89 NULL, /* prev */ 90 NULL, /* next */ 91 }; 92 93 static volatile uint32_t ixpclk_base; 94 95 CFATTACH_DECL_NEW(ixpclk, sizeof(struct ixpclk_softc), 96 ixpclk_match, ixpclk_attach, NULL, NULL); 97 98 #define GET_TIMER_VALUE(sc) (bus_space_read_4((sc)->sc_iot, \ 99 (sc)->sc_ioh, \ 100 IXP425_OST_TIM0)) 101 102 #define GET_TS_VALUE(sc) (*(volatile uint32_t *) \ 103 (IXP425_TIMER_VBASE + IXP425_OST_TS)) 104 105 static int 106 ixpclk_match(device_t parent, cfdata_t match, void *aux) 107 { 108 return 2; 109 } 110 111 static void 112 ixpclk_attach(device_t parent, device_t self, void *aux) 113 { 114 struct ixpclk_softc *sc = device_private(self); 115 struct ixpsip_attach_args *sa = aux; 116 117 printf("\n"); 118 119 ixpclk_sc = sc; 120 121 sc->sc_iot = sa->sa_iot; 122 sc->sc_baseaddr = sa->sa_addr; 123 124 if (bus_space_map(sc->sc_iot, sa->sa_addr, sa->sa_size, 0, 125 &sc->sc_ioh)) 126 panic("%s: Cannot map registers", device_xname(self)); 127 128 aprint_normal_dev(self, "IXP425 Interval Timer\n"); 129 } 130 131 /* 132 * cpu_initclocks: 133 * 134 * Initialize the clock and get them going. 135 */ 136 void 137 cpu_initclocks(void) 138 { 139 struct ixpclk_softc *sc = ixpclk_sc; 140 u_int oldirqstate; 141 #if defined(PERFCTRS) 142 void *pmu_ih; 143 #endif 144 145 if (hz < 50 || COUNTS_PER_SEC % hz) { 146 aprint_error("Cannot get %d Hz clock; using 100 Hz\n", hz); 147 hz = 100; 148 } 149 150 /* 151 * We only have one timer available; stathz and profhz are 152 * always left as 0 (the upper-layer clock code deals with 153 * this situation). 154 */ 155 if (stathz != 0) 156 aprint_error("Cannot get %d Hz statclock\n", stathz); 157 stathz = 0; 158 159 if (profhz != 0) 160 aprint_error("Cannot get %d Hz profclock\n", profhz); 161 profhz = 0; 162 163 /* Report the clock frequency. */ 164 aprint_normal("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz); 165 166 oldirqstate = disable_interrupts(I32_bit); 167 168 /* Hook up the clock interrupt handler. */ 169 clock_ih = ixp425_intr_establish(IXP425_INT_TMR0, IPL_CLOCK, 170 ixpclk_intr, NULL); 171 if (clock_ih == NULL) 172 panic("cpu_initclocks: unable to register timer interrupt"); 173 174 #if defined(PERFCTRS) 175 pmu_ih = ixp425_intr_establish(IXP425_INT_XPMU, IPL_STATCLOCK, 176 xscale_pmc_dispatch, NULL); 177 if (pmu_ih == NULL) 178 panic("cpu_initclocks: unable to register timer interrupt"); 179 #endif 180 181 /* Set up the new clock parameters. */ 182 183 /* clear interrupt */ 184 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, 185 OST_WARM_RESET | OST_WDOG_INT | OST_TS_INT | 186 OST_TIM1_INT | OST_TIM0_INT); 187 188 counts_per_hz = COUNTS_PER_SEC / hz; 189 190 /* reload value & Timer enable */ 191 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_TIM0_RELOAD, 192 (counts_per_hz & TIMERRELOAD_MASK) | OST_TIMER_EN); 193 194 restore_interrupts(oldirqstate); 195 196 tc_init(&ixpclk_timecounter); 197 } 198 199 /* 200 * setstatclockrate: 201 * 202 * Set the rate of the statistics clock. 203 * 204 * We assume that hz is either stathz or profhz, and that neither 205 * will change after being set by cpu_initclocks(). We could 206 * recalculate the intervals here, but that would be a pain. 207 */ 208 void 209 setstatclockrate(int newhz) 210 { 211 212 /* 213 * XXX Use TMR1? 214 */ 215 } 216 217 static u_int 218 ixpclk_get_timecount(struct timecounter *tc) 219 { 220 u_int savedints, base, counter; 221 222 savedints = disable_interrupts(I32_bit); 223 base = ixpclk_base; 224 counter = GET_TIMER_VALUE(ixpclk_sc); 225 restore_interrupts(savedints); 226 227 return base - counter; 228 } 229 230 /* 231 * delay: 232 * 233 * Delay for at least N microseconds. 234 */ 235 void 236 delay(u_int n) 237 { 238 uint32_t first, last; 239 int usecs; 240 241 if (n == 0) 242 return; 243 244 /* 245 * Clamp the timeout at a maximum value (about 32 seconds with 246 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 247 * near that length of time and if they are, they should be hung 248 * out to dry. 249 */ 250 if (n >= (0x80000000U / COUNTS_PER_USEC)) 251 usecs = (0x80000000U / COUNTS_PER_USEC) - 1; 252 else 253 usecs = n * COUNTS_PER_USEC; 254 255 /* Note: Timestamp timer counts *up*, unlike the other timers */ 256 first = GET_TS_VALUE(); 257 258 while (usecs > 0) { 259 last = GET_TS_VALUE(); 260 usecs -= (int)(last - first); 261 first = last; 262 } 263 } 264 265 /* 266 * ixpclk_intr: 267 * 268 * Handle the hardclock interrupt. 269 */ 270 int 271 ixpclk_intr(void *arg) 272 { 273 struct ixpclk_softc *sc = ixpclk_sc; 274 struct clockframe *frame = arg; 275 276 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, 277 OST_TIM0_INT); 278 279 atomic_add_32(&ixpclk_base, counts_per_hz); 280 281 hardclock(frame); 282 283 return (1); 284 } 285
Indexes created Thu Sep 25 16:09:42 GMT 2025