ixp425_timer.c revision 1.18.36.1
1 /* $NetBSD: ixp425_timer.c,v 1.18.36.1 2018/07/28 04:37:29 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_timer.c,v 1.18.36.1 2018/07/28 04:37:29 pgoyette Exp $"); 32 33 #include "opt_ixp425.h" 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/atomic.h> 40 #include <sys/time.h> 41 #include <sys/timetc.h> 42 #include <sys/device.h> 43 44 #include <dev/clock_subr.h> 45 46 #include <sys/bus.h> 47 #include <machine/intr.h> 48 49 #include <arm/cpufunc.h> 50 51 #include <arm/xscale/ixp425reg.h> 52 #include <arm/xscale/ixp425var.h> 53 #include <arm/xscale/ixp425_sipvar.h> 54 55 static int ixpclk_match(device_t, cfdata_t, void *); 56 static void ixpclk_attach(device_t, device_t, void *); 57 static u_int ixpclk_get_timecount(struct timecounter *); 58 59 static uint32_t counts_per_hz; 60 61 static void *clock_ih; 62 63 /* callback functions for intr_functions */ 64 int ixpclk_intr(void *); 65 66 struct ixpclk_softc { 67 bus_addr_t sc_baseaddr; 68 bus_space_tag_t sc_iot; 69 bus_space_handle_t sc_ioh; 70 }; 71 72 #ifndef IXP425_CLOCK_FREQ 73 #define COUNTS_PER_SEC 66666600 /* 66MHz */ 74 #else 75 #define COUNTS_PER_SEC IXP425_CLOCK_FREQ 76 #endif 77 #define COUNTS_PER_USEC ((COUNTS_PER_SEC / 1000000) + 1) 78 79 static struct ixpclk_softc *ixpclk_sc; 80 81 static struct timecounter ixpclk_timecounter = { 82 ixpclk_get_timecount, /* get_timecount */ 83 0, /* no poll_pps */ 84 0xffffffff, /* counter_mask */ 85 COUNTS_PER_SEC, /* frequency */ 86 "ixpclk", /* name */ 87 100, /* quality */ 88 NULL, /* prev */ 89 NULL, /* next */ 90 }; 91 92 static volatile uint32_t ixpclk_base; 93 94 CFATTACH_DECL_NEW(ixpclk, sizeof(struct ixpclk_softc), 95 ixpclk_match, ixpclk_attach, NULL, NULL); 96 97 #define GET_TIMER_VALUE(sc) (bus_space_read_4((sc)->sc_iot, \ 98 (sc)->sc_ioh, \ 99 IXP425_OST_TIM0)) 100 101 #define GET_TS_VALUE(sc) (*(volatile uint32_t *) \ 102 (IXP425_TIMER_VBASE + IXP425_OST_TS)) 103 104 static int 105 ixpclk_match(device_t parent, cfdata_t match, void *aux) 106 { 107 return 2; 108 } 109 110 static void 111 ixpclk_attach(device_t parent, device_t self, void *aux) 112 { 113 struct ixpclk_softc *sc = device_private(self); 114 struct ixpsip_attach_args *sa = aux; 115 116 printf("\n"); 117 118 ixpclk_sc = sc; 119 120 sc->sc_iot = sa->sa_iot; 121 sc->sc_baseaddr = sa->sa_addr; 122 123 if (bus_space_map(sc->sc_iot, sa->sa_addr, sa->sa_size, 0, 124 &sc->sc_ioh)) 125 panic("%s: Cannot map registers", device_xname(self)); 126 127 aprint_normal_dev(self, "IXP425 Interval Timer\n"); 128 } 129 130 /* 131 * cpu_initclocks: 132 * 133 * Initialize the clock and get them going. 134 */ 135 void 136 cpu_initclocks(void) 137 { 138 struct ixpclk_softc *sc = ixpclk_sc; 139 u_int oldirqstate; 140 141 if (hz < 50 || COUNTS_PER_SEC % hz) { 142 aprint_error("Cannot get %d Hz clock; using 100 Hz\n", hz); 143 hz = 100; 144 } 145 146 /* 147 * We only have one timer available; stathz and profhz are 148 * always left as 0 (the upper-layer clock code deals with 149 * this situation). 150 */ 151 if (stathz != 0) 152 aprint_error("Cannot get %d Hz statclock\n", stathz); 153 stathz = 0; 154 155 if (profhz != 0) 156 aprint_error("Cannot get %d Hz profclock\n", profhz); 157 profhz = 0; 158 159 /* Report the clock frequency. */ 160 aprint_normal("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz); 161 162 oldirqstate = disable_interrupts(I32_bit); 163 164 /* Hook up the clock interrupt handler. */ 165 clock_ih = ixp425_intr_establish(IXP425_INT_TMR0, IPL_CLOCK, 166 ixpclk_intr, NULL); 167 if (clock_ih == NULL) 168 panic("cpu_initclocks: unable to register timer interrupt"); 169 170 /* Set up the new clock parameters. */ 171 172 /* clear interrupt */ 173 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, 174 OST_WARM_RESET | OST_WDOG_INT | OST_TS_INT | 175 OST_TIM1_INT | OST_TIM0_INT); 176 177 counts_per_hz = COUNTS_PER_SEC / hz; 178 179 /* reload value & Timer enable */ 180 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_TIM0_RELOAD, 181 (counts_per_hz & TIMERRELOAD_MASK) | OST_TIMER_EN); 182 183 restore_interrupts(oldirqstate); 184 185 tc_init(&ixpclk_timecounter); 186 } 187 188 /* 189 * setstatclockrate: 190 * 191 * Set the rate of the statistics clock. 192 * 193 * We assume that hz is either stathz or profhz, and that neither 194 * will change after being set by cpu_initclocks(). We could 195 * recalculate the intervals here, but that would be a pain. 196 */ 197 void 198 setstatclockrate(int newhz) 199 { 200 201 /* 202 * XXX Use TMR1? 203 */ 204 } 205 206 static u_int 207 ixpclk_get_timecount(struct timecounter *tc) 208 { 209 u_int savedints, base, counter; 210 211 savedints = disable_interrupts(I32_bit); 212 base = ixpclk_base; 213 counter = GET_TIMER_VALUE(ixpclk_sc); 214 restore_interrupts(savedints); 215 216 return base - counter; 217 } 218 219 /* 220 * delay: 221 * 222 * Delay for at least N microseconds. 223 */ 224 void 225 delay(u_int n) 226 { 227 uint32_t first, last; 228 int usecs; 229 230 if (n == 0) 231 return; 232 233 /* 234 * Clamp the timeout at a maximum value (about 32 seconds with 235 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 236 * near that length of time and if they are, they should be hung 237 * out to dry. 238 */ 239 if (n >= (0x80000000U / COUNTS_PER_USEC)) 240 usecs = (0x80000000U / COUNTS_PER_USEC) - 1; 241 else 242 usecs = n * COUNTS_PER_USEC; 243 244 /* Note: Timestamp timer counts *up*, unlike the other timers */ 245 first = GET_TS_VALUE(); 246 247 while (usecs > 0) { 248 last = GET_TS_VALUE(); 249 usecs -= (int)(last - first); 250 first = last; 251 } 252 } 253 254 /* 255 * ixpclk_intr: 256 * 257 * Handle the hardclock interrupt. 258 */ 259 int 260 ixpclk_intr(void *arg) 261 { 262 struct ixpclk_softc *sc = ixpclk_sc; 263 struct clockframe *frame = arg; 264 265 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, 266 OST_TIM0_INT); 267 268 atomic_add_32(&ixpclk_base, counts_per_hz); 269 270 hardclock(frame); 271 272 return (1); 273 } 274
Indexes created Sun Oct 12 09:09:55 GMT 2025