ixp425reg.h revision 1.11
1 /* $NetBSD: ixp425reg.h,v 1.11 2003/09/25 14:48:16 ichiro Exp $ */ 2 /* 3 * Copyright (c) 2003 4 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #ifndef _IXP425REG_H_ 36 #define _IXP425REG_H_ 37 38 /* 39 * Physical memory map for the Intel IXP425 40 */ 41 /* 42 * CC00 00FF --------------------------- 43 * SDRAM Configuration Registers 44 * CC00 0000 --------------------------- 45 * 46 * C800 BFFF --------------------------- 47 * System and Peripheral Registers 48 * C800 0000 --------------------------- 49 * Expansion Bus Configuration Registers 50 * C400 0000 --------------------------- 51 * PCI Configuration and Status Registers 52 * C000 0000 --------------------------- 53 * 54 * 6400 0000 --------------------------- 55 * Queue manager 56 * 6000 0000 --------------------------- 57 * Expansion Bus Data 58 * 5000 0000 --------------------------- 59 * PCI Data 60 * 4800 0000 --------------------------- 61 * 62 * 4000 0000 --------------------------- 63 * SDRAM 64 * 1000 0000 --------------------------- 65 */ 66 67 /* 68 * Virtual memory map for the Intel IXP425 integrated devices 69 */ 70 /* 71 * FFFF FFFF --------------------------- 72 * 73 * F001 2000 --------------------------- 74 * PCI Configuration and Status Registers 75 * F001 1000 --------------------------- 76 * Expansion bus Configuration Registers 77 * F001 0000 --------------------------- 78 * System and Peripheral Registers 79 * VA F000 0000 = PA C800 0000 (SIZE 0x10000) 80 * F000 0000 --------------------------- 81 * 82 * 0000 0000 --------------------------- 83 * 84 */ 85 86 /* Physical/Virtual address for I/O space */ 87 88 #define IXP425_IO_VBASE 0xf0000000UL 89 #define IXP425_IO_HWBASE 0xc8000000UL 90 #define IXP425_IO_SIZE 0x00010000UL 91 92 /* Offset */ 93 94 #define IXP425_UART0_OFFSET 0x00000000UL 95 #define IXP425_UART1_OFFSET 0x00001000UL 96 #define IXP425_PMC_OFFSET 0x00002000UL 97 #define IXP425_INTR_OFFSET 0x00003000UL 98 #define IXP425_GPIO_OFFSET 0x00004000UL 99 #define IXP425_TIMER_OFFSET 0x00005000UL 100 #define IXP425_HSS_OFFSET 0x00006000UL /* Not User Programmable */ 101 #define IXP425_NPE_A_OFFSET 0x00007000UL /* Not User Programmable */ 102 #define IXP425_NPE_B_OFFSET 0x00008000UL /* Not User Programmable */ 103 #define IXP425_MAC_A_OFFSET 0x00009000UL 104 #define IXP425_MAC_B_OFFSET 0x0000a000UL 105 #define IXP425_USB_OFFSET 0x0000b000UL 106 107 #define IXP425_REG_SIZE 0x1000 108 109 /* 110 * UART 111 * UART0 0xc8000000 112 * UART1 0xc8001000 113 * 114 */ 115 /* I/O space */ 116 #define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET) 117 #define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET) 118 119 #define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET) 120 /* 0xf0000000 */ 121 #define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET) 122 /* 0xf0001000 */ 123 124 /* registers */ 125 /* Buffer and Divisor */ 126 #define IXP425_UART_DATA 0x0000 127 #define IXP425_UART_DLL 0x0000 /* Divisor Latch Low */ 128 #define IXP425_UART_DLH 0x0004 /* Divisor Latch High */ 129 130 /* Interrupt Enable Register */ 131 #define IXP425_UART_IER 0x0004 132 #define IER_DMAE (1U << 7) /* Enable DMA Requests */ 133 #define IER_UUE (1U << 6) /* Enable UART UNIT */ 134 #define IER_NRZE (1U << 5) /* Enable NRZ coding */ 135 #define IER_RTOIE (1U << 4) /* Enable receiver T/O interrupt */ 136 #define IER_RIE (1U << 3) /* Enable modem interrupt */ 137 #define IER_RLSE (1U << 2) /* Enable line status interrupt */ 138 #define IER_TIE (1U << 1) /* Enable transmitter interrupt */ 139 #define IER_RAVIE (1U << 0) /* Enable receiver interrupt */ 140 141 /* Interrupt Identification Register */ 142 #define IXP425_UART_IIR 0x0008 143 #define IIR_IMASK 0xf 144 #define IIR_NOPEND (1U << 0) /* No pending interrupts */ 145 #define IIR_MLSC (0U << 1) /* Modem status */ 146 #define IIR_TXRDY (1U << 1) /* Transmitter ready */ 147 #define IIR_RXRDY (2U << 1) /* Receiver ready */ 148 #define IIR_RXERR (2U << 1) /* Receiver error */ 149 #define IIR_TOD (1U << 3) /* Time Out interrupt pending */ 150 #define IIR_FIFOS (3U << 6) /* FIFO mode enable */ 151 152 /* FIFO control */ 153 #define IXP425_UART_FCR 0x0008 154 #define FCR_TRIGGER_1 (0U << 6) /* ITL 0 */ 155 #define FCR_TRIGGER_8 (1U << 6) /* ITL 0 */ 156 #define FCR_TRIGGER_16 (2U << 6) /* ITL 0 */ 157 #define FCR_TRIGGER_32 (3U << 6) /* ITL 0 */ 158 #define FCR_RESETTF (1U << 2) /* Reset TX FIFO */ 159 #define FCR_RESETRF (1U << 1) /* Reset RX FIFO */ 160 #define FCR_ENABLE (1U << 0) /* Enable FIFO */ 161 162 /* Line control */ 163 #define IXP425_UART_LCR 0x000c 164 #define LCR_DLAB (1U << 7) /* Divisor latch access enable */ 165 #define LCR_SBREAK (1U << 6) /* Break Control */ 166 #define LCR_PEVEN (1U << 4) /* Even-Parity */ 167 #define LCR_PODD (0U << 4) /* Even-Parity */ 168 #define LCR_PENE (1U << 3) /* Enable parity */ 169 #define LCR_PNONE (0U << 3) /* No parity */ 170 #define LCR_1STOP (0U << 2) /* 1 Stop Bit */ 171 #define LCR_2STOP (1U << 2) /* 2 Stop Bit */ 172 #define LCR_8BITS (3U << 0) /* 8 bits per serial word */ 173 #define LCR_7BITS (2U << 0) /* 7 bits per serial word */ 174 #define LCR_6BITS (1U << 0) /* 6 bits per serial word */ 175 #define LCR_5BITS (0U << 0) /* 5 bits per serial word */ 176 177 /* Modem control */ 178 #define IXP425_UART_MCR 0x0010 179 #define MCR_LOOPBACK (1U << 4) /* Loop test */ 180 #define MCR_IENABLE (1U << 3) /* Out2: enables UART interrupts */ 181 #define MCR_DRS (1U << 2) /* Out1: resets some internal modems */ 182 #define MCR_RTS (1U << 1) /* Request To Send */ 183 #define MCR_DTR (1U << 0) /* Data Terminal Ready */ 184 185 /* Line Status Register */ 186 #define IXP425_UART_LSR 0x0014 187 #define LSR_FIFOE (1U << 7) 188 #define LSR_TEMT (1U << 6) /* Transmitter empty: byte sent */ 189 #define LSR_TDRQ (1U << 5) /* Transmitter buffer empty */ 190 #define LSR_BI (1U << 4) /* Break detected */ 191 #define LSR_FE (1U << 3) /* Framing error: bad stop bit */ 192 #define LSR_PE (1U << 2) /* Parity error */ 193 #define LSR_OE (1U << 1) /* Overrun, lost incoming byte */ 194 #define LSR_DR (1U << 0) /* Byte ready in Receive Buffer */ 195 #define LSR_RCV_MASK 0x1f /* Incoming data and error */ 196 197 /* Modem Status Register */ 198 #define IXP425_UART_MSR 0x0018 199 #define MSR_DCD (1U << 7) /* Current Data Carrier Detect */ 200 #define MSR_RI (1U << 6) /* Current Ring Indicator */ 201 #define MSR_DSR (1U << 5) /* Current Data Set Ready */ 202 #define MSR_CTS (1U << 4) /* Current Clear to Send */ 203 #define MSR_DDCD (1U << 3) /* DCD has changed state */ 204 #define MSR_TERI (1U << 2) /* RI has toggled low to high */ 205 #define MSR_DDSR (1U << 1) /* DSR has changed state */ 206 #define MSR_DCTS (1U << 0) /* CTS has changed state */ 207 208 /* Scratch Pad Status Register */ 209 #define IXP425_UART_SPR 0x001C 210 211 /* Slow Infrared Select Status Register */ 212 #define IXP425_UART_ISR 0x0020 213 214 #define IXP4XX_COM_NPORTS 8 215 216 /* 217 * Timers 218 * 219 */ 220 221 #define IXP425_OST_TIM0 0x0004 222 #define IXP425_OST_TIM1 0x000C 223 224 #define IXP425_OST_TIM0_RELOAD 0x0008 225 #define IXP425_OST_TIM1_RELOAD 0x0010 226 #define TIMERRELOAD_MASK 0xFFFFFFFC 227 #define OST_ONESHOT_EN (1U << 1) 228 #define OST_TIMER_EN (1U << 0) 229 230 #define IXP425_OST_STATUS 0x0020 231 #define OST_WARM_RESET (1U << 4) 232 #define OST_WDOG_INT (1U << 3) 233 #define OST_TS_INT (1U << 2) 234 #define OST_TIM1_INT (1U << 1) 235 #define OST_TIM0_INT (1U << 0) 236 237 /* 238 * Interrupt Controller Unit. 239 * PA 0xc8003000 240 */ 241 242 #define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET 243 #define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET 244 /* 0xf0003000 */ 245 #define IXP425_IRQ_SIZE 0x00000020UL 246 247 #define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00) 248 #define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04) 249 #define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08) 250 #define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C) 251 #define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10) 252 #define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14) 253 #define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18) 254 #define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C) 255 256 #define IXP425_INT_SW1 31 /* SW Interrupt 1 */ 257 #define IXP425_INT_SW0 30 /* SW Interrupt 0 */ 258 #define IXP425_INT_GPIO_12 29 /* GPIO 12 */ 259 #define IXP425_INT_GPIO_11 28 /* GPIO 11 */ 260 #define IXP425_INT_GPIO_10 27 /* GPIO 11 */ 261 #define IXP425_INT_GPIO_9 26 /* GPIO 9 */ 262 #define IXP425_INT_GPIO_8 25 /* GPIO 8 */ 263 #define IXP425_INT_GPIO_7 24 /* GPIO 7 */ 264 #define IXP425_INT_GPIO_6 23 /* GPIO 6 */ 265 #define IXP425_INT_GPIO_5 22 /* GPIO 5 */ 266 #define IXP425_INT_GPIO_4 21 /* GPIO 4 */ 267 #define IXP425_INT_GPIO_3 20 /* GPIO 3 */ 268 #define IXP425_INT_GPIO_2 19 /* GPIO 2 */ 269 #define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */ 270 #define IXP425_INT_AHB_PMU 17 /* AHB PMU */ 271 #define IXP425_INT_WDOG 16 /* Watchdog Timer */ 272 #define IXP425_INT_UART0 15 /* HighSpeed UART */ 273 #define IXP425_INT_STAMP 14 /* Timestamp Timer */ 274 #define IXP425_INT_UART1 13 /* Console UART */ 275 #define IXP425_INT_USB 12 /* USB */ 276 #define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */ 277 #define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */ 278 #define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */ 279 #define IXP425_INT_PCIINT 8 /* PCI Interrupt */ 280 #define IXP425_INT_GPIO_1 7 /* GPIO 1 */ 281 #define IXP425_INT_GPIO_0 6 /* GPIO 0 */ 282 #define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */ 283 #define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */ 284 #define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */ 285 #define IXP425_INT_NPE_B 2 /* Ethernet NPE B */ 286 #define IXP425_INT_NPE_A 1 /* Ethernet NPE A */ 287 #define IXP425_INT_HSS 0 /* WAN/HSS NPE */ 288 289 /* 290 * software interrupt 291 */ 292 #define IXP425_INT_bit31 31 293 #define IXP425_INT_bit30 30 294 #define IXP425_INT_bit29 29 295 #define IXP425_INT_bit22 22 296 297 #define IXP425_INT_HWMASK (0xffffffff & \ 298 ~((1 << IXP425_INT_bit31) | \ 299 (1 << IXP425_INT_bit30) | \ 300 (1 << IXP425_INT_bit29) | \ 301 (1 << IXP425_INT_bit22))) 302 303 /* 304 * GPIO 305 */ 306 #define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET 307 #define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET 308 /* 0xf0004000 */ 309 #define IXP425_GPIO_SIZE 0x00000020UL 310 311 #define IXP425_GPIO_GPOUTR 0x00 312 #define IXP425_GPIO_GPOER 0x04 313 #define IXP425_GPIO_GPINR 0x08 314 #define IXP425_GPIO_GPISR 0x0c 315 #define IXP425_GPIO_GPIT1R 0x10 316 #define IXP425_GPIO_GPIT2R 0x14 317 #define IXP425_GPIO_GPCLKR 0x18 318 # define GPCLKR_MUX14 (1U << 8) 319 # define GPCLKR_CLK0TC_SHIFT 4 320 # define GPCLKR_CLK0DC_SHIFT 0 321 322 /* GPIO Output */ 323 #define GPOUT_ON 0x1 324 #define GPOUT_OFF 0x0 325 326 /* GPIO direction */ 327 #define GPOER_INPUT 0x1 328 #define GPOER_OUTPUT 0x0 329 330 /* 331 * Expansion Bus 332 */ 333 #define IXP425_EXP_HWBASE 0xc4000000UL 334 #define IXP425_EXP_VBASE (IXP425_IO_VBASE + IXP425_IO_SIZE) 335 /* 0xf0010000 */ 336 #define IXP425_EXP_SIZE IXP425_REG_SIZE /* 0x1000 */ 337 338 /* offset */ 339 #define EXP_TIMING_CS0_OFFSET 0x0000 340 #define EXP_TIMING_CS1_OFFSET 0x0004 341 #define EXP_TIMING_CS2_OFFSET 0x0008 342 #define EXP_TIMING_CS3_OFFSET 0x000c 343 #define EXP_TIMING_CS4_OFFSET 0x0010 344 #define EXP_TIMING_CS5_OFFSET 0x0014 345 #define EXP_TIMING_CS6_OFFSET 0x0018 346 #define EXP_TIMING_CS7_OFFSET 0x001c 347 348 #define IXP425_EXP_RECOVERY_SHIFT 16 349 #define IXP425_EXP_HOLD_SHIFT 20 350 #define IXP425_EXP_STROBE_SHIFT 22 351 #define IXP425_EXP_SETUP_SHIFT 26 352 #define IXP425_EXP_ADDR_SHIFT 28 353 #define IXP425_EXP_CS_EN (1U << 31) 354 355 #define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT) 356 #define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT) 357 #define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT) 358 #define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) 359 #define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT) 360 361 // EXP_CSn bits 362 #define EXP_BYTE_EN (1 << 0) 363 #define EXP_WR_EN (1 << 1) 364 #define EXP_SPLT_EN (1 << 3) 365 #define EXP_MUX_EN (1 << 4) 366 #define EXP_HRDY_POL (1 << 5) 367 #define EXP_BYTE_RD16 (1 << 6) 368 #define EXP_SZ_512 (0 << 10) 369 #define EXP_SZ_1K (1 << 10) 370 #define EXP_SZ_2K (2 << 10) 371 #define EXP_SZ_4K (3 << 10) 372 #define EXP_SZ_8K (4 << 10) 373 #define EXP_SZ_16K (5 << 10) 374 #define EXP_SZ_32K (6 << 10) 375 #define EXP_SZ_64K (7 << 10) 376 #define EXP_SZ_128K (8 << 10) 377 #define EXP_SZ_256K (9 << 10) 378 #define EXP_SZ_512K (10 << 10) 379 #define EXP_SZ_1M (11 << 10) 380 #define EXP_SZ_2M (12 << 10) 381 #define EXP_SZ_4M (13 << 10) 382 #define EXP_SZ_8M (14 << 10) 383 #define EXP_SZ_16M (15 << 10) 384 #define EXP_CYC_INTEL (0 << 14) 385 #define EXP_CYC_MOTO (1 << 14) 386 #define EXP_CYC_HPI (2 << 14) 387 388 // EXP_CNFG0 bits 389 #define EXP_CNFG0_8BIT (1 << 0) 390 #define EXP_CNFG0_PCI_HOST (1 << 1) 391 #define EXP_CNFG0_PCI_ARB (1 << 2) 392 #define EXP_CNFG0_PCI_66MHZ (1 << 4) 393 #define EXP_CNFG0_MEM_MAP (1 << 31) 394 395 // EXP_CNFG1 bits 396 #define EXP_CNFG1_SW_INT0 (1 << 0) 397 #define EXP_CNFG1_SW_INT1 (1 << 1) 398 399 /* 400 * PCI 401 */ 402 #define IXP425_PCI_HWBASE 0xc0000000 403 #define IXP425_PCI_VBASE (IXP425_EXP_VBASE + IXP425_EXP_SIZE) 404 /* 0xf0011000 */ 405 #define IXP425_PCI_SIZE IXP425_REG_SIZE /* 0x1000 */ 406 407 /* 408 * Mapping registers of IXP425 PCI Configuration 409 */ 410 /* PCI_ID_REG 0x00 */ 411 /* PCI_COMMAND_STATUS_REG 0x04 */ 412 /* PCI_CLASS_REG 0x08 */ 413 /* PCI_BHLC_REG 0x0c */ 414 #define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */ 415 #define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */ 416 #define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */ 417 #define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */ 418 #define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */ 419 #define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */ 420 /* PCI_SUBSYS_ID_REG 0x2c */ 421 /* PCI_INTERRUPT_REG 0x3c */ 422 #define PCI_RTOTTO 0x40 423 424 /* PCI Controller CSR Base Address */ 425 #define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE 426 427 /* PCI Memory Space */ 428 #define IXP425_PCI_MEM_HWBASE 0x48000000UL /* VA == PA */ 429 #define IXP425_PCI_MEM_VBASE IXP425_PCI_MEM_HWBASE 430 #define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */ 431 432 /* PCI I/O Space */ 433 #define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */ 434 435 /* PCI Controller Configuration Offset */ 436 #define PCI_NP_AD 0x00 437 #define PCI_NP_CBE 0x04 438 # define NP_CBE_SHIFT 4 439 #define PCI_NP_WDATA 0x08 440 #define PCI_NP_RDATA 0x0c 441 #define PCI_CRP_AD_CBE 0x10 442 #define PCI_CRP_AD_WDATA 0x14 443 #define PCI_CRP_AD_RDATA 0x18 444 #define PCI_CSR 0x1c 445 # define CSR_PRST (1U << 16) 446 # define CSR_IC (1U << 15) 447 # define CSR_ABE (1U << 4) 448 # define CSR_PDS (1U << 3) 449 # define CSR_ADS (1U << 2) 450 #define PCI_ISR 0x20 451 # define ISR_AHBE (1U << 3) 452 # define ISR_PPE (1U << 2) 453 # define ISR_PFE (1U << 1) 454 # define ISR_PSE (1U << 0) 455 #define PCI_INTEN 0x24 456 #define PCI_DMACTRL 0x28 457 #define PCI_AHBMEMBASE 0x2c 458 #define PCI_AHBIOBASE 0x30 459 #define PCI_PCIMEMBASE 0x34 460 #define PCI_AHBDOORBELL 0x38 461 #define PCI_PCIDOORBELL 0x3c 462 #define PCI_ATPDMA0_AHBADDR 0x40 463 #define PCI_ATPDMA0_PCIADDR 0x44 464 #define PCI_ATPDMA0_LENGTH 0x48 465 #define PCI_ATPDMA1_AHBADDR 0x4c 466 #define PCI_ATPDMA1_PCIADDR 0x50 467 #define PCI_ATPDMA1_LENGTH 0x54 468 #define PCI_PTADMA0_AHBADDR 0x58 469 #define PCI_PTADMA0_PCIADDR 0x5c 470 #define PCI_PTADMA0_LENGTH 0x60 471 #define PCI_PTADMA1_AHBADDR 0x64 472 #define PCI_PTADMA1_PCIADDR 0x68 473 #define PCI_PTADMA1_LENGTH 0x6c 474 475 /* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */ 476 #define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/ 477 #define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/ 478 #define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */ 479 #define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */ 480 #define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */ 481 #define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */ 482 #define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */ 483 #define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */ 484 485 /* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */ 486 #define COMMAND_CRP_READ 0x0 487 #define COMMAND_CRP_WRITE (1U << 16) 488 /* 489 * SDRAM Configuration Register 490 */ 491 #define IXP425_MCU_HWBASE 0xcc000000UL 492 #define MCU_SDR_CONFIG 0x00 493 #define MCU_SDR_REFRESH 0x04 494 #define MCU_SDR_IR 0x08 495 496 /* 497 * Performance Monitoring Unit (CP14) 498 * 499 * CP14.0.1 Performance Monitor Control Register(PMNC) 500 * CP14.1.1 Clock Counter(CCNT) 501 * CP14.4.1 Interrupt Enable Register(INTEN) 502 * CP14.5.1 Overflow Flag Register(FLAG) 503 * CP14.8.1 Event Selection Register(EVTSEL) 504 * CP14.0.2 Performance Counter Register 0(PMN0) 505 * CP14.1.2 Performance Counter Register 0(PMN1) 506 * CP14.2.2 Performance Counter Register 0(PMN2) 507 * CP14.3.2 Performance Counter Register 0(PMN3) 508 */ 509 510 #define PMNC_E 0x00000001 /* enable all counters */ 511 #define PMNC_P 0x00000002 /* reset all PMNs to 0 */ 512 #define PMNC_C 0x00000004 /* clock counter reset */ 513 #define PMNC_D 0x00000008 /* clock counter / 64 */ 514 515 #define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */ 516 #define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */ 517 #define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */ 518 #define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */ 519 #define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */ 520 521 #define FLAG_CC_IF 0x00000001 /* clock counter overflow */ 522 #define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */ 523 #define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */ 524 #define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */ 525 #define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */ 526 527 #define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */ 528 #define PMNC_EVCNT0_SHIFT 0 529 #define PMNC_EVCNT1_SHIFT 8 530 #define PMNC_EVCNT2_SHIFT 16 531 #define PMNC_EVCNT3_SHIFT 24 532 533 #endif /* _IXP425REG_H_ */ 534
Indexes created Sat Oct 25 10:09:55 GMT 2025