ixp425reg.h revision 1.13
1 /* $NetBSD: ixp425reg.h,v 1.13 2003/10/23 09:29:36 scw Exp $ */ 2 /* 3 * Copyright (c) 2003 4 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #ifndef _IXP425REG_H_ 36 #define _IXP425REG_H_ 37 38 /* 39 * Physical memory map for the Intel IXP425 40 */ 41 /* 42 * CC00 00FF --------------------------- 43 * SDRAM Configuration Registers 44 * CC00 0000 --------------------------- 45 * 46 * C800 BFFF --------------------------- 47 * System and Peripheral Registers 48 * C800 0000 --------------------------- 49 * Expansion Bus Configuration Registers 50 * C400 0000 --------------------------- 51 * PCI Configuration and Status Registers 52 * C000 0000 --------------------------- 53 * 54 * 6400 0000 --------------------------- 55 * Queue manager 56 * 6000 0000 --------------------------- 57 * Expansion Bus Data 58 * 5000 0000 --------------------------- 59 * PCI Data 60 * 4800 0000 --------------------------- 61 * 62 * 4000 0000 --------------------------- 63 * SDRAM 64 * 1000 0000 --------------------------- 65 */ 66 67 /* 68 * Virtual memory map for the Intel IXP425 integrated devices 69 */ 70 /* 71 * FFFF FFFF --------------------------- 72 * 73 * F001 2000 --------------------------- 74 * PCI Configuration and Status Registers 75 * F001 1000 --------------------------- 76 * Expansion bus Configuration Registers 77 * F001 0000 --------------------------- 78 * System and Peripheral Registers 79 * VA F000 0000 = PA C800 0000 (SIZE 0x10000) 80 * F000 0000 --------------------------- 81 * 82 * 0000 0000 --------------------------- 83 * 84 */ 85 86 /* Physical/Virtual address for I/O space */ 87 88 #define IXP425_IO_VBASE 0xf0000000UL 89 #define IXP425_IO_HWBASE 0xc8000000UL 90 #define IXP425_IO_SIZE 0x00010000UL 91 92 /* Offset */ 93 94 #define IXP425_UART0_OFFSET 0x00000000UL 95 #define IXP425_UART1_OFFSET 0x00001000UL 96 #define IXP425_PMC_OFFSET 0x00002000UL 97 #define IXP425_INTR_OFFSET 0x00003000UL 98 #define IXP425_GPIO_OFFSET 0x00004000UL 99 #define IXP425_TIMER_OFFSET 0x00005000UL 100 #define IXP425_HSS_OFFSET 0x00006000UL /* Not User Programmable */ 101 #define IXP425_NPE_A_OFFSET 0x00007000UL /* Not User Programmable */ 102 #define IXP425_NPE_B_OFFSET 0x00008000UL /* Not User Programmable */ 103 #define IXP425_MAC_A_OFFSET 0x00009000UL 104 #define IXP425_MAC_B_OFFSET 0x0000a000UL 105 #define IXP425_USB_OFFSET 0x0000b000UL 106 107 #define IXP425_REG_SIZE 0x1000 108 109 /* 110 * UART 111 * UART0 0xc8000000 112 * UART1 0xc8001000 113 * 114 */ 115 /* I/O space */ 116 #define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET) 117 #define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET) 118 119 #define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET) 120 /* 0xf0000000 */ 121 #define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET) 122 /* 0xf0001000 */ 123 124 #define IXP425_UART_FREQ 14745600 125 126 /*#define IXP4XX_COM_NPORTS 8*/ 127 128 /* 129 * Timers 130 * 131 */ 132 #define IXP425_TIMER_HWBASE (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET) 133 134 #define IXP425_OST_TIM0 0x0004 135 #define IXP425_OST_TIM1 0x000C 136 137 #define IXP425_OST_TIM0_RELOAD 0x0008 138 #define IXP425_OST_TIM1_RELOAD 0x0010 139 #define TIMERRELOAD_MASK 0xFFFFFFFC 140 #define OST_ONESHOT_EN (1U << 1) 141 #define OST_TIMER_EN (1U << 0) 142 143 #define IXP425_OST_STATUS 0x0020 144 #define OST_WARM_RESET (1U << 4) 145 #define OST_WDOG_INT (1U << 3) 146 #define OST_TS_INT (1U << 2) 147 #define OST_TIM1_INT (1U << 1) 148 #define OST_TIM0_INT (1U << 0) 149 150 #define IXP425_OST_WDOG 0x0014 151 #define IXP425_OST_WDOG_ENAB 0x0018 152 #define IXP425_OST_WDOG_KEY 0x001c 153 #define OST_WDOG_KEY_MAJICK 0x482e 154 #define OST_WDOG_ENAB_RST_ENA (1u << 0) 155 #define OST_WDOG_ENAB_INT_ENA (1u << 1) 156 #define OST_WDOG_ENAB_CNT_ENA (1u << 2) 157 158 /* 159 * Interrupt Controller Unit. 160 * PA 0xc8003000 161 */ 162 163 #define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET 164 #define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET 165 /* 0xf0003000 */ 166 #define IXP425_IRQ_SIZE 0x00000020UL 167 168 #define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00) 169 #define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04) 170 #define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08) 171 #define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C) 172 #define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10) 173 #define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14) 174 #define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18) 175 #define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C) 176 177 #define IXP425_INT_SW1 31 /* SW Interrupt 1 */ 178 #define IXP425_INT_SW0 30 /* SW Interrupt 0 */ 179 #define IXP425_INT_GPIO_12 29 /* GPIO 12 */ 180 #define IXP425_INT_GPIO_11 28 /* GPIO 11 */ 181 #define IXP425_INT_GPIO_10 27 /* GPIO 11 */ 182 #define IXP425_INT_GPIO_9 26 /* GPIO 9 */ 183 #define IXP425_INT_GPIO_8 25 /* GPIO 8 */ 184 #define IXP425_INT_GPIO_7 24 /* GPIO 7 */ 185 #define IXP425_INT_GPIO_6 23 /* GPIO 6 */ 186 #define IXP425_INT_GPIO_5 22 /* GPIO 5 */ 187 #define IXP425_INT_GPIO_4 21 /* GPIO 4 */ 188 #define IXP425_INT_GPIO_3 20 /* GPIO 3 */ 189 #define IXP425_INT_GPIO_2 19 /* GPIO 2 */ 190 #define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */ 191 #define IXP425_INT_AHB_PMU 17 /* AHB PMU */ 192 #define IXP425_INT_WDOG 16 /* Watchdog Timer */ 193 #define IXP425_INT_UART0 15 /* HighSpeed UART */ 194 #define IXP425_INT_STAMP 14 /* Timestamp Timer */ 195 #define IXP425_INT_UART1 13 /* Console UART */ 196 #define IXP425_INT_USB 12 /* USB */ 197 #define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */ 198 #define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */ 199 #define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */ 200 #define IXP425_INT_PCIINT 8 /* PCI Interrupt */ 201 #define IXP425_INT_GPIO_1 7 /* GPIO 1 */ 202 #define IXP425_INT_GPIO_0 6 /* GPIO 0 */ 203 #define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */ 204 #define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */ 205 #define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */ 206 #define IXP425_INT_NPE_B 2 /* Ethernet NPE B */ 207 #define IXP425_INT_NPE_A 1 /* Ethernet NPE A */ 208 #define IXP425_INT_HSS 0 /* WAN/HSS NPE */ 209 210 /* 211 * software interrupt 212 */ 213 #define IXP425_INT_bit31 31 214 #define IXP425_INT_bit30 30 215 #define IXP425_INT_bit29 29 216 #define IXP425_INT_bit22 22 217 218 #define IXP425_INT_HWMASK (0xffffffff & \ 219 ~((1 << IXP425_INT_bit31) | \ 220 (1 << IXP425_INT_bit30) | \ 221 (1 << IXP425_INT_bit29) | \ 222 (1 << IXP425_INT_bit22))) 223 #define IXP425_INT_GPIOMASK (0x3ff800c0u) 224 225 /* 226 * GPIO 227 */ 228 #define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET 229 #define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET 230 /* 0xf0004000 */ 231 #define IXP425_GPIO_SIZE 0x00000020UL 232 233 #define IXP425_GPIO_GPOUTR 0x00 234 #define IXP425_GPIO_GPOER 0x04 235 #define IXP425_GPIO_GPINR 0x08 236 #define IXP425_GPIO_GPISR 0x0c 237 #define IXP425_GPIO_GPIT1R 0x10 238 #define IXP425_GPIO_GPIT2R 0x14 239 #define IXP425_GPIO_GPCLKR 0x18 240 # define GPCLKR_MUX14 (1U << 8) 241 # define GPCLKR_CLK0TC_SHIFT 4 242 # define GPCLKR_CLK0DC_SHIFT 0 243 244 /* GPIO Output */ 245 #define GPOUT_ON 0x1 246 #define GPOUT_OFF 0x0 247 248 /* GPIO direction */ 249 #define GPOER_INPUT 0x1 250 #define GPOER_OUTPUT 0x0 251 252 /* GPIO Type bits */ 253 #define GPIO_TYPE_ACT_HIGH 0x0 254 #define GPIO_TYPE_ACT_LOW 0x1 255 #define GPIO_TYPE_EDG_RISING 0x2 256 #define GPIO_TYPE_EDG_FALLING 0x3 257 #define GPIO_TYPE_TRANSITIONAL 0x4 258 #define GPIO_TYPE_MASK 0x7 259 #define GPIO_TYPE(b,v) ((v) << (((b) & 0x7) * 3)) 260 #define GPIO_TYPE_REG(b) (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R) 261 262 /* 263 * Expansion Bus 264 */ 265 #define IXP425_EXP_HWBASE 0xc4000000UL 266 #define IXP425_EXP_VBASE (IXP425_IO_VBASE + IXP425_IO_SIZE) 267 /* 0xf0010000 */ 268 #define IXP425_EXP_SIZE IXP425_REG_SIZE /* 0x1000 */ 269 270 /* offset */ 271 #define EXP_TIMING_CS0_OFFSET 0x0000 272 #define EXP_TIMING_CS1_OFFSET 0x0004 273 #define EXP_TIMING_CS2_OFFSET 0x0008 274 #define EXP_TIMING_CS3_OFFSET 0x000c 275 #define EXP_TIMING_CS4_OFFSET 0x0010 276 #define EXP_TIMING_CS5_OFFSET 0x0014 277 #define EXP_TIMING_CS6_OFFSET 0x0018 278 #define EXP_TIMING_CS7_OFFSET 0x001c 279 #define EXP_CNFG0_OFFSET 0x0020 280 #define EXP_CNFG1_OFFSET 0x0024 281 282 #define IXP425_EXP_RECOVERY_SHIFT 16 283 #define IXP425_EXP_HOLD_SHIFT 20 284 #define IXP425_EXP_STROBE_SHIFT 22 285 #define IXP425_EXP_SETUP_SHIFT 26 286 #define IXP425_EXP_ADDR_SHIFT 28 287 #define IXP425_EXP_CS_EN (1U << 31) 288 289 #define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT) 290 #define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT) 291 #define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT) 292 #define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) 293 #define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT) 294 295 // EXP_CSn bits 296 #define EXP_BYTE_EN (1 << 0) 297 #define EXP_WR_EN (1 << 1) 298 #define EXP_SPLT_EN (1 << 3) 299 #define EXP_MUX_EN (1 << 4) 300 #define EXP_HRDY_POL (1 << 5) 301 #define EXP_BYTE_RD16 (1 << 6) 302 #define EXP_SZ_512 (0 << 10) 303 #define EXP_SZ_1K (1 << 10) 304 #define EXP_SZ_2K (2 << 10) 305 #define EXP_SZ_4K (3 << 10) 306 #define EXP_SZ_8K (4 << 10) 307 #define EXP_SZ_16K (5 << 10) 308 #define EXP_SZ_32K (6 << 10) 309 #define EXP_SZ_64K (7 << 10) 310 #define EXP_SZ_128K (8 << 10) 311 #define EXP_SZ_256K (9 << 10) 312 #define EXP_SZ_512K (10 << 10) 313 #define EXP_SZ_1M (11 << 10) 314 #define EXP_SZ_2M (12 << 10) 315 #define EXP_SZ_4M (13 << 10) 316 #define EXP_SZ_8M (14 << 10) 317 #define EXP_SZ_16M (15 << 10) 318 #define EXP_CYC_INTEL (0 << 14) 319 #define EXP_CYC_MOTO (1 << 14) 320 #define EXP_CYC_HPI (2 << 14) 321 322 // EXP_CNFG0 bits 323 #define EXP_CNFG0_8BIT (1 << 0) 324 #define EXP_CNFG0_PCI_HOST (1 << 1) 325 #define EXP_CNFG0_PCI_ARB (1 << 2) 326 #define EXP_CNFG0_PCI_66MHZ (1 << 4) 327 #define EXP_CNFG0_MEM_MAP (1 << 31) 328 329 // EXP_CNFG1 bits 330 #define EXP_CNFG1_SW_INT0 (1 << 0) 331 #define EXP_CNFG1_SW_INT1 (1 << 1) 332 333 /* 334 * PCI 335 */ 336 #define IXP425_PCI_HWBASE 0xc0000000 337 #define IXP425_PCI_VBASE (IXP425_EXP_VBASE + IXP425_EXP_SIZE) 338 /* 0xf0011000 */ 339 #define IXP425_PCI_SIZE IXP425_REG_SIZE /* 0x1000 */ 340 341 /* 342 * Mapping registers of IXP425 PCI Configuration 343 */ 344 /* PCI_ID_REG 0x00 */ 345 /* PCI_COMMAND_STATUS_REG 0x04 */ 346 /* PCI_CLASS_REG 0x08 */ 347 /* PCI_BHLC_REG 0x0c */ 348 #define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */ 349 #define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */ 350 #define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */ 351 #define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */ 352 #define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */ 353 #define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */ 354 /* PCI_SUBSYS_ID_REG 0x2c */ 355 /* PCI_INTERRUPT_REG 0x3c */ 356 #define PCI_RTOTTO 0x40 357 358 /* PCI Controller CSR Base Address */ 359 #define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE 360 361 /* PCI Memory Space */ 362 #define IXP425_PCI_MEM_HWBASE 0x48000000UL /* VA == PA */ 363 #define IXP425_PCI_MEM_VBASE IXP425_PCI_MEM_HWBASE 364 #define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */ 365 366 /* PCI I/O Space */ 367 #define IXP425_PCI_IO_HWBASE 0x00000000UL 368 #define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */ 369 370 /* PCI Controller Configuration Offset */ 371 #define PCI_NP_AD 0x00 372 #define PCI_NP_CBE 0x04 373 # define NP_CBE_SHIFT 4 374 #define PCI_NP_WDATA 0x08 375 #define PCI_NP_RDATA 0x0c 376 #define PCI_CRP_AD_CBE 0x10 377 #define PCI_CRP_AD_WDATA 0x14 378 #define PCI_CRP_AD_RDATA 0x18 379 #define PCI_CSR 0x1c 380 # define CSR_PRST (1U << 16) 381 # define CSR_IC (1U << 15) 382 # define CSR_ABE (1U << 4) 383 # define CSR_PDS (1U << 3) 384 # define CSR_ADS (1U << 2) 385 # define CSR_HOST (1U << 0) 386 #define PCI_ISR 0x20 387 # define ISR_AHBE (1U << 3) 388 # define ISR_PPE (1U << 2) 389 # define ISR_PFE (1U << 1) 390 # define ISR_PSE (1U << 0) 391 #define PCI_INTEN 0x24 392 #define PCI_DMACTRL 0x28 393 #define PCI_AHBMEMBASE 0x2c 394 #define PCI_AHBIOBASE 0x30 395 #define PCI_PCIMEMBASE 0x34 396 #define PCI_AHBDOORBELL 0x38 397 #define PCI_PCIDOORBELL 0x3c 398 #define PCI_ATPDMA0_AHBADDR 0x40 399 #define PCI_ATPDMA0_PCIADDR 0x44 400 #define PCI_ATPDMA0_LENGTH 0x48 401 #define PCI_ATPDMA1_AHBADDR 0x4c 402 #define PCI_ATPDMA1_PCIADDR 0x50 403 #define PCI_ATPDMA1_LENGTH 0x54 404 #define PCI_PTADMA0_AHBADDR 0x58 405 #define PCI_PTADMA0_PCIADDR 0x5c 406 #define PCI_PTADMA0_LENGTH 0x60 407 #define PCI_PTADMA1_AHBADDR 0x64 408 #define PCI_PTADMA1_PCIADDR 0x68 409 #define PCI_PTADMA1_LENGTH 0x6c 410 411 /* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */ 412 #define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/ 413 #define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/ 414 #define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */ 415 #define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */ 416 #define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */ 417 #define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */ 418 #define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */ 419 #define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */ 420 421 /* PCI byte enables */ 422 #define BE_8BIT(a) ((0x10u << ((a) & 0x03)) ^ 0xf0) 423 #define BE_16BIT(a) ((0x30u << ((a) & 0x02)) ^ 0xf0) 424 #define BE_32BIT(a) 0x00 425 426 /* PCI byte selects */ 427 #define READ_8BIT(v,a) ((u_int8_t)((v) >> (((a) & 3) * 8))) 428 #define READ_16BIT(v,a) ((u_int16_t)((v) >> (((a) & 2) * 8))) 429 #define WRITE_8BIT(v,a) (((u_int32_t)(v)) << (((a) & 3) * 8)) 430 #define WRITE_16BIT(v,a) (((u_int32_t)(v)) << (((a) & 2) * 8)) 431 432 /* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */ 433 #define COMMAND_CRP_READ 0x00 434 #define COMMAND_CRP_WRITE (1U << 16) 435 436 /* 437 * SDRAM Configuration Register 438 */ 439 #define IXP425_MCU_HWBASE 0xcc000000UL 440 #define MCU_SDR_CONFIG 0x00 441 #define MCU_SDR_REFRESH 0x04 442 #define MCU_SDR_IR 0x08 443 444 /* 445 * Performance Monitoring Unit (CP14) 446 * 447 * CP14.0.1 Performance Monitor Control Register(PMNC) 448 * CP14.1.1 Clock Counter(CCNT) 449 * CP14.4.1 Interrupt Enable Register(INTEN) 450 * CP14.5.1 Overflow Flag Register(FLAG) 451 * CP14.8.1 Event Selection Register(EVTSEL) 452 * CP14.0.2 Performance Counter Register 0(PMN0) 453 * CP14.1.2 Performance Counter Register 0(PMN1) 454 * CP14.2.2 Performance Counter Register 0(PMN2) 455 * CP14.3.2 Performance Counter Register 0(PMN3) 456 */ 457 458 #define PMNC_E 0x00000001 /* enable all counters */ 459 #define PMNC_P 0x00000002 /* reset all PMNs to 0 */ 460 #define PMNC_C 0x00000004 /* clock counter reset */ 461 #define PMNC_D 0x00000008 /* clock counter / 64 */ 462 463 #define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */ 464 #define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */ 465 #define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */ 466 #define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */ 467 #define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */ 468 469 #define FLAG_CC_IF 0x00000001 /* clock counter overflow */ 470 #define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */ 471 #define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */ 472 #define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */ 473 #define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */ 474 475 #define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */ 476 #define PMNC_EVCNT0_SHIFT 0 477 #define PMNC_EVCNT1_SHIFT 8 478 #define PMNC_EVCNT2_SHIFT 16 479 #define PMNC_EVCNT3_SHIFT 24 480 481 #endif /* _IXP425REG_H_ */ 482
Indexes created Sat Oct 25 07:10:08 GMT 2025