ixp425reg.h revision 1.19.22.1
1 /* $NetBSD: ixp425reg.h,v 1.19.22.1 2006/12/18 11:42:04 yamt Exp $ */ 2 /* 3 * Copyright (c) 2003 4 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #ifndef _IXP425REG_H_ 36 #define _IXP425REG_H_ 37 38 /* 39 * Physical memory map for the Intel IXP425 40 */ 41 /* 42 * CC00 00FF --------------------------- 43 * SDRAM Configuration Registers 44 * CC00 0000 --------------------------- 45 * 46 * C800 BFFF --------------------------- 47 * System and Peripheral Registers 48 * C800 0000 --------------------------- 49 * Expansion Bus Configuration Registers 50 * C400 0000 --------------------------- 51 * PCI Configuration and Status Registers 52 * C000 0000 --------------------------- 53 * 54 * 6400 0000 --------------------------- 55 * Queue manager 56 * 6000 0000 --------------------------- 57 * Expansion Bus Data 58 * 5000 0000 --------------------------- 59 * PCI Data 60 * 4800 0000 --------------------------- 61 * 62 * 4000 0000 --------------------------- 63 * SDRAM 64 * 1000 0000 --------------------------- 65 */ 66 67 /* 68 * Virtual memory map for the Intel IXP425 integrated devices 69 */ 70 /* 71 * FFFF FFFF --------------------------- 72 * 73 * FC00 0000 --------------------------- 74 * PCI Data (memory space) 75 * F800 0000 --------------------------- 76 * 77 * F020 1000 --------------------------- 78 * SDRAM Controller 79 * F020 0000 --------------------------- 80 * 81 * F001 2000 --------------------------- 82 * PCI Configuration and Status Registers 83 * F001 1000 --------------------------- 84 * Expansion bus Configuration Registers 85 * F001 0000 --------------------------- 86 * System and Peripheral Registers 87 * VA F000 0000 = PA C800 0000 (SIZE 0x10000) 88 * F000 0000 --------------------------- 89 * 90 * 0000 0000 --------------------------- 91 * 92 */ 93 94 /* Physical/Virtual address for I/O space */ 95 96 #define IXP425_IO_VBASE 0xf0000000UL 97 #define IXP425_IO_HWBASE 0xc8000000UL 98 #define IXP425_IO_SIZE 0x00010000UL 99 100 /* Offset */ 101 102 #define IXP425_UART0_OFFSET 0x00000000UL 103 #define IXP425_UART1_OFFSET 0x00001000UL 104 #define IXP425_PMC_OFFSET 0x00002000UL 105 #define IXP425_INTR_OFFSET 0x00003000UL 106 #define IXP425_GPIO_OFFSET 0x00004000UL 107 #define IXP425_TIMER_OFFSET 0x00005000UL 108 #define IXP425_NPE_A_OFFSET 0x00006000UL /* Not User Programmable */ 109 #define IXP425_NPE_B_OFFSET 0x00007000UL /* Not User Programmable */ 110 #define IXP425_NPE_C_OFFSET 0x00008000UL /* Not User Programmable */ 111 #define IXP425_MAC_A_OFFSET 0x00009000UL 112 #define IXP425_MAC_B_OFFSET 0x0000a000UL 113 #define IXP425_USB_OFFSET 0x0000b000UL 114 115 #define IXP425_REG_SIZE 0x1000 116 117 /* 118 * UART 119 * UART0 0xc8000000 120 * UART1 0xc8001000 121 * 122 */ 123 /* I/O space */ 124 #define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET) 125 #define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET) 126 127 #define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET) 128 /* 0xf0000000 */ 129 #define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET) 130 /* 0xf0001000 */ 131 132 #define IXP425_UART_FREQ 14745600 133 134 /*#define IXP4XX_COM_NPORTS 8*/ 135 136 /* 137 * Timers 138 * 139 */ 140 #define IXP425_TIMER_HWBASE (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET) 141 #define IXP425_TIMER_VBASE (IXP425_IO_VBASE + IXP425_TIMER_OFFSET) 142 143 #define IXP425_OST_TS 0x0000 144 #define IXP425_OST_TIM0 0x0004 145 #define IXP425_OST_TIM1 0x000C 146 147 #define IXP425_OST_TIM0_RELOAD 0x0008 148 #define IXP425_OST_TIM1_RELOAD 0x0010 149 #define TIMERRELOAD_MASK 0xFFFFFFFC 150 #define OST_ONESHOT_EN (1U << 1) 151 #define OST_TIMER_EN (1U << 0) 152 153 #define IXP425_OST_STATUS 0x0020 154 #define OST_WARM_RESET (1U << 4) 155 #define OST_WDOG_INT (1U << 3) 156 #define OST_TS_INT (1U << 2) 157 #define OST_TIM1_INT (1U << 1) 158 #define OST_TIM0_INT (1U << 0) 159 160 #define IXP425_OST_WDOG_HWBASE (IXP425_TIMER_HWBASE + 0x14) 161 #define IXP425_OST_WDOG_VBASE (IXP425_TIMER_VBASE + 0x14) 162 #define IXP425_OST_WDOG_SIZE 0x0c 163 #define IXP425_OST_WDOG 0x0000 164 #define IXP425_OST_WDOG_ENAB 0x0004 165 #define IXP425_OST_WDOG_KEY 0x0008 166 #define OST_WDOG_KEY_MAJICK 0x482e 167 #define OST_WDOG_ENAB_RST_ENA (1u << 0) 168 #define OST_WDOG_ENAB_INT_ENA (1u << 1) 169 #define OST_WDOG_ENAB_CNT_ENA (1u << 2) 170 171 /* 172 * Interrupt Controller Unit. 173 * PA 0xc8003000 174 */ 175 176 #define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET 177 #define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET 178 /* 0xf0003000 */ 179 #define IXP425_IRQ_SIZE 0x00000020UL 180 181 #define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00) 182 #define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04) 183 #define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08) 184 #define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C) 185 #define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10) 186 #define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14) 187 #define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18) 188 #define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C) 189 190 #define IXP425_INT_SW1 31 /* SW Interrupt 1 */ 191 #define IXP425_INT_SW0 30 /* SW Interrupt 0 */ 192 #define IXP425_INT_GPIO_12 29 /* GPIO 12 */ 193 #define IXP425_INT_GPIO_11 28 /* GPIO 11 */ 194 #define IXP425_INT_GPIO_10 27 /* GPIO 11 */ 195 #define IXP425_INT_GPIO_9 26 /* GPIO 9 */ 196 #define IXP425_INT_GPIO_8 25 /* GPIO 8 */ 197 #define IXP425_INT_GPIO_7 24 /* GPIO 7 */ 198 #define IXP425_INT_GPIO_6 23 /* GPIO 6 */ 199 #define IXP425_INT_GPIO_5 22 /* GPIO 5 */ 200 #define IXP425_INT_GPIO_4 21 /* GPIO 4 */ 201 #define IXP425_INT_GPIO_3 20 /* GPIO 3 */ 202 #define IXP425_INT_GPIO_2 19 /* GPIO 2 */ 203 #define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */ 204 #define IXP425_INT_AHB_PMU 17 /* AHB PMU */ 205 #define IXP425_INT_WDOG 16 /* Watchdog Timer */ 206 #define IXP425_INT_UART0 15 /* HighSpeed UART */ 207 #define IXP425_INT_STAMP 14 /* Timestamp Timer */ 208 #define IXP425_INT_UART1 13 /* Console UART */ 209 #define IXP425_INT_USB 12 /* USB */ 210 #define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */ 211 #define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */ 212 #define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */ 213 #define IXP425_INT_PCIINT 8 /* PCI Interrupt */ 214 #define IXP425_INT_GPIO_1 7 /* GPIO 1 */ 215 #define IXP425_INT_GPIO_0 6 /* GPIO 0 */ 216 #define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */ 217 #define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */ 218 #define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */ 219 #define IXP425_INT_NPE_C 2 /* Ethernet NPE C */ 220 #define IXP425_INT_NPE_B 1 /* Ethernet NPE B */ 221 #define IXP425_INT_NPE_A 0 /* NPE A */ 222 223 /* 224 * software interrupt 225 */ 226 #define IXP425_INT_bit31 31 227 #define IXP425_INT_bit30 30 228 #define IXP425_INT_bit14 14 229 #define IXP425_INT_bit11 11 230 231 #define IXP425_INT_HWMASK (0xffffffff & \ 232 ~((1 << IXP425_INT_bit31) | \ 233 (1 << IXP425_INT_bit30) | \ 234 (1 << IXP425_INT_bit14) | \ 235 (1 << IXP425_INT_bit11))) 236 #define IXP425_INT_GPIOMASK (0x3ff800c0u) 237 238 /* 239 * GPIO 240 */ 241 #define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET 242 #define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET 243 /* 0xf0004000 */ 244 #define IXP425_GPIO_SIZE 0x00000020UL 245 246 #define IXP425_GPIO_GPOUTR 0x00 247 #define IXP425_GPIO_GPOER 0x04 248 #define IXP425_GPIO_GPINR 0x08 249 #define IXP425_GPIO_GPISR 0x0c 250 #define IXP425_GPIO_GPIT1R 0x10 251 #define IXP425_GPIO_GPIT2R 0x14 252 #define IXP425_GPIO_GPCLKR 0x18 253 # define GPCLKR_MUX14 (1U << 8) 254 # define GPCLKR_CLK0TC_SHIFT 4 255 # define GPCLKR_CLK0DC_SHIFT 0 256 257 /* GPIO Output */ 258 #define GPOUT_ON 0x1 259 #define GPOUT_OFF 0x0 260 261 /* GPIO direction */ 262 #define GPOER_INPUT 0x1 263 #define GPOER_OUTPUT 0x0 264 265 /* GPIO Type bits */ 266 #define GPIO_TYPE_ACT_HIGH 0x0 267 #define GPIO_TYPE_ACT_LOW 0x1 268 #define GPIO_TYPE_EDG_RISING 0x2 269 #define GPIO_TYPE_EDG_FALLING 0x3 270 #define GPIO_TYPE_TRANSITIONAL 0x4 271 #define GPIO_TYPE_MASK 0x7 272 #define GPIO_TYPE(b,v) ((v) << (((b) & 0x7) * 3)) 273 #define GPIO_TYPE_REG(b) (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R) 274 275 /* 276 * Expansion Bus 277 */ 278 #define IXP425_EXP_HWBASE 0xc4000000UL 279 #define IXP425_EXP_VBASE (IXP425_IO_VBASE + IXP425_IO_SIZE) 280 /* 0xf0010000 */ 281 #define IXP425_EXP_SIZE IXP425_REG_SIZE /* 0x1000 */ 282 283 /* offset */ 284 #define EXP_TIMING_CS0_OFFSET 0x0000 285 #define EXP_TIMING_CS1_OFFSET 0x0004 286 #define EXP_TIMING_CS2_OFFSET 0x0008 287 #define EXP_TIMING_CS3_OFFSET 0x000c 288 #define EXP_TIMING_CS4_OFFSET 0x0010 289 #define EXP_TIMING_CS5_OFFSET 0x0014 290 #define EXP_TIMING_CS6_OFFSET 0x0018 291 #define EXP_TIMING_CS7_OFFSET 0x001c 292 #define EXP_CNFG0_OFFSET 0x0020 293 #define EXP_CNFG1_OFFSET 0x0024 294 #define EXP_FCTRL_OFFSET 0x0028 295 296 #define IXP425_EXP_RECOVERY_SHIFT 16 297 #define IXP425_EXP_HOLD_SHIFT 20 298 #define IXP425_EXP_STROBE_SHIFT 22 299 #define IXP425_EXP_SETUP_SHIFT 26 300 #define IXP425_EXP_ADDR_SHIFT 28 301 #define IXP425_EXP_CS_EN (1U << 31) 302 303 #define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT) 304 #define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT) 305 #define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT) 306 #define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) 307 #define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT) 308 309 // EXP_CSn bits 310 #define EXP_BYTE_EN (1 << 0) 311 #define EXP_WR_EN (1 << 1) 312 #define EXP_SPLT_EN (1 << 3) 313 #define EXP_MUX_EN (1 << 4) 314 #define EXP_HRDY_POL (1 << 5) 315 #define EXP_BYTE_RD16 (1 << 6) 316 #define EXP_SZ_512 (0 << 10) 317 #define EXP_SZ_1K (1 << 10) 318 #define EXP_SZ_2K (2 << 10) 319 #define EXP_SZ_4K (3 << 10) 320 #define EXP_SZ_8K (4 << 10) 321 #define EXP_SZ_16K (5 << 10) 322 #define EXP_SZ_32K (6 << 10) 323 #define EXP_SZ_64K (7 << 10) 324 #define EXP_SZ_128K (8 << 10) 325 #define EXP_SZ_256K (9 << 10) 326 #define EXP_SZ_512K (10 << 10) 327 #define EXP_SZ_1M (11 << 10) 328 #define EXP_SZ_2M (12 << 10) 329 #define EXP_SZ_4M (13 << 10) 330 #define EXP_SZ_8M (14 << 10) 331 #define EXP_SZ_16M (15 << 10) 332 #define EXP_CYC_INTEL (0 << 14) 333 #define EXP_CYC_MOTO (1 << 14) 334 #define EXP_CYC_HPI (2 << 14) 335 336 // EXP_CNFG0 bits 337 #define EXP_CNFG0_8BIT (1 << 0) 338 #define EXP_CNFG0_PCI_HOST (1 << 1) 339 #define EXP_CNFG0_PCI_ARB (1 << 2) 340 #define EXP_CNFG0_PCI_66MHZ (1 << 4) 341 #define EXP_CNFG0_MEM_MAP (1 << 31) 342 343 // EXP_CNFG1 bits 344 #define EXP_CNFG1_SW_INT0 (1 << 0) 345 #define EXP_CNFG1_SW_INT1 (1 << 1) 346 347 /* 348 * PCI 349 */ 350 #define IXP425_PCI_HWBASE 0xc0000000 351 #define IXP425_PCI_VBASE (IXP425_EXP_VBASE + IXP425_EXP_SIZE) 352 /* 0xf0011000 */ 353 #define IXP425_PCI_SIZE IXP425_REG_SIZE /* 0x1000 */ 354 355 /* 356 * Mapping registers of IXP425 PCI Configuration 357 */ 358 /* PCI_ID_REG 0x00 */ 359 /* PCI_COMMAND_STATUS_REG 0x04 */ 360 /* PCI_CLASS_REG 0x08 */ 361 /* PCI_BHLC_REG 0x0c */ 362 #define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */ 363 #define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */ 364 #define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */ 365 #define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */ 366 #define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */ 367 #define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */ 368 /* PCI_SUBSYS_ID_REG 0x2c */ 369 /* PCI_INTERRUPT_REG 0x3c */ 370 #define PCI_RTOTTO 0x40 371 372 /* PCI Controller CSR Base Address */ 373 #define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE 374 375 /* PCI Memory Space */ 376 #define IXP425_PCI_MEM_HWBASE 0x48000000UL 377 #define IXP425_PCI_MEM_VBASE 0xf8000000UL 378 #define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */ 379 380 /* PCI I/O Space */ 381 #define IXP425_PCI_IO_HWBASE 0x00000000UL 382 #define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */ 383 384 /* PCI Controller Configuration Offset */ 385 #define PCI_NP_AD 0x00 386 #define PCI_NP_CBE 0x04 387 # define NP_CBE_SHIFT 4 388 #define PCI_NP_WDATA 0x08 389 #define PCI_NP_RDATA 0x0c 390 #define PCI_CRP_AD_CBE 0x10 391 #define PCI_CRP_AD_WDATA 0x14 392 #define PCI_CRP_AD_RDATA 0x18 393 #define PCI_CSR 0x1c 394 # define CSR_PRST (1U << 16) 395 # define CSR_IC (1U << 15) 396 # define CSR_ABE (1U << 4) 397 # define CSR_PDS (1U << 3) 398 # define CSR_ADS (1U << 2) 399 # define CSR_HOST (1U << 0) 400 #define PCI_ISR 0x20 401 # define ISR_AHBE (1U << 3) 402 # define ISR_PPE (1U << 2) 403 # define ISR_PFE (1U << 1) 404 # define ISR_PSE (1U << 0) 405 #define PCI_INTEN 0x24 406 #define PCI_DMACTRL 0x28 407 #define PCI_AHBMEMBASE 0x2c 408 #define PCI_AHBIOBASE 0x30 409 #define PCI_PCIMEMBASE 0x34 410 #define PCI_AHBDOORBELL 0x38 411 #define PCI_PCIDOORBELL 0x3c 412 #define PCI_ATPDMA0_AHBADDR 0x40 413 #define PCI_ATPDMA0_PCIADDR 0x44 414 #define PCI_ATPDMA0_LENGTH 0x48 415 #define PCI_ATPDMA1_AHBADDR 0x4c 416 #define PCI_ATPDMA1_PCIADDR 0x50 417 #define PCI_ATPDMA1_LENGTH 0x54 418 #define PCI_PTADMA0_AHBADDR 0x58 419 #define PCI_PTADMA0_PCIADDR 0x5c 420 #define PCI_PTADMA0_LENGTH 0x60 421 #define PCI_PTADMA1_AHBADDR 0x64 422 #define PCI_PTADMA1_PCIADDR 0x68 423 #define PCI_PTADMA1_LENGTH 0x6c 424 425 /* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */ 426 #define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/ 427 #define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/ 428 #define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */ 429 #define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */ 430 #define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */ 431 #define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */ 432 #define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */ 433 #define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */ 434 435 /* PCI byte enables */ 436 #define BE_8BIT(a) ((0x10u << ((a) & 0x03)) ^ 0xf0) 437 #define BE_16BIT(a) ((0x30u << ((a) & 0x02)) ^ 0xf0) 438 #define BE_32BIT(a) 0x00 439 440 /* PCI byte selects */ 441 #define READ_8BIT(v,a) ((u_int8_t)((v) >> (((a) & 3) * 8))) 442 #define READ_16BIT(v,a) ((u_int16_t)((v) >> (((a) & 2) * 8))) 443 #define WRITE_8BIT(v,a) (((u_int32_t)(v)) << (((a) & 3) * 8)) 444 #define WRITE_16BIT(v,a) (((u_int32_t)(v)) << (((a) & 2) * 8)) 445 446 /* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */ 447 #define COMMAND_CRP_READ 0x00 448 #define COMMAND_CRP_WRITE (1U << 16) 449 450 /* 451 * SDRAM Configuration Register 452 */ 453 #define IXP425_MCU_HWBASE 0xcc000000UL 454 #define IXP425_MCU_VBASE 0xf0200000UL 455 #define IXP425_MCU_SIZE 0x1000 /* Actually only 256 bytes */ 456 #define MCU_SDR_CONFIG 0x00 457 #define MCU_SDR_CONFIG_MCONF(x) ((x) & 0x7) 458 #define MCU_SDR_CONFIG_64MBIT (1u << 5) 459 #define MCU_SDR_REFRESH 0x04 460 #define MCU_SDR_IR 0x08 461 462 /* 463 * Performance Monitoring Unit (CP14) 464 * 465 * CP14.0.1 Performance Monitor Control Register(PMNC) 466 * CP14.1.1 Clock Counter(CCNT) 467 * CP14.4.1 Interrupt Enable Register(INTEN) 468 * CP14.5.1 Overflow Flag Register(FLAG) 469 * CP14.8.1 Event Selection Register(EVTSEL) 470 * CP14.0.2 Performance Counter Register 0(PMN0) 471 * CP14.1.2 Performance Counter Register 0(PMN1) 472 * CP14.2.2 Performance Counter Register 0(PMN2) 473 * CP14.3.2 Performance Counter Register 0(PMN3) 474 */ 475 476 #define PMNC_E 0x00000001 /* enable all counters */ 477 #define PMNC_P 0x00000002 /* reset all PMNs to 0 */ 478 #define PMNC_C 0x00000004 /* clock counter reset */ 479 #define PMNC_D 0x00000008 /* clock counter / 64 */ 480 481 #define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */ 482 #define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */ 483 #define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */ 484 #define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */ 485 #define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */ 486 487 #define FLAG_CC_IF 0x00000001 /* clock counter overflow */ 488 #define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */ 489 #define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */ 490 #define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */ 491 #define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */ 492 493 #define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */ 494 #define PMNC_EVCNT0_SHIFT 0 495 #define PMNC_EVCNT1_SHIFT 8 496 #define PMNC_EVCNT2_SHIFT 16 497 #define PMNC_EVCNT3_SHIFT 24 498 499 500 /* 501 * Queue Manager 502 */ 503 #define IXP425_QMGR_HWBASE 0x60000000UL 504 #define IXP425_QMGR_VBASE (IXP425_PCI_VBASE + IXP425_PCI_SIZE) 505 #define IXP425_QMGR_SIZE 0x4000 506 507 /* 508 * Network Processing Engines (NPE's) and associated Ethernet MAC's. 509 */ 510 #define IXP425_NPE_A_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_A_OFFSET) 511 #define IXP425_NPE_A_VBASE (IXP425_IO_VBASE + IXP425_NPE_A_OFFSET) 512 #define IXP425_NPE_A_SIZE 0x1000 /* Actually only 256 bytes */ 513 514 #define IXP425_NPE_B_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_B_OFFSET) 515 #define IXP425_NPE_B_VBASE (IXP425_IO_VBASE + IXP425_NPE_B_OFFSET) 516 #define IXP425_NPE_B_SIZE 0x1000 /* Actually only 256 bytes */ 517 518 #define IXP425_NPE_C_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_C_OFFSET) 519 #define IXP425_NPE_C_VBASE (IXP425_IO_VBASE + IXP425_NPE_C_OFFSET) 520 #define IXP425_NPE_C_SIZE 0x1000 /* Actually only 256 bytes */ 521 522 #define IXP425_MAC_A_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_A_OFFSET) 523 #define IXP425_MAC_A_VBASE (IXP425_IO_VBASE + IXP425_MAC_A_OFFSET) 524 #define IXP425_MAC_A_SIZE 0x1000 /* Actually only 256 bytes */ 525 526 #define IXP425_MAC_B_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_B_OFFSET) 527 #define IXP425_MAC_B_VBASE (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET) 528 #define IXP425_MAC_B_SIZE 0x1000 /* Actually only 256 bytes */ 529 530 #endif /* _IXP425REG_H_ */ 531
Indexes created Sat Oct 25 10:09:55 GMT 2025