ixp425reg.h revision 1.2
1 /* $NetBSD: ixp425reg.h,v 1.2 2003/05/24 23:48:44 ichiro Exp $ */ 2 /* 3 * Copyright (c) 2003 4 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #ifndef _IXP425REG_H_ 36 #define _IXP425REG_H_ 37 38 /* 39 * Physical memory map for the Intel IXP425 40 */ 41 /* 42 * CC00 00FF --------------------------- 43 * SDRAM Configuration Registers 44 * CC00 0000 --------------------------- 45 * 46 * C800 BFFF --------------------------- 47 * System and Peripheral Registers 48 * C800 0000 --------------------------- 49 * Expansion Bus Configuration Registers 50 * C400 0000 --------------------------- 51 * PCI Configuration and Status Registers 52 * C000 0000 --------------------------- 53 * 54 * 6400 0000 --------------------------- 55 * Queue manager 56 * 6000 0000 --------------------------- 57 * Expansion Bus Data 58 * 5000 0000 --------------------------- 59 * PCI Data 60 * 4800 0000 --------------------------- 61 * 62 * 4000 0000 --------------------------- 63 * SDRAM 64 * 1000 0000 --------------------------- 65 */ 66 67 /* 68 * Virtual memory map for the Intel IXP425 integrated devices 69 */ 70 /* 71 * FFFF FFFF --------------------------- 72 * 73 * F001 2000 --------------------------- 74 * PCI Configuration and Status Registers 75 * F001 1000 --------------------------- 76 * Expansion bus Configuration Registers 77 * F001 0000 --------------------------- 78 * System and Peripheral Registers 79 * VA F000 0000 = PA C800 0000 (SIZE 0x10000) 80 * F000 0000 --------------------------- 81 * 82 * 0000 0000 --------------------------- 83 * 84 */ 85 86 /* Physical/Virtual address for I/O space */ 87 88 #define IXP425_IO_VBASE 0xf0000000UL 89 #define IXP425_IO_HWBASE 0xc8000000UL 90 #define IXP425_IO_SIZE 0x00010000UL 91 92 /* Offset */ 93 94 #define IXP425_UART0_OFFSET 0x00000000UL 95 #define IXP425_UART1_OFFSET 0x00001000UL 96 #define IXP425_PMC_OFFSET 0x00002000UL 97 #define IXP425_INTR_OFFSET 0x00003000UL 98 #define IXP425_GPIO_OFFSET 0x00004000UL 99 #define IXP425_TIMER_OFFSET 0x00005000UL 100 #define IXP425_HSS_OFFSET 0x00006000UL /* Not User Programmable */ 101 #define IXP425_NPE_A_OFFSET 0x00007000UL /* Not User Programmable */ 102 #define IXP425_NPE_B_OFFSET 0x00008000UL /* Not User Programmable */ 103 #define IXP425_MAC_A_OFFSET 0x00009000UL 104 #define IXP425_MAC_B_OFFSET 0x0000a000UL 105 #define IXP425_USB_OFFSET 0x0000b000UL 106 107 #define IXP425_REG_SIZE 0x1000 108 109 /* 110 * UART 111 * UART0 0xc8000000 112 * UART1 0xc8001000 113 * 114 */ 115 /* I/O space */ 116 #define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET) 117 #define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET) 118 119 #define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET) 120 #define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET) 121 122 /* registers */ 123 /* Buffer and Divisor */ 124 #define IXP425_UART_DATA 0x0000 125 #define IXP425_UART_DLL 0x0000 /* Divisor Latch Low */ 126 #define IXP425_UART_DLH 0x0004 /* Divisor Latch High */ 127 128 /* Interrupt Enable Register */ 129 #define IXP425_UART_IER 0x0004 130 #define IER_DMAE (1U << 7) /* Enable DMA Requests */ 131 #define IER_UUE (1U << 6) /* Enable UART UNIT */ 132 #define IER_NRZE (1U << 5) /* Enable NRZ coding */ 133 #define IER_RTOIE (1U << 4) /* Enable receiver T/O interrupt */ 134 #define IER_RIE (1U << 3) /* Enable modem interrupt */ 135 #define IER_RLSE (1U << 2) /* Enable line status interrupt */ 136 #define IER_TIE (1U << 1) /* Enable transmitter interrupt */ 137 #define IER_RAVIE (1U << 0) /* Enable receiver interrupt */ 138 139 /* Interrupt Identification Register */ 140 #define IXP425_UART_IIR 0x0008 141 #define IIR_NOPEND (1U << 0) /* No pending interrupts */ 142 #define IIR_MLSC (0U << 1) /* Modem status */ 143 #define IIR_TXRDY (1U << 1) /* Transmitter ready */ 144 #define IIR_RXRDY (2U << 1) /* Receiver ready */ 145 #define IIR_RXERR (2U << 1) /* Receiver error */ 146 #define IIR_TOD (1U << 3) /* Time Out interrupt pending */ 147 #define IIR_FIFOS (3U << 6) /* FIFO mode enable */ 148 149 /* FIFO control */ 150 #define IXP425_UART_FCR 0x0008 151 #define FCR_TRIGGER_1 (0U << 6) /* ITL 0 */ 152 #define FCR_TRIGGER_8 (1U << 6) /* ITL 0 */ 153 #define FCR_TRIGGER_16 (2U << 6) /* ITL 0 */ 154 #define FCR_TRIGGER_32 (3U << 6) /* ITL 0 */ 155 #define FCR_RESETTF (1U << 2) /* Reset TX FIFO */ 156 #define FCR_RESETRF (1U << 1) /* Reset RX FIFO */ 157 #define FCR_ENABLE (1U << 0) /* Enable FIFO */ 158 159 /* Line control */ 160 #define IXP425_UART_LCR 0x000c 161 #define LCR_DLAB (1U << 7) /* Divisor latch access enable */ 162 #define LCR_SBREAK (1U << 6) /* Break Control */ 163 #define LCR_PEVEN (1U << 4) /* Even-Parity */ 164 #define LCR_PODD (0U << 4) /* Even-Parity */ 165 #define LCR_PENE (1U << 3) /* Enable parity */ 166 #define LCR_PNONE (0U << 3) /* No parity */ 167 #define LCR_1STOP (0U << 2) /* 1 Stop Bit */ 168 #define LCR_2STOP (1U << 2) /* 2 Stop Bit */ 169 #define LCR_8BITS (3U << 0) /* 8 bits per serial word */ 170 #define LCR_7BITS (2U << 0) /* 7 bits per serial word */ 171 #define LCR_6BITS (1U << 0) /* 6 bits per serial word */ 172 #define LCR_5BITS (0U << 0) /* 5 bits per serial word */ 173 174 /* Modem control */ 175 #define IXP425_UART_MCR 0x0010 176 #define MCR_LOOPBACK (1U << 4) /* Loop test */ 177 #define MCR_IENABLE (1U << 3) /* Out2: enables UART interrupts */ 178 #define MCR_DRS (1U << 2) /* Out1: resets some internal modems */ 179 #define MCR_RTS (1U << 1) /* Request To Send */ 180 #define MCR_DTR (1U << 0) /* Data Terminal Ready */ 181 182 /* Line Status Register */ 183 #define IXP425_UART_LSR 0x0014 184 #define LSR_FIFOE (1U << 7) 185 #define LSR_TEMT (1U << 6) /* Transmitter empty: byte sent */ 186 #define LSR_TDRQ (1U << 5) /* Transmitter buffer empty */ 187 #define LSR_BI (1U << 4) /* Break detected */ 188 #define LSR_FE (1U << 3) /* Framing error: bad stop bit */ 189 #define LSR_PE (1U << 2) /* Parity error */ 190 #define LSR_OE (1U << 1) /* Overrun, lost incoming byte */ 191 #define LSR_DR (1U << 0) /* Byte ready in Receive Buffer */ 192 193 /* Modem Status Register */ 194 #define IXP425_UART_MSR 0x0018 195 #define MSR_DCD (1U << 7) /* Current Data Carrier Detect */ 196 #define MSR_RI (1U << 6) /* Current Ring Indicator */ 197 #define MSR_DSR (1U << 5) /* Current Data Set Ready */ 198 #define MSR_CTS (1U << 4) /* Current Clear to Send */ 199 #define MSR_DDCD (1U << 3) /* DCD has changed state */ 200 #define MSR_TERI (1U << 2) /* RI has toggled low to high */ 201 #define MSR_DDSR (1U << 1) /* DSR has changed state */ 202 #define MSR_DCTS (1U << 0) /* CTS has changed state */ 203 204 /* Scratch Pad Status Register */ 205 #define IXP425_UART_SPR 0x001C 206 207 /* Slow Infrared Select Status Register */ 208 #define IXP425_UART_ISR 0x0020 209 210 #define IXP4XX_COM_NPORTS 8 211 212 /* 213 * Timers 214 * 215 */ 216 217 #define IXP425_OST_TIM0 0x0004 218 #define IXP425_OST_TIM1 0x000C 219 220 #define IXP425_OST_TIM0_RELOAD 0x0008 221 #define IXP425_OST_TIM1_RELOAD 0x0010 222 #define TIMERRELOAD_MASK 0xFFFFFFFC 223 #define OST_ONESHOT_EN (1U << 1) 224 #define OST_TIMER_EN (1U << 0) 225 226 #define IXP425_OST_STATUS 0x0020 227 #define OST_WARM_RESET (1U << 4) 228 #define OST_WDOG_INT (1U << 3) 229 #define OST_TS_INT (1U << 2) 230 #define OST_TIM1_INT (1U << 1) 231 #define OST_TIM0_INT (1U << 0) 232 233 /* 234 * Interrupt Controller Unit. 235 * 236 */ 237 238 #define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET 239 #define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET 240 #define IXP425_IRQ_SIZE 0x00000020UL 241 242 #define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00) 243 #define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04) 244 #define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08) 245 #define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C) 246 #define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10) 247 #define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14) 248 #define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18) 249 #define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C) 250 251 #define IXP425_INT_SW1 31 /* SW Interrupt 1 */ 252 #define IXP425_INT_SW0 30 /* SW Interrupt 0 */ 253 #define IXP425_INT_GPIO_12 29 /* GPIO 12 */ 254 #define IXP425_INT_GPIO_11 28 /* GPIO 11 */ 255 #define IXP425_INT_GPIO_10 27 /* GPIO 11 */ 256 #define IXP425_INT_GPIO_9 26 /* GPIO 9 */ 257 #define IXP425_INT_GPIO_8 25 /* GPIO 8 */ 258 #define IXP425_INT_GPIO_7 24 /* GPIO 7 */ 259 #define IXP425_INT_GPIO_6 23 /* GPIO 6 */ 260 #define IXP425_INT_GPIO_5 22 /* GPIO 5 */ 261 #define IXP425_INT_GPIO_4 21 /* GPIO 4 */ 262 #define IXP425_INT_GPIO_3 20 /* GPIO 3 */ 263 #define IXP425_INT_GPIO_2 19 /* GPIO 2 */ 264 #define IXP425_INT_XPMU 18 /* XScale PMU */ 265 #define IXP425_INT_PMU 17 /* PMU */ 266 #define IXP425_INT_WDOG 16 /* Watchdog Timer */ 267 #define IXP425_INT_UART1 15 /* Console UART */ 268 #define IXP425_INT_STAMP 14 /* Timestamp Timer */ 269 #define IXP425_INT_UART0 13 /* HighSpeed UART */ 270 #define IXP425_INT_USB 12 /* USB */ 271 #define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */ 272 #define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */ 273 #define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */ 274 #define IXP425_INT_PCIINT 8 /* PCI Interrupt */ 275 #define IXP425_INT_GPIO_1 7 /* GPIO 1 */ 276 #define IXP425_INT_GPIO_0 6 /* GPIO 0 */ 277 #define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */ 278 #define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */ 279 #define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */ 280 #define IXP425_INT_NPE_B 2 /* Ethernet NPE B */ 281 #define IXP425_INT_NPE_A 1 /* Ethernet NPE A */ 282 #define IXP425_INT_HSS 0 /* WAN/HSS NPE */ 283 284 /* 285 * software interrupt 286 */ 287 #define IXP425_INT_bit31 31 288 #define IXP425_INT_bit30 30 289 #define IXP425_INT_bit29 29 290 #define IXP425_INT_bit22 22 291 292 #define IXP425_INT_HWMASK (0xffffffff & \ 293 ~((1 << IXP425_INT_bit31) | \ 294 (1 << IXP425_INT_bit30) | \ 295 (1 << IXP425_INT_bit29) | \ 296 (1 << IXP425_INT_bit22))) 297 298 /* 299 * Expansion Bus 300 */ 301 #define IXP425_EXP_HWBASE 0xc4000000UL 302 #define IXP425_EXP_VBASE (IXP425_IO_VBASE + IXP425_IO_SIZE) 303 #define IXP425_EXP_SIZE IXP425_REG_SIZE 304 305 /* offset */ 306 #define EXP_TIMING_CS0_OFFSET 0x0000 307 #define EXP_TIMING_CS1_OFFSET 0x0004 308 #define EXP_TIMING_CS2_OFFSET 0x0008 309 #define EXP_TIMING_CS3_OFFSET 0x000c 310 #define EXP_TIMING_CS4_OFFSET 0x0010 311 #define EXP_TIMING_CS5_OFFSET 0x0014 312 #define EXP_TIMING_CS6_OFFSET 0x0018 313 #define EXP_TIMING_CS7_OFFSET 0x001c 314 315 #define IXP425_EXP_RECOVERY_SHIFT 16 316 #define IXP425_EXP_HOLD_SHIFT 20 317 #define IXP425_EXP_STROBE_SHIFT 22 318 #define IXP425_EXP_SETUP_SHIFT 26 319 #define IXP425_EXP_ADDR_SHIFT 28 320 #define IXP425_EXP_CS_EN (1U << 31) 321 322 #define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT) 323 #define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT) 324 #define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT) 325 #define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) 326 #define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) 327 328 // EXP_CSn bits 329 #define EXP_BYTE_EN (1 << 0) 330 #define EXP_WR_EN (1 << 1) 331 #define EXP_SPLT_EN (1 << 3) 332 #define EXP_MUX_EN (1 << 4) 333 #define EXP_HRDY_POL (1 << 5) 334 #define EXP_BYTE_RD16 (1 << 6) 335 #define EXP_SZ_512 (0 << 10) 336 #define EXP_SZ_1K (1 << 10) 337 #define EXP_SZ_2K (2 << 10) 338 #define EXP_SZ_4K (3 << 10) 339 #define EXP_SZ_8K (4 << 10) 340 #define EXP_SZ_16K (5 << 10) 341 #define EXP_SZ_32K (6 << 10) 342 #define EXP_SZ_64K (7 << 10) 343 #define EXP_SZ_128K (8 << 10) 344 #define EXP_SZ_256K (9 << 10) 345 #define EXP_SZ_512K (10 << 10) 346 #define EXP_SZ_1M (11 << 10) 347 #define EXP_SZ_2M (12 << 10) 348 #define EXP_SZ_4M (13 << 10) 349 #define EXP_SZ_8M (14 << 10) 350 #define EXP_SZ_16M (15 << 10) 351 #define EXP_CYC_INTEL (0 << 14) 352 #define EXP_CYC_MOTO (1 << 14) 353 #define EXP_CYC_HPI (2 << 14) 354 355 // EXP_CNFG0 bits 356 #define EXP_CNFG0_8BIT (1 << 0) 357 #define EXP_CNFG0_PCI_HOST (1 << 1) 358 #define EXP_CNFG0_PCI_ARB (1 << 2) 359 #define EXP_CNFG0_PCI_66MHZ (1 << 4) 360 #define EXP_CNFG0_MEM_MAP (1 << 31) 361 362 // EXP_CNFG1 bits 363 #define EXP_CNFG1_SW_INT0 (1 << 0) 364 #define EXP_CNFG1_SW_INT1 (1 << 1) 365 366 /* 367 * PCI 368 */ 369 /* PCI Configuration Registers */ 370 #define IXP425_PCI_HWBASE 0xc0000000 371 #define IXP425_PCI_VBASE (IXP425_EXP_VBASE + IXP425_EXP_SIZE) 372 #define IXP425_PCI_SIZE IXP425_REG_SIZE /* 0x1000 */ 373 374 /* 375 * Performance Monitoring Unit (CP14) 376 * 377 * CP14.0.1 Performance Monitor Control Register(PMNC) 378 * CP14.1.1 Clock Counter(CCNT) 379 * CP14.4.1 Interrupt Enable Register(INTEN) 380 * CP14.5.1 Overflow Flag Register(FLAG) 381 * CP14.8.1 Event Selection Register(EVTSEL) 382 * CP14.0.2 Performance Counter Register 0(PMN0) 383 * CP14.1.2 Performance Counter Register 0(PMN1) 384 * CP14.2.2 Performance Counter Register 0(PMN2) 385 * CP14.3.2 Performance Counter Register 0(PMN3) 386 */ 387 388 #define PMNC_E 0x00000001 /* enable all counters */ 389 #define PMNC_P 0x00000002 /* reset all PMNs to 0 */ 390 #define PMNC_C 0x00000004 /* clock counter reset */ 391 #define PMNC_D 0x00000008 /* clock counter / 64 */ 392 393 #define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */ 394 #define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */ 395 #define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */ 396 #define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */ 397 #define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */ 398 399 #define FLAG_CC_IF 0x00000001 /* clock counter overflow */ 400 #define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */ 401 #define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */ 402 #define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */ 403 #define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */ 404 405 #define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */ 406 #define PMNC_EVCNT0_SHIFT 0 407 #define PMNC_EVCNT1_SHIFT 8 408 #define PMNC_EVCNT2_SHIFT 16 409 #define PMNC_EVCNT3_SHIFT 24 410 411 #endif /* _IXP425REG_H_ */ 412
Indexes created Sat Oct 25 07:10:08 GMT 2025