pxa2x0_ohci.c revision 1.6
1 /* $NetBSD: pxa2x0_ohci.c,v 1.6 2009/08/09 06:12:34 kiyohara Exp $ */ 2 /* $OpenBSD: pxa2x0_ohci.c,v 1.19 2005/04/08 02:32:54 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005 David Gwynne <dlg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/param.h> 21 #include <sys/systm.h> 22 #include <sys/device.h> 23 #include <sys/kernel.h> 24 25 #include <machine/intr.h> 26 #include <machine/bus.h> 27 28 #include <dev/usb/usb.h> 29 #include <dev/usb/usbdi.h> 30 #include <dev/usb/usbdivar.h> 31 #include <dev/usb/usb_mem.h> 32 33 #include <dev/usb/ohcireg.h> 34 #include <dev/usb/ohcivar.h> 35 36 #include <arm/xscale/pxa2x0cpu.h> 37 #include <arm/xscale/pxa2x0reg.h> 38 #include <arm/xscale/pxa2x0var.h> 39 #include <arm/xscale/pxa2x0_gpio.h> 40 41 struct pxaohci_softc { 42 ohci_softc_t sc; 43 44 void *sc_ih; 45 }; 46 47 #if 0 48 static void pxaohci_power(int, void *); 49 #endif 50 static void pxaohci_enable(struct pxaohci_softc *); 51 static void pxaohci_disable(struct pxaohci_softc *); 52 53 #define HREAD4(sc,r) bus_space_read_4((sc)->sc.iot, (sc)->sc.ioh, (r)) 54 #define HWRITE4(sc,r,v) bus_space_write_4((sc)->sc.iot, (sc)->sc.ioh, (r), (v)) 55 56 static int 57 pxaohci_match(device_t parent, struct cfdata *cf, void *aux) 58 { 59 struct pxaip_attach_args *pxa = aux; 60 61 if (CPU_IS_PXA270 && strcmp(pxa->pxa_name, cf->cf_name) == 0) { 62 pxa->pxa_size = PXA2X0_USBHC_SIZE; 63 return 1; 64 } 65 return 0; 66 } 67 68 static void 69 pxaohci_attach(device_t parent, device_t self, void *aux) 70 { 71 struct pxaohci_softc *sc = device_private(self); 72 struct pxaip_attach_args *pxa = aux; 73 bus_space_handle_t powman_ioh; 74 usbd_status r; 75 76 #ifdef USB_DEBUG 77 { 78 //extern int ohcidebug; 79 //ohcidebug = 16; 80 } 81 #endif 82 83 sc->sc.iot = pxa->pxa_iot; 84 sc->sc.sc_bus.dmatag = pxa->pxa_dmat; 85 sc->sc.sc_size = 0; 86 sc->sc_ih = NULL; 87 sc->sc.sc_dev = self; 88 sc->sc.sc_bus.hci_private = sc; 89 90 aprint_normal("\n"); 91 aprint_naive("\n"); 92 93 /* Map I/O space */ 94 if (bus_space_map(sc->sc.iot, pxa->pxa_addr, pxa->pxa_size, 0, 95 &sc->sc.ioh)) { 96 aprint_error_dev(sc->sc.sc_dev, "couldn't map memory space\n"); 97 return; 98 } 99 sc->sc.sc_size = pxa->pxa_size; 100 101 /* XXX copied from ohci_pci.c. needed? */ 102 bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size, 103 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 104 105 /* start the usb clock */ 106 pxa2x0_clkman_config(CKEN_USBHC, 1); 107 pxaohci_enable(sc); 108 109 /* Disable interrupts, so we don't get any spurious ones. */ 110 bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE, 111 OHCI_MIE); 112 113 sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_USBH1, IPL_USB, 114 ohci_intr, &sc->sc); 115 if (sc->sc_ih == NULL) { 116 aprint_error_dev(sc->sc.sc_dev, 117 "unable to establish interrupt\n"); 118 goto free_map; 119 } 120 121 strlcpy(sc->sc.sc_vendor, "PXA27x", sizeof(sc->sc.sc_vendor)); 122 r = ohci_init(&sc->sc); 123 if (r != USBD_NORMAL_COMPLETION) { 124 aprint_error_dev(sc->sc.sc_dev, "init failed, error=%d\n", r); 125 goto free_intr; 126 } 127 128 #if 0 129 sc->sc.sc_powerhook = powerhook_establish(sc->sc.sc_bus.bdev.dv_xname, 130 pxaohci_power, sc); 131 if (sc->sc.sc_powerhook == NULL) { 132 aprint_error("%s: cannot establish powerhook\n", 133 sc->sc.sc_dev->sc_bus.bdev.dv_xname); 134 } 135 #endif 136 137 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 138 139 return; 140 141 free_intr: 142 pxa2x0_intr_disestablish(sc->sc_ih); 143 sc->sc_ih = NULL; 144 free_map: 145 pxaohci_disable(sc); 146 pxa2x0_clkman_config(CKEN_USBHC, 0); 147 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 148 sc->sc.sc_size = 0; 149 } 150 151 static int 152 pxaohci_detach(device_t self, int flags) 153 { 154 struct pxaohci_softc *sc = device_private(self); 155 int error; 156 157 error = ohci_detach(&sc->sc, flags); 158 if (error) 159 return error; 160 161 #if 0 162 if (sc->sc.sc_powerhook) { 163 powerhook_disestablish(sc->sc.sc_powerhook); 164 sc->sc.sc_powerhook = NULL; 165 } 166 #endif 167 168 if (sc->sc_ih) { 169 pxa2x0_intr_disestablish(sc->sc_ih); 170 sc->sc_ih = NULL; 171 } 172 173 pxaohci_disable(sc); 174 175 /* stop clock */ 176 pxa2x0_clkman_config(CKEN_USBHC, 0); 177 178 if (sc->sc.sc_size) { 179 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 180 sc->sc.sc_size = 0; 181 } 182 183 return 0; 184 } 185 186 #if 0 187 static void 188 pxaohci_power(int why, void *arg) 189 { 190 struct pxaohci_softc *sc = (struct pxaohci_softc *)arg; 191 int s; 192 193 s = splhardusb(); 194 sc->sc.sc_bus.use_polling++; 195 switch (why) { 196 case PWR_STANDBY: 197 case PWR_SUSPEND: 198 #if 0 199 ohci_power(why, &sc->sc); 200 #endif 201 pxa2x0_clkman_config(CKEN_USBHC, 0); 202 break; 203 204 case PWR_RESUME: 205 pxa2x0_clkman_config(CKEN_USBHC, 1); 206 pxaohci_enable(sc); 207 #if 0 208 ohci_power(why, &sc->sc); 209 #endif 210 break; 211 } 212 sc->sc.sc_bus.use_polling--; 213 splx(s); 214 } 215 #endif 216 217 static void 218 pxaohci_enable(struct pxaohci_softc *sc) 219 { 220 uint32_t hr; 221 222 /* Full host reset */ 223 hr = HREAD4(sc, USBHC_HR); 224 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR); 225 226 DELAY(USBHC_RST_WAIT); 227 228 hr = HREAD4(sc, USBHC_HR); 229 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR)); 230 231 /* Force system bus interface reset */ 232 hr = HREAD4(sc, USBHC_HR); 233 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FSBIR); 234 235 while (HREAD4(sc, USBHC_HR) & USBHC_HR_FSBIR) 236 DELAY(3); 237 238 /* Enable the ports (physically only one, only enable that one?) */ 239 hr = HREAD4(sc, USBHC_HR); 240 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE)); 241 hr = HREAD4(sc, USBHC_HR); 242 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & 243 ~(USBHC_HR_SSEP1 | USBHC_HR_SSEP2 | USBHC_HR_SSEP3)); 244 HWRITE4(sc, USBHC_HIE, USBHC_HIE_RWIE | USBHC_HIE_UPRIE); 245 246 hr = HREAD4(sc, USBHC_UHCRHDA); 247 } 248 249 static void 250 pxaohci_disable(struct pxaohci_softc *sc) 251 { 252 uint32_t hr; 253 254 /* Full host reset */ 255 hr = HREAD4(sc, USBHC_HR); 256 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR); 257 258 DELAY(USBHC_RST_WAIT); 259 260 hr = HREAD4(sc, USBHC_HR); 261 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR)); 262 } 263 264 265 CFATTACH_DECL2_NEW(pxaohci, sizeof(struct pxaohci_softc), 266 pxaohci_match, pxaohci_attach, pxaohci_detach, ohci_activate, NULL, 267 ohci_childdet); 268 269 270
Indexes created Tue Oct 21 12:09:54 GMT 2025