wdc_mb.c revision 1.11
1 /* $NetBSD: wdc_mb.c,v 1.11 2002/10/02 05:04:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/malloc.h> 43 #include <sys/device.h> 44 45 #include <machine/bswap.h> 46 #include <machine/cpu.h> 47 #include <machine/bus.h> 48 #include <machine/iomap.h> 49 #include <machine/mfp.h> 50 #include <machine/dma.h> 51 52 #include <dev/ata/atavar.h> 53 #include <dev/ic/wdcvar.h> 54 55 #include <m68k/asm_single.h> 56 57 #include <atari/dev/ym2149reg.h> 58 #include <atari/atari/device.h> 59 60 /* 61 * XXX This code currently doesn't even try to allow 32-bit data port use. 62 */ 63 static int claim_hw __P((void *, int)); 64 static void free_hw __P((void *)); 65 static void read_multi_2_swap __P((bus_space_tag_t, bus_space_handle_t, 66 bus_size_t, u_int16_t *, bus_size_t)); 67 static void write_multi_2_swap __P((bus_space_tag_t, bus_space_handle_t, 68 bus_size_t, const u_int16_t *, bus_size_t)); 69 70 struct wdc_mb_softc { 71 struct wdc_softc sc_wdcdev; 72 struct channel_softc *wdc_chanptr; 73 struct channel_softc wdc_channel; 74 void *sc_ih; 75 }; 76 77 int wdc_mb_probe __P((struct device *, struct cfdata *, void *)); 78 void wdc_mb_attach __P((struct device *, struct device *, void *)); 79 80 CFATTACH_DECL(wdc_mb, sizeof(struct wdc_mb_softc), 81 wdc_mb_probe, wdc_mb_attach, NULL, NULL); 82 83 int 84 wdc_mb_probe(parent, cfp, aux) 85 struct device *parent; 86 struct cfdata *cfp; 87 void *aux; 88 { 89 static int wdc_matched = 0; 90 struct channel_softc ch; 91 int result = 0; 92 u_char sv_ierb; 93 94 if ((machineid & ATARI_TT) || strcmp("wdc", aux) || wdc_matched) 95 return 0; 96 if (!atari_realconfig) 97 return 0; 98 99 memset(&ch, 0, sizeof(ch)); 100 101 ch.cmd_iot = ch.ctl_iot = mb_alloc_bus_space_tag(); 102 if (ch.cmd_iot == NULL) 103 return 0; 104 ch.cmd_iot->stride = 2; 105 ch.cmd_iot->wo_1 = 1; 106 107 if (bus_space_map(ch.cmd_iot, 0xfff00000, 0x40, 0, &ch.cmd_ioh)) 108 return 0; 109 if (bus_space_subregion(ch.cmd_iot, ch.cmd_ioh, 0x38, 1, &ch.ctl_ioh)) 110 return 0; 111 112 /* 113 * Make sure IDE interrupts are disabled during probing. 114 */ 115 sv_ierb = MFP->mf_ierb; 116 MFP->mf_ierb &= ~IB_DINT; 117 118 /* 119 * Make sure that IDE is turned on on the Falcon. 120 */ 121 if (machineid & ATARI_FALCON) 122 ym2149_ser2(0); 123 124 result = wdcprobe(&ch); 125 126 MFP->mf_ierb = sv_ierb; 127 128 bus_space_unmap(ch.cmd_iot, ch.cmd_ioh, 0x40); 129 mb_free_bus_space_tag(ch.cmd_iot); 130 131 if (result) 132 wdc_matched = 1; 133 return (result); 134 } 135 136 void 137 wdc_mb_attach(parent, self, aux) 138 struct device *parent, *self; 139 void *aux; 140 { 141 struct wdc_mb_softc *sc = (void *)self; 142 143 printf("\n"); 144 145 sc->wdc_channel.cmd_iot = sc->wdc_channel.ctl_iot = 146 mb_alloc_bus_space_tag(); 147 sc->wdc_channel.cmd_iot->stride = 2; 148 sc->wdc_channel.cmd_iot->wo_1 = 1; 149 sc->wdc_channel.cmd_iot->abs_rms_2 = read_multi_2_swap; 150 sc->wdc_channel.cmd_iot->abs_wms_2 = write_multi_2_swap; 151 if (bus_space_map(sc->wdc_channel.cmd_iot, 0xfff00000, 0x40, 0, 152 &sc->wdc_channel.cmd_ioh)) { 153 printf("%s: couldn't map registers\n", 154 sc->sc_wdcdev.sc_dev.dv_xname); 155 return; 156 } 157 if (bus_space_subregion(sc->wdc_channel.cmd_iot, 158 sc->wdc_channel.cmd_ioh, 0x38, 1, &sc->wdc_channel.ctl_ioh)) 159 return; 160 161 /* 162 * Play a nasty trick here. Normally we only manipulate the 163 * interrupt *mask*. However to defeat wd_get_parms(), we 164 * disable the interrupts here using the *enable* register. 165 */ 166 MFP->mf_ierb &= ~IB_DINT; 167 168 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_HWLOCK | 169 WDC_CAPABILITY_ATA_NOSTREAM; 170 sc->sc_wdcdev.PIO_cap = 0; 171 sc->sc_wdcdev.claim_hw = &claim_hw; 172 sc->sc_wdcdev.free_hw = &free_hw; 173 sc->wdc_chanptr = &sc->wdc_channel; 174 sc->sc_wdcdev.channels = &sc->wdc_chanptr; 175 sc->sc_wdcdev.nchannels = 1; 176 sc->wdc_channel.channel = 0; 177 sc->wdc_channel.wdc = &sc->sc_wdcdev; 178 sc->wdc_channel.ch_queue = malloc(sizeof(struct channel_queue), 179 M_DEVBUF, M_NOWAIT); 180 if (sc->wdc_channel.ch_queue == NULL) { 181 printf("%s: can't allocate memory for command queue", 182 sc->sc_wdcdev.sc_dev.dv_xname); 183 return; 184 } 185 wdcattach(&sc->wdc_channel); 186 187 /* 188 * Setup & enable disk related interrupts. 189 */ 190 MFP->mf_ierb |= IB_DINT; 191 MFP->mf_iprb = (u_int8_t)~IB_DINT; 192 MFP->mf_imrb |= IB_DINT; 193 } 194 195 /* 196 * Hardware locking 197 */ 198 static int wd_lock; 199 200 static int 201 claim_hw(softc, maysleep) 202 void *softc; 203 int maysleep; 204 { 205 if (wd_lock != DMA_LOCK_GRANT) { 206 if (wd_lock == DMA_LOCK_REQ) { 207 /* 208 * ST_DMA access is being claimed. 209 */ 210 return 0; 211 } 212 if (!st_dmagrab((dma_farg)wdcintr, 213 (dma_farg)(maysleep ? NULL : wdcrestart), softc, 214 &wd_lock, 1)) 215 return 0; 216 } 217 return 1; 218 } 219 220 static void 221 free_hw(softc) 222 void *softc; 223 { 224 /* 225 * Flush pending interrupts before giving-up lock 226 */ 227 MFP->mf_iprb = (u_int8_t)~IB_DINT; 228 229 /* 230 * Only free the lock on a Falcon. On the Hades, keep it. 231 */ 232 /* if (machineid & ATARI_FALCON) */ 233 st_dmafree(softc, &wd_lock); 234 } 235 236 /* 237 * XXX 238 * This piece of uglyness is caused by the fact that the byte lanes of 239 * the data-register are swapped on the atari. This works OK for an IDE 240 * disk, but turns into a nightmare when used on atapi devices. 241 */ 242 #define calc_addr(base, off, stride, wm) \ 243 ((u_long)(base) + ((off) << (stride)) + (wm)) 244 245 static void 246 read_multi_2_swap(t, h, o, a, c) 247 bus_space_tag_t t; 248 bus_space_handle_t h; 249 bus_size_t o, c; 250 u_int16_t *a; 251 { 252 u_int16_t *ba; 253 254 ba = (u_int16_t *)calc_addr(h, o, t->stride, t->wo_2); 255 for (; c; a++, c--) 256 *a = bswap16(*ba); 257 } 258 259 static void 260 write_multi_2_swap(t, h, o, a, c) 261 bus_space_tag_t t; 262 bus_space_handle_t h; 263 bus_size_t o, c; 264 const u_int16_t *a; 265 { 266 u_int16_t *ba; 267 268 ba = (u_int16_t *)calc_addr(h, o, t->stride, t->wo_2); 269 for (; c; a++, c--) 270 *ba = bswap16(*a); 271 } 272
Indexes created Mon Sep 22 10:09:38 GMT 2025