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      1 /*	$NetBSD: bebox.h,v 1.2 2012/10/20 12:37:49 kiyohara Exp $	*/
      2 /*
      3  * Copyright (c) 2011 KIYOHARA Takashi
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #ifndef _BEBOX_H
     29 #define _BEBOX_H
     30 
     31 /*
     32  * BeBox mainboard's Register
     33  */
     34 #define BEBOX_REG		0x7ffff000
     35 
     36 #define BEBOX_SET_MASK		0x80000000
     37 #define BEBOX_CLEAR_MASK	0x00000000
     38 
     39 #define READ_BEBOX_REG(reg)	*(volatile uint32_t *)(BEBOX_REG + (reg))
     40 #define SET_BEBOX_REG(reg, v)	\
     41 	*(volatile uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_SET_MASK)
     42 #define CLEAR_BEBOX_REG(reg, v)	\
     43 	*(volatile uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_CLEAR_MASK)
     44 
     45 #define CPU0_INT_MASK	     0x0f0	/* Interrupt Mask for CPU0 */
     46 #define CPU1_INT_MASK	     0x1f0	/* Interrupt Mask for CPU1 */
     47 #define INT_SOURCE	     0x2f0	/* Interrupt Source */
     48 #define CPU_CONTROL	     0x3f0	/* Inter-CPU Interrupt */
     49 #define CPU_RESET	     0x4f0	/* Reset Control */
     50 #define INTR_VECTOR_REG	     0xff0
     51 
     52 #define BEBOX_INTR_MASK	0x0ffffffc
     53 
     54 /* Control */
     55 #define CPU0_SMI	(1 << 30)	/* SMI to CPU0 */
     56 #define CPU1_SMI	(1 << 29)	/* SMI to CPU1 */
     57 #define CPU1_INT	(1 << 28)	/* Interrupt to CPU1 (rev.1 only) */
     58 #define CPU0_TLBISYNC	(1 << 27)	/* tlbsync to CPU0 */
     59 #define CPU1_TLBISYNC	(1 << 26)	/* tlbsync to CPU1 */
     60 #define WHO_AM_I	(1 << 25)
     61 
     62 #define TLBISYNC_FROM(n)	(1 << (CPU1_TLBISYNC + (n)))
     63 
     64 /* Reset */
     65 #define CPU1_SRESET	(1 << 30)	/* Software Reset to CPU1 */
     66 #define CPU1_HRESET	(1 << 29)	/* Hardware Reset to CPU1 */
     67 
     68 #endif /* _BEBOX_H */
     69