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      1 /*	$NetBSD: io.c,v 1.8 2022/02/16 23:49:26 riastradh Exp $	*/
      2 
      3 /*-
      4  * Copyright (C) 1995-1997 Gary Thomas (gdt (at) linuxppc.org)
      5  * All rights reserved.
      6  *
      7  * PCI/ISA I/O support
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *      This product includes software developed by Gary Thomas.
     20  * 4. The name of the author may not be used to endorse or promote products
     21  *    derived from this software without specific prior written permission.
     22  *
     23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33  */
     34 
     35 #include <lib/libsa/stand.h>
     36 #include "boot.h"
     37 
     38 volatile u_char *PCI_mem = (u_char *)0xc0000000;
     39 volatile u_char *ISA_io  = (u_char *)0x80000000;
     40 volatile u_char *ISA_mem = (u_char *)0xc0000000;
     41 
     42 static int dcache_line_size = 32;
     43 
     44 void
     45 outb(int port, u_char val)
     46 {
     47 
     48 	ISA_io[port] = val;
     49 }
     50 
     51 void
     52 outw(int port, u_short val)
     53 {
     54 
     55 	outb(port, val >> 8);
     56 	outb(port + 1, val);
     57 }
     58 
     59 u_char
     60 inb(int port)
     61 {
     62 
     63 	return ISA_io[port];
     64 }
     65 
     66 u_short
     67 inw(int port)
     68 {
     69 
     70 	return *((volatile uint16_t *)(&ISA_io[port]));
     71 }
     72 
     73 u_short
     74 inwrb(int port)
     75 {
     76 
     77 	return le16toh(*((volatile uint16_t *)(&ISA_io[port])));
     78 }
     79 
     80 void
     81 writeb(u_long addr, u_char val)
     82 {
     83 
     84 	PCI_mem[addr] = val;
     85 }
     86 
     87 void
     88 writel(u_long addr, u_long val)
     89 {
     90 
     91 	*((u_long *)&PCI_mem[addr]) = htole32(val);
     92 }
     93 
     94 u_char
     95 readb(u_long addr)
     96 {
     97 
     98 	return PCI_mem[addr];
     99 }
    100 
    101 u_short
    102 readw(u_long addr)
    103 {
    104 
    105 	return le16toh(*((u_short *)&PCI_mem[addr]));
    106 }
    107 
    108 u_long
    109 readl(u_long addr)
    110 {
    111 
    112 	return le32toh(*((u_long *)&PCI_mem[addr]));
    113 }
    114 
    115 u_long
    116 local_to_PCI(u_long addr)
    117 {
    118 
    119 	return (addr & 0x7FFFFFFF) | 0x80000000;
    120 }
    121 
    122 void
    123 _wbinv(uint32_t adr, uint32_t siz)
    124 {
    125 	uint32_t bnd;
    126 
    127 	asm volatile("eieio" ::: "memory");
    128 	for (bnd = adr + siz; adr < bnd; adr += dcache_line_size)
    129 		asm volatile("dcbf 0,%0" :: "r"(adr) : "memory");
    130 	asm volatile("sync" ::: "memory");
    131 }
    132 
    133 void
    134 _inv(uint32_t adr, uint32_t siz)
    135 {
    136 	uint32_t bnd, off;
    137 
    138 	off = adr & (dcache_line_size - 1);
    139 	adr -= off;
    140 	siz += off;
    141 	asm volatile("eieio" ::: "memory");
    142 	if (off != 0) {
    143 		/* wbinv() leading unaligned dcache line */
    144 		asm volatile("dcbf 0,%0" :: "r"(adr) : "memory");
    145 		if (siz < dcache_line_size)
    146 			goto done;
    147 		adr += dcache_line_size;
    148 		siz -= dcache_line_size;
    149 	}
    150 	bnd = adr + siz;
    151 	off = bnd & (dcache_line_size - 1);
    152 	if (off != 0) {
    153 		/* wbinv() trailing unaligned dcache line */
    154 		asm volatile("dcbf 0,%0" :: "r"(bnd) : "memory"); /* it's OK */
    155 		if (siz < dcache_line_size)
    156 			goto done;
    157 		siz -= off;
    158 	}
    159 	for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) {
    160 		/* inv() intermediate dcache lines if ever */
    161 		asm volatile("dcbi 0,%0" :: "r"(adr) : "memory");
    162 	}
    163   done:
    164 	asm volatile("sync" ::: "memory");
    165 }
    166