pci_machdep.c revision 1.31 
1/*	$NetBSD: pci_machdep.c,v 1.31 2011/07/01 20:37:08 dyoung Exp $	*/
2
3/*
4 * Copyright (c) 2000 Soren S. Jorvang.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions, and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.31 2011/07/01 20:37:08 dyoung Exp $");
30
31#include <sys/types.h>
32#include <sys/param.h>
33#include <sys/time.h>
34#include <sys/systm.h>
35#include <sys/errno.h>
36#include <sys/device.h>
37#include <sys/extent.h>
38
39#define _COBALT_BUS_DMA_PRIVATE
40#include <sys/bus.h>
41#include <machine/intr.h>
42
43#include <dev/pci/pcivar.h>
44#include <dev/pci/pcireg.h>
45#include <dev/pci/pcidevs.h>
46#include <dev/pci/pciconf.h>
47#include <dev/pci/pciide_apollo_reg.h>
48
49#include <cobalt/dev/gtreg.h>
50
51/*
52 * PCI doesn't have any special needs; just use
53 * the generic versions of these functions.
54 */
55struct cobalt_bus_dma_tag pci_bus_dma_tag = {
56	_bus_dmamap_create,
57	_bus_dmamap_destroy,
58	_bus_dmamap_load,
59	_bus_dmamap_load_mbuf,
60	_bus_dmamap_load_uio,
61	_bus_dmamap_load_raw,
62	_bus_dmamap_unload,
63	_bus_dmamap_sync,
64	_bus_dmamem_alloc,
65	_bus_dmamem_free,
66	_bus_dmamem_map,
67	_bus_dmamem_unmap,
68	_bus_dmamem_mmap,
69};
70
71void
72pci_attach_hook(struct device *parent, struct device *self,
73    struct pcibus_attach_args *pba)
74{
75	/* XXX */
76
77	return;
78}
79
80int
81pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
82{
83
84	return 32;
85}
86
87pcitag_t
88pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
89{
90
91	return (bus << 16) | (device << 11) | (function << 8);
92}
93
94void
95pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
96{
97
98	if (bp != NULL)
99		*bp = (tag >> 16) & 0xff;
100	if (dp != NULL)
101		*dp = (tag >> 11) & 0x1f;
102	if (fp != NULL)
103		*fp = (tag >> 8) & 0x07;
104}
105
106pcireg_t
107pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
108{
109	pcireg_t data;
110	int bus, dev, func;
111
112	KASSERT(pc != NULL);
113
114	pci_decompose_tag(pc, tag, &bus, &dev, &func);
115
116	/*
117	 * 2700 hardware wedges on accesses to device 6.
118	 */
119	if (bus == 0 && dev == 6)
120		return 0;
121	/*
122	 * 2800 hardware wedges on accesses to device 31.
123	 */
124	if (bus == 0 && dev == 31)
125		return 0;
126
127	bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR,
128	    PCICFG_ENABLE | tag | reg);
129	data = bus_space_read_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_DATA);
130	bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR, 0);
131
132	return data;
133}
134
135void
136pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
137{
138
139	bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR,
140	    PCICFG_ENABLE | tag | reg);
141	bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_DATA, data);
142	bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR, 0);
143}
144
145int
146pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
147{
148	pci_chipset_tag_t pc = pa->pa_pc;
149	pcitag_t intrtag = pa->pa_intrtag;
150	int pin = pa->pa_intrpin;
151	int line = pa->pa_intrline;
152	int bus, dev, func;
153
154	pci_decompose_tag(pc, intrtag, &bus, &dev, &func);
155
156	/*
157	 * The interrupt lines of the internal Tulips are connected
158	 * directly to the CPU.
159	 */
160	if (cobalt_id == COBALT_ID_QUBE2700) {
161		if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A) {
162			/* tulip is connected to CPU INT2 on Qube2700 */
163			*ihp = NICU_INT + 2;
164			return 0;
165		}
166	} else {
167		if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A) {
168			/* the primary tulip is connected to CPU INT1 */
169			*ihp = NICU_INT + 1;
170			return 0;
171		}
172		if (bus == 0 && dev == 12 && pin == PCI_INTERRUPT_PIN_A) {
173			/* the secondary tulip is connected to CPU INT2 */
174			*ihp = NICU_INT + 2;
175			return 0;
176		}
177	}
178
179	/* sanity check */
180	if (line == 0 || line >= NICU_INT)
181		return -1;
182
183	*ihp = line;
184	return 0;
185}
186
187const char *
188pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
189{
190	static char irqstr[8];
191
192	if (ih >= NICU_INT)
193		sprintf(irqstr, "level %d", ih - NICU_INT);
194	else
195		sprintf(irqstr, "irq %d", ih);
196
197	return irqstr;
198}
199
200const struct evcnt *
201pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
202{
203
204	/* XXX for now, no evcnt parent reported */
205	return NULL;
206}
207
208int
209pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
210		 int attr, uint64_t data)
211{
212
213	switch (attr) {
214	case PCI_INTR_MPSAFE:
215		return 0;
216	default:
217		return ENODEV;
218	}
219}
220
221void *
222pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
223    int (*func)(void *), void *arg)
224{
225
226	if (ih >= NICU_INT)
227		return cpu_intr_establish(ih - NICU_INT, level, func, arg);
228	else
229		return icu_intr_establish(ih, IST_LEVEL, level, func, arg);
230}
231
232void
233pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
234{
235
236	/* Try both, only the valid one will disestablish. */
237	cpu_intr_disestablish(cookie);
238	icu_intr_disestablish(cookie);
239}
240
241void
242pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz,
243    int *iline)
244{
245
246	/*
247	 * Use irq 9 on all devices on the Qube's PCI slot.
248	 * XXX doesn't handle devices over PCI-PCI bridges
249	 */
250	if (bus == 0 && dev == 10 && pin != PCI_INTERRUPT_PIN_NONE)
251		*iline = 9;
252}
253
254int
255pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
256{
257
258	/* ignore bogus IDs */
259	if (PCI_VENDOR(id) == 0)
260		return 0;
261
262	/* 2700 hardware wedges on accesses to device 6. */
263	if (bus == 0 && dev == 6)
264		return 0;
265
266	/* 2800 hardware wedges on accesses to device 31. */
267	if (bus == 0 && dev == 31)
268		return 0;
269
270	/* Don't configure the bridge and PCI probe. */
271	if (PCI_VENDOR(id) == PCI_VENDOR_MARVELL &&
272	    PCI_PRODUCT(id) == PCI_PRODUCT_MARVELL_GT64011)
273	        return 0;
274
275	/* Don't configure on-board VIA VT82C586 (pcib, uhci) */
276	if (bus == 0 && dev == 9 && (func == 0 || func == 2))
277		return 0;
278
279	/* Enable viaide secondary port. Some firmware doesn't enable it. */
280	if (bus == 0 && dev == 9 && func == 1) {
281		pcitag_t tag;
282		pcireg_t csr;
283
284#define	APO_VIAIDECONF	(APO_VIA_REGBASE + 0x00)
285
286		tag = pci_make_tag(pc, bus, dev, func);
287		csr = pci_conf_read(pc, tag, APO_VIAIDECONF);
288		pci_conf_write(pc, tag, APO_VIAIDECONF,
289		    csr | APO_IDECONF_EN(1));
290	}
291	return PCI_CONF_DEFAULT & ~(PCI_COMMAND_SERR_ENABLE |
292	    PCI_COMMAND_PARITY_ENABLE);
293}
294