PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

#include <sys/cpu.h> or <mips/cpuregs.h> as needed

branches: 1.36.4;
Convert cobalt to generic mips bus_dma.

branches: 1.35.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

kill sprintf

branches: 1.33.2;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

branches: 1.32.2; 1.32.12;
Cleanup kernel files to use sys variants for bus.h, cpu.h, and intr.h
Use <mips/..> for db_machdep.h and psl.h

#include <sys/bus.h> instead of <machine/bus.h>.

TAB/space cosmetics.

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

Merge forward from matt-nb5-mips64.
(XXX generic kernels on raq2 die after interrupts are enabled but gxemul
works fine).

branches: 1.27.20; 1.27.26; 1.27.28;
pci_intr_setattr(), allows PCI interrupts to be marked MPSAFE on x86, and
other platforms if the code is added.

pci_intr_map(...)
pci_intr_setattr(pc, ih, PCI_INTR_MPSAFE, 1);
pci_intr_establish(...)

branches: 1.26.2; 1.26.4; 1.26.6;
Reorganize interrupt handling on cobalt and allow multiple interrupts on
each icu irq to support multi function PCI devices in the Qube's PCI slot:

- split out interrupt stuff from machdep.c into new interrupt.c
- prepare struct *_intrhead to handle cpu and icu interrupts
- use LIST and malloc(9) to handle multiple interrupts per icu irq
(mostly taken from algor/pci/pcib.c and evbmips/malta/pci/pcib.c)
- move evcnt(9) stuff into *_intrhead from cobalt_intrhand
(i.e. make it per interrupt rather than per handler)
- in pci_intr_map(9) handle CPU interrupt separately and add a sanity check
- fixup interrupt lines for devices on the PCI slot in pci_conf_interrupt(9)
- move some device address definitions into <machine/cpu.h> and
remove <machine/leds.h>
- misc cosmetics

No objection on port-cobalt for three weeks.

branches: 1.25.42;
According to info from Byron Servies on port-cobalt,
the interrupt line from the primary (and only) tulip Ethernet
on Qube2700 is connected to CPU INT2, so handle it properly
in pci_intr_map(9).

branches: 1.24.6; 1.24.8; 1.24.10;
Vendor GALILEO is now MARVELL.

branches: 1.23.2;
- configure PCI space for viaide so that DMA will work even if the firmware
doesn't map DMA registers properly
- enable viaide secondary port explicitly which isn't enabled by some firmware

Tested on RaQ and RaQ2.

Check more invalid devices in pci_conf_hook(9).

Replace some magic numbers with macro.

ANSIfy.

branches: 1.19.2; 1.19.4; 1.19.6;
PCI_NETBSD_CONFIGURE should allocate (but not map) address space expansion
ROMS by default. Full discussion at
http://mail-index.netbsd.org/tech-kern/2005/12/16/0023.html
Closes PR kern/32467
Reviewed by briggs@

branches: 1.18.2; 1.18.4; 1.18.6;
merge ktrace-lwp.

branches: 1.17.2;
Switch cobalt port to use MI pci_configure_bus(9)
with options PCI_NETBSD_CONFIGURE.
Patch from KIYOHARA Takashi on port-cobalt.

This change makes siop(4) (and maybe all other PCI devices
using pci mem space) work on cobalt.

branches: 1.16.4; 1.16.6; 1.16.10;
- Use bus_space(9) to access PCI configuration registers on GT64111.
- Remove unused pci stuff from mainbus.c.

Use common mips generic software interrupt routines.

TAB/space cleanup.

__KERNEL_RCSID()

branches: 1.12.16;
Implement pci_intr_disestablish().

branches: 1.11.4; 1.11.8;
Fix typo on pci_intr_map() changes.
Reported by Shigeji Ishikawa <psybear@ogre.rim.or.jp> in port-cobalt/12121.

Change pci_intr_map to get interrupt source information from a "struct
pci_attach_args *" instead of from four separate parameters which in
all cases were extracted from the same "struct pci_attach_args".

This both simplifies the driver api, and allows for alternate PCI
interrupt mapping schemes, such as one using the tables described in
the Intel Multiprocessor Spec which describe interrupt wirings for
devices behind pci-pci bridges based on the device's location rather
the bridge's location.

Tested on alpha and i386; welcome to 1.5Q

branches: 1.9.2;
Don't include <vm/vm.h>.

remove/move more mach vm header files:

<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

Implement the more flexiable `evcnt' interface as discussed (briefly) on
tech-kern and now documented in evcnt(9).

Different form of PCI bug workaround. Should make 2700 system work.

branches: 1.5.2;
The interrupt line registers for the devices wired directly to the CPU
are not meaningfull. Instead match them by {bus,device,pin}.

Some cleanups.

Blocking soft interrupts can be useful..

Extend the evil interrupt kludge to the second ethernet.

NetBSD/cobalt. Work-in-progress.