1 /* $NetBSD: wdc_g1.c,v 1.6 2023/12/20 06:36:03 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_ata.h" /* for ATADEBUG */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/bus.h> 38 39 #include <machine/intr.h> 40 #include <machine/sysasicvar.h> 41 42 #include <arch/dreamcast/dev/g1/g1busvar.h> 43 44 #include <dev/ata/atavar.h> 45 #include <dev/ic/wdcvar.h> 46 #include <dev/ata/atareg.h> 47 48 #define WDC_G1_CMD_ADDR 0x005f7080 49 #define WDC_G1_REG_NPORTS 8 50 #define WDC_G1_CTL_ADDR 0x005f7018 51 #define WDC_G1_AUXREG_NPORTS 1 52 53 struct wdc_g1_softc { 54 struct wdc_softc sc_wdcdev; 55 struct ata_channel *wdc_chanlist[1]; 56 struct ata_channel ata_channel; 57 struct wdc_regs wdc_regs; 58 void *sc_ih; 59 int sc_irq; 60 }; 61 62 static int wdc_g1_probe(device_t, cfdata_t, void *); 63 static void wdc_g1_attach(device_t, device_t, void *); 64 static void wdc_g1_do_reset(struct ata_channel *, int); 65 static int wdc_g1_intr(void *); 66 67 CFATTACH_DECL_NEW(wdc_g1bus, sizeof(struct wdc_g1_softc), 68 wdc_g1_probe, wdc_g1_attach, NULL, NULL); 69 70 static int 71 wdc_g1_probe(device_t parent, cfdata_t cf, void *aux) 72 { 73 struct g1bus_attach_args *ga = aux; 74 struct wdc_regs wdr; 75 int result = 0, i; 76 77 *((volatile uint32_t *)0xa05f74e4) = 0x1fffff; 78 for (i = 0; i < 0x200000 / 4; i++) 79 (void)((volatile uint32_t *)0xa0000000)[i]; 80 81 wdr.cmd_iot = ga->ga_memt; 82 if (bus_space_map(wdr.cmd_iot, WDC_G1_CMD_ADDR, 83 WDC_G1_REG_NPORTS * 4, 0, &wdr.cmd_baseioh)) 84 goto out; 85 86 for (i = 0; i < WDC_G1_REG_NPORTS; i++) { 87 if (bus_space_subregion(wdr.cmd_iot, wdr.cmd_baseioh, i * 4, 88 i == 0 ? 2 : 1, &wdr.cmd_iohs[i]) != 0) 89 goto outunmap; 90 } 91 92 wdc_init_shadow_regs(&wdr); 93 94 wdr.ctl_iot = ga->ga_memt; 95 if (bus_space_map(wdr.ctl_iot, WDC_G1_CTL_ADDR, 96 WDC_G1_AUXREG_NPORTS, 0, &wdr.ctl_ioh)) 97 goto outunmap; 98 99 result = wdcprobe_with_reset(&wdr, wdc_g1_do_reset); 100 101 bus_space_unmap(wdr.ctl_iot, wdr.ctl_ioh, WDC_G1_AUXREG_NPORTS); 102 outunmap: 103 bus_space_unmap(wdr.cmd_iot, wdr.cmd_baseioh, WDC_G1_REG_NPORTS); 104 out: 105 return result; 106 } 107 108 static void 109 wdc_g1_attach(struct device *parent, struct device *self, void *aux) 110 { 111 struct wdc_g1_softc *sc = device_private(self); 112 struct wdc_regs *wdr; 113 struct g1bus_attach_args *ga = aux; 114 int i; 115 116 sc->sc_wdcdev.sc_atac.atac_dev = self; 117 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs; 118 119 wdr->cmd_iot = ga->ga_memt; 120 wdr->ctl_iot = ga->ga_memt; 121 if (bus_space_map(wdr->cmd_iot, WDC_G1_CMD_ADDR, 122 WDC_G1_REG_NPORTS * 4, 0, &wdr->cmd_baseioh) || 123 bus_space_map(wdr->ctl_iot, WDC_G1_CTL_ADDR, 124 WDC_G1_AUXREG_NPORTS, 0, &wdr->ctl_ioh)) { 125 aprint_error(": couldn't map registers\n"); 126 return; 127 } 128 129 for (i = 0; i < WDC_G1_REG_NPORTS; i++) { 130 if (bus_space_subregion(wdr->cmd_iot, 131 wdr->cmd_baseioh, i * 4, i == 0 ? 2 : 1, 132 &wdr->cmd_iohs[i]) != 0) { 133 aprint_error(": couldn't subregion registers\n"); 134 return; 135 } 136 } 137 138 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA; 139 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 140 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 141 sc->wdc_chanlist[0] = &sc->ata_channel; 142 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist; 143 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 144 sc->sc_wdcdev.wdc_maxdrives = 2; 145 sc->sc_wdcdev.reset = wdc_g1_do_reset; 146 sc->ata_channel.ch_channel = 0; 147 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 148 149 wdc_init_shadow_regs(wdr); 150 151 aprint_normal(": %s\n", sysasic_intr_string(SYSASIC_IRL9)); 152 153 sysasic_intr_establish(SYSASIC_EVENT_GDROM, IPL_BIO, SYSASIC_IRL9, 154 wdc_g1_intr, &sc->ata_channel); 155 156 wdcattach(&sc->ata_channel); 157 } 158 159 int 160 wdc_g1_intr(void *arg) 161 { 162 163 return wdcintr(arg); 164 } 165 166 /* 167 * This does what the generic wdc_do_reset() does, with additional 168 * GD-ROM reset. GD-ROM is a very early ATAPI device appeared in 1998 169 * and it doesn't reset itself by the WDCTL_RST in AUX_CTLR but requires 170 * ATAPI_SOFT_RESET command to reset whole device as a master. 171 */ 172 static void 173 wdc_g1_do_reset(struct ata_channel *chp, int poll) 174 { 175 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 176 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 177 int s = 0; 178 179 if (poll != 0) 180 s = splbio(); 181 182 /* master */ 183 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 184 WDSD_IBM); 185 delay(10); /* 400ns delay */ 186 /* assert SRST, wait for reset to complete */ 187 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 188 WDCTL_RST | WDCTL_4BIT | WDCTL_IDS); 189 delay(2000); 190 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 191 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 192 WDCTL_4BIT | WDCTL_IDS); 193 delay(10); /* 400ns delay */ 194 195 /* reset GD-ROM at master via ATAPI command */ 196 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 197 WDSD_IBM); 198 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 199 ATAPI_SOFT_RESET); 200 delay(100 * 1000); 201 202 if (poll != 0) 203 splx(s); 204 } 205
Indexes created Fri Sep 26 08:10:20 GMT 2025