wdc_g1.c revision 1.1
1 /* $NetBSD: wdc_g1.c,v 1.1 2016/12/29 11:49:05 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_ata.h" /* for ATADEBUG */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 #include <sys/bus.h> 39 40 #include <machine/intr.h> 41 #include <machine/sysasicvar.h> 42 43 #include <arch/dreamcast/dev/g1/g1busvar.h> 44 45 #include <dev/ata/atavar.h> 46 #include <dev/ic/wdcvar.h> 47 #include <dev/ata/atareg.h> 48 49 #define WDC_G1_CMD_ADDR 0x005f7080 50 #define WDC_G1_REG_NPORTS 8 51 #define WDC_G1_CTL_ADDR 0x005f7018 52 #define WDC_G1_AUXREG_NPORTS 1 53 54 struct wdc_g1_softc { 55 struct wdc_softc sc_wdcdev; 56 struct ata_channel *wdc_chanlist[1]; 57 struct ata_channel ata_channel; 58 struct ata_queue wdc_chqueue; 59 struct wdc_regs wdc_regs; 60 void *sc_ih; 61 int sc_irq; 62 }; 63 64 static int wdc_g1_probe(device_t, cfdata_t, void *); 65 static void wdc_g1_attach(device_t, device_t, void *); 66 static void wdc_g1_do_reset(struct ata_channel *, int); 67 static int wdc_g1_intr(void *); 68 69 CFATTACH_DECL_NEW(wdc_g1bus, sizeof(struct wdc_g1_softc), 70 wdc_g1_probe, wdc_g1_attach, NULL, NULL); 71 72 static int 73 wdc_g1_probe(device_t parent, cfdata_t cf, void *aux) 74 { 75 struct ata_channel ch; 76 struct g1bus_attach_args *ga = aux; 77 struct wdc_softc wdc; 78 struct wdc_regs wdr; 79 int result = 0, i; 80 #ifdef ATADEBUG 81 struct device dev; 82 #endif 83 84 *((volatile uint32_t *)0xa05f74e4) = 0x1fffff; 85 for (i = 0; i < 0x200000 / 4; i++) 86 (void)((volatile uint32_t *)0xa0000000)[i]; 87 88 memset(&wdc, 0, sizeof(wdc)); 89 memset(&ch, 0, sizeof(ch)); 90 ch.ch_atac = &wdc.sc_atac; 91 wdc.reset = wdc_g1_do_reset; 92 wdc.regs = &wdr; 93 94 wdr.cmd_iot = ga->ga_memt; 95 if (bus_space_map(wdr.cmd_iot, WDC_G1_CMD_ADDR, 96 WDC_G1_REG_NPORTS * 4, 0, &wdr.cmd_baseioh)) 97 goto out; 98 99 for (i = 0; i < WDC_G1_REG_NPORTS; i++) { 100 if (bus_space_subregion(wdr.cmd_iot, wdr.cmd_baseioh, i * 4, 101 i == 0 ? 2 : 1, &wdr.cmd_iohs[i]) != 0) 102 goto outunmap; 103 } 104 105 wdc_init_shadow_regs(&ch); 106 107 wdr.ctl_iot = ga->ga_memt; 108 if (bus_space_map(wdr.ctl_iot, WDC_G1_CTL_ADDR, 109 WDC_G1_AUXREG_NPORTS, 0, &wdr.ctl_ioh)) 110 goto outunmap; 111 112 #ifdef ATADEBUG 113 /* fake up device name for ATADEBUG_PRINT() with DEBUG_PROBE */ 114 memset(&dev, 0, sizeof(dev)); 115 strncat(dev.dv_xname, "wdc(g1probe)", sizeof(dev.dv_xname)); 116 wdc.sc_atac.atac_dev = &dev; 117 #endif 118 result = wdcprobe(&ch); 119 120 bus_space_unmap(wdr.ctl_iot, wdr.ctl_ioh, WDC_G1_AUXREG_NPORTS); 121 outunmap: 122 bus_space_unmap(wdr.cmd_iot, wdr.cmd_baseioh, WDC_G1_REG_NPORTS); 123 out: 124 return result; 125 } 126 127 static void 128 wdc_g1_attach(struct device *parent, struct device *self, void *aux) 129 { 130 struct wdc_g1_softc *sc = device_private(self); 131 struct wdc_regs *wdr; 132 struct g1bus_attach_args *ga = aux; 133 int i; 134 135 sc->sc_wdcdev.sc_atac.atac_dev = self; 136 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs; 137 138 wdr->cmd_iot = ga->ga_memt; 139 wdr->ctl_iot = ga->ga_memt; 140 if (bus_space_map(wdr->cmd_iot, WDC_G1_CMD_ADDR, 141 WDC_G1_REG_NPORTS * 4, 0, &wdr->cmd_baseioh) || 142 bus_space_map(wdr->ctl_iot, WDC_G1_CTL_ADDR, 143 WDC_G1_AUXREG_NPORTS, 0, &wdr->ctl_ioh)) { 144 aprint_error(": couldn't map registers\n"); 145 return; 146 } 147 148 for (i = 0; i < WDC_G1_REG_NPORTS; i++) { 149 if (bus_space_subregion(wdr->cmd_iot, 150 wdr->cmd_baseioh, i * 4, i == 0 ? 2 : 1, 151 &wdr->cmd_iohs[i]) != 0) { 152 aprint_error(": couldn't subregion registers\n"); 153 return; 154 } 155 } 156 157 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA; 158 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 159 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 160 sc->wdc_chanlist[0] = &sc->ata_channel; 161 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist; 162 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 163 sc->sc_wdcdev.wdc_maxdrives = 2; 164 sc->sc_wdcdev.reset = wdc_g1_do_reset; 165 sc->ata_channel.ch_channel = 0; 166 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 167 sc->ata_channel.ch_queue = &sc->wdc_chqueue; 168 wdc_init_shadow_regs(&sc->ata_channel); 169 170 aprint_normal(": %s\n", sysasic_intr_string(SYSASIC_IRL9)); 171 172 sysasic_intr_establish(SYSASIC_EVENT_GDROM, IPL_BIO, SYSASIC_IRL9, 173 wdc_g1_intr, &sc->ata_channel); 174 175 wdcattach(&sc->ata_channel); 176 } 177 178 int 179 wdc_g1_intr(void *arg) 180 { 181 182 return wdcintr(arg); 183 } 184 185 static void 186 wdc_g1_do_reset(struct ata_channel *chp, int poll) 187 { 188 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 189 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 190 int s = 0; 191 192 if (poll != 0) 193 s = splbio(); 194 195 /* master */ 196 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 197 WDSD_IBM); 198 delay(10); /* 400ns delay */ 199 /* assert SRST, wait for reset to complete */ 200 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 201 WDCTL_RST | WDCTL_4BIT | WDCTL_IDS); 202 delay(2000); 203 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 204 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 205 WDCTL_4BIT | WDCTL_IDS); 206 delay(10); /* 400ns delay */ 207 208 /* reset GD-ROM at master via ATAPI command */ 209 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 210 WDSD_IBM); 211 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 212 ATAPI_SOFT_RESET); 213 delay(100 * 1000); 214 215 if (poll != 0) 216 splx(s); 217 } 218
Indexes created Tue Sep 30 11:09:46 GMT 2025