wdc_g1.c revision 1.2
1 /* $NetBSD: wdc_g1.c,v 1.2 2017/10/07 19:58:53 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_ata.h" /* for ATADEBUG */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 #include <sys/bus.h> 39 40 #include <machine/intr.h> 41 #include <machine/sysasicvar.h> 42 43 #include <arch/dreamcast/dev/g1/g1busvar.h> 44 45 #include <dev/ata/atavar.h> 46 #include <dev/ic/wdcvar.h> 47 #include <dev/ata/atareg.h> 48 49 #define WDC_G1_CMD_ADDR 0x005f7080 50 #define WDC_G1_REG_NPORTS 8 51 #define WDC_G1_CTL_ADDR 0x005f7018 52 #define WDC_G1_AUXREG_NPORTS 1 53 54 struct wdc_g1_softc { 55 struct wdc_softc sc_wdcdev; 56 struct ata_channel *wdc_chanlist[1]; 57 struct ata_channel ata_channel; 58 struct wdc_regs wdc_regs; 59 void *sc_ih; 60 int sc_irq; 61 }; 62 63 static int wdc_g1_probe(device_t, cfdata_t, void *); 64 static void wdc_g1_attach(device_t, device_t, void *); 65 static void wdc_g1_do_reset(struct ata_channel *, int); 66 static int wdc_g1_intr(void *); 67 68 CFATTACH_DECL_NEW(wdc_g1bus, sizeof(struct wdc_g1_softc), 69 wdc_g1_probe, wdc_g1_attach, NULL, NULL); 70 71 static int 72 wdc_g1_probe(device_t parent, cfdata_t cf, void *aux) 73 { 74 struct ata_channel ch; 75 struct g1bus_attach_args *ga = aux; 76 struct wdc_softc wdc; 77 struct wdc_regs wdr; 78 int result = 0, i; 79 #ifdef ATADEBUG 80 struct device dev; 81 #endif 82 83 *((volatile uint32_t *)0xa05f74e4) = 0x1fffff; 84 for (i = 0; i < 0x200000 / 4; i++) 85 (void)((volatile uint32_t *)0xa0000000)[i]; 86 87 memset(&wdc, 0, sizeof(wdc)); 88 memset(&ch, 0, sizeof(ch)); 89 ch.ch_atac = &wdc.sc_atac; 90 wdc.reset = wdc_g1_do_reset; 91 wdc.regs = &wdr; 92 93 wdr.cmd_iot = ga->ga_memt; 94 if (bus_space_map(wdr.cmd_iot, WDC_G1_CMD_ADDR, 95 WDC_G1_REG_NPORTS * 4, 0, &wdr.cmd_baseioh)) 96 goto out; 97 98 for (i = 0; i < WDC_G1_REG_NPORTS; i++) { 99 if (bus_space_subregion(wdr.cmd_iot, wdr.cmd_baseioh, i * 4, 100 i == 0 ? 2 : 1, &wdr.cmd_iohs[i]) != 0) 101 goto outunmap; 102 } 103 104 wdc_init_shadow_regs(&ch); 105 106 wdr.ctl_iot = ga->ga_memt; 107 if (bus_space_map(wdr.ctl_iot, WDC_G1_CTL_ADDR, 108 WDC_G1_AUXREG_NPORTS, 0, &wdr.ctl_ioh)) 109 goto outunmap; 110 111 #ifdef ATADEBUG 112 /* fake up device name for ATADEBUG_PRINT() with DEBUG_PROBE */ 113 memset(&dev, 0, sizeof(dev)); 114 strncat(dev.dv_xname, "wdc(g1probe)", sizeof(dev.dv_xname)); 115 wdc.sc_atac.atac_dev = &dev; 116 #endif 117 result = wdcprobe(&ch); 118 119 bus_space_unmap(wdr.ctl_iot, wdr.ctl_ioh, WDC_G1_AUXREG_NPORTS); 120 outunmap: 121 bus_space_unmap(wdr.cmd_iot, wdr.cmd_baseioh, WDC_G1_REG_NPORTS); 122 out: 123 return result; 124 } 125 126 static void 127 wdc_g1_attach(struct device *parent, struct device *self, void *aux) 128 { 129 struct wdc_g1_softc *sc = device_private(self); 130 struct wdc_regs *wdr; 131 struct g1bus_attach_args *ga = aux; 132 int i; 133 134 sc->sc_wdcdev.sc_atac.atac_dev = self; 135 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs; 136 137 wdr->cmd_iot = ga->ga_memt; 138 wdr->ctl_iot = ga->ga_memt; 139 if (bus_space_map(wdr->cmd_iot, WDC_G1_CMD_ADDR, 140 WDC_G1_REG_NPORTS * 4, 0, &wdr->cmd_baseioh) || 141 bus_space_map(wdr->ctl_iot, WDC_G1_CTL_ADDR, 142 WDC_G1_AUXREG_NPORTS, 0, &wdr->ctl_ioh)) { 143 aprint_error(": couldn't map registers\n"); 144 return; 145 } 146 147 for (i = 0; i < WDC_G1_REG_NPORTS; i++) { 148 if (bus_space_subregion(wdr->cmd_iot, 149 wdr->cmd_baseioh, i * 4, i == 0 ? 2 : 1, 150 &wdr->cmd_iohs[i]) != 0) { 151 aprint_error(": couldn't subregion registers\n"); 152 return; 153 } 154 } 155 156 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA; 157 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 158 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 159 sc->wdc_chanlist[0] = &sc->ata_channel; 160 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist; 161 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 162 sc->sc_wdcdev.wdc_maxdrives = 2; 163 sc->sc_wdcdev.reset = wdc_g1_do_reset; 164 sc->ata_channel.ch_channel = 0; 165 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 166 sc->ata_channel.ch_queue = ata_queue_alloc(1); 167 wdc_init_shadow_regs(wdr); 168 169 aprint_normal(": %s\n", sysasic_intr_string(SYSASIC_IRL9)); 170 171 sysasic_intr_establish(SYSASIC_EVENT_GDROM, IPL_BIO, SYSASIC_IRL9, 172 wdc_g1_intr, &sc->ata_channel); 173 174 wdcattach(&sc->ata_channel); 175 } 176 177 int 178 wdc_g1_intr(void *arg) 179 { 180 181 return wdcintr(arg); 182 } 183 184 static void 185 wdc_g1_do_reset(struct ata_channel *chp, int poll) 186 { 187 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 188 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 189 int s = 0; 190 191 if (poll != 0) 192 s = splbio(); 193 194 /* master */ 195 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 196 WDSD_IBM); 197 delay(10); /* 400ns delay */ 198 /* assert SRST, wait for reset to complete */ 199 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 200 WDCTL_RST | WDCTL_4BIT | WDCTL_IDS); 201 delay(2000); 202 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 203 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 204 WDCTL_4BIT | WDCTL_IDS); 205 delay(10); /* 400ns delay */ 206 207 /* reset GD-ROM at master via ATAPI command */ 208 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 209 WDSD_IBM); 210 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 211 ATAPI_SOFT_RESET); 212 delay(100 * 1000); 213 214 if (poll != 0) 215 splx(s); 216 } 217
Indexes created Tue Sep 30 11:09:46 GMT 2025