wdc_g1.c revision 1.5
1 /* $NetBSD: wdc_g1.c,v 1.5 2019/09/14 17:11:39 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_ata.h" /* for ATADEBUG */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 #include <sys/bus.h> 39 40 #include <machine/intr.h> 41 #include <machine/sysasicvar.h> 42 43 #include <arch/dreamcast/dev/g1/g1busvar.h> 44 45 #include <dev/ata/atavar.h> 46 #include <dev/ic/wdcvar.h> 47 #include <dev/ata/atareg.h> 48 49 #define WDC_G1_CMD_ADDR 0x005f7080 50 #define WDC_G1_REG_NPORTS 8 51 #define WDC_G1_CTL_ADDR 0x005f7018 52 #define WDC_G1_AUXREG_NPORTS 1 53 54 struct wdc_g1_softc { 55 struct wdc_softc sc_wdcdev; 56 struct ata_channel *wdc_chanlist[1]; 57 struct ata_channel ata_channel; 58 struct wdc_regs wdc_regs; 59 void *sc_ih; 60 int sc_irq; 61 }; 62 63 static int wdc_g1_probe(device_t, cfdata_t, void *); 64 static void wdc_g1_attach(device_t, device_t, void *); 65 static void wdc_g1_do_reset(struct ata_channel *, int); 66 static int wdc_g1_intr(void *); 67 68 CFATTACH_DECL_NEW(wdc_g1bus, sizeof(struct wdc_g1_softc), 69 wdc_g1_probe, wdc_g1_attach, NULL, NULL); 70 71 static int 72 wdc_g1_probe(device_t parent, cfdata_t cf, void *aux) 73 { 74 struct g1bus_attach_args *ga = aux; 75 struct wdc_regs wdr; 76 int result = 0, i; 77 78 *((volatile uint32_t *)0xa05f74e4) = 0x1fffff; 79 for (i = 0; i < 0x200000 / 4; i++) 80 (void)((volatile uint32_t *)0xa0000000)[i]; 81 82 wdr.cmd_iot = ga->ga_memt; 83 if (bus_space_map(wdr.cmd_iot, WDC_G1_CMD_ADDR, 84 WDC_G1_REG_NPORTS * 4, 0, &wdr.cmd_baseioh)) 85 goto out; 86 87 for (i = 0; i < WDC_G1_REG_NPORTS; i++) { 88 if (bus_space_subregion(wdr.cmd_iot, wdr.cmd_baseioh, i * 4, 89 i == 0 ? 2 : 1, &wdr.cmd_iohs[i]) != 0) 90 goto outunmap; 91 } 92 93 wdc_init_shadow_regs(&wdr); 94 95 wdr.ctl_iot = ga->ga_memt; 96 if (bus_space_map(wdr.ctl_iot, WDC_G1_CTL_ADDR, 97 WDC_G1_AUXREG_NPORTS, 0, &wdr.ctl_ioh)) 98 goto outunmap; 99 100 result = wdcprobe_with_reset(&wdr, wdc_g1_do_reset); 101 102 bus_space_unmap(wdr.ctl_iot, wdr.ctl_ioh, WDC_G1_AUXREG_NPORTS); 103 outunmap: 104 bus_space_unmap(wdr.cmd_iot, wdr.cmd_baseioh, WDC_G1_REG_NPORTS); 105 out: 106 return result; 107 } 108 109 static void 110 wdc_g1_attach(struct device *parent, struct device *self, void *aux) 111 { 112 struct wdc_g1_softc *sc = device_private(self); 113 struct wdc_regs *wdr; 114 struct g1bus_attach_args *ga = aux; 115 int i; 116 117 sc->sc_wdcdev.sc_atac.atac_dev = self; 118 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs; 119 120 wdr->cmd_iot = ga->ga_memt; 121 wdr->ctl_iot = ga->ga_memt; 122 if (bus_space_map(wdr->cmd_iot, WDC_G1_CMD_ADDR, 123 WDC_G1_REG_NPORTS * 4, 0, &wdr->cmd_baseioh) || 124 bus_space_map(wdr->ctl_iot, WDC_G1_CTL_ADDR, 125 WDC_G1_AUXREG_NPORTS, 0, &wdr->ctl_ioh)) { 126 aprint_error(": couldn't map registers\n"); 127 return; 128 } 129 130 for (i = 0; i < WDC_G1_REG_NPORTS; i++) { 131 if (bus_space_subregion(wdr->cmd_iot, 132 wdr->cmd_baseioh, i * 4, i == 0 ? 2 : 1, 133 &wdr->cmd_iohs[i]) != 0) { 134 aprint_error(": couldn't subregion registers\n"); 135 return; 136 } 137 } 138 139 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA; 140 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 141 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 142 sc->wdc_chanlist[0] = &sc->ata_channel; 143 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist; 144 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 145 sc->sc_wdcdev.wdc_maxdrives = 2; 146 sc->sc_wdcdev.reset = wdc_g1_do_reset; 147 sc->ata_channel.ch_channel = 0; 148 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 149 150 wdc_init_shadow_regs(wdr); 151 152 aprint_normal(": %s\n", sysasic_intr_string(SYSASIC_IRL9)); 153 154 sysasic_intr_establish(SYSASIC_EVENT_GDROM, IPL_BIO, SYSASIC_IRL9, 155 wdc_g1_intr, &sc->ata_channel); 156 157 wdcattach(&sc->ata_channel); 158 } 159 160 int 161 wdc_g1_intr(void *arg) 162 { 163 164 return wdcintr(arg); 165 } 166 167 /* 168 * This does what the generic wdc_do_reset() does, with additional 169 * GD-ROM reset. GD-ROM is a very early ATAPI device appeared in 1998 170 * and it doesn't reset itself by the WDCTL_RST in AUX_CTLR but requires 171 * ATAPI_SOFT_RESET command to reset whole device as a master. 172 */ 173 static void 174 wdc_g1_do_reset(struct ata_channel *chp, int poll) 175 { 176 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 177 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 178 int s = 0; 179 180 if (poll != 0) 181 s = splbio(); 182 183 /* master */ 184 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 185 WDSD_IBM); 186 delay(10); /* 400ns delay */ 187 /* assert SRST, wait for reset to complete */ 188 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 189 WDCTL_RST | WDCTL_4BIT | WDCTL_IDS); 190 delay(2000); 191 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 192 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 193 WDCTL_4BIT | WDCTL_IDS); 194 delay(10); /* 400ns delay */ 195 196 /* reset GD-ROM at master via ATAPI command */ 197 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 198 WDSD_IBM); 199 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 200 ATAPI_SOFT_RESET); 201 delay(100 * 1000); 202 203 if (poll != 0) 204 splx(s); 205 } 206
Indexes created Tue Sep 30 17:09:57 GMT 2025